{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T11:46:31Z","timestamp":1759146391892,"version":"3.28.0"},"reference-count":9,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2004]]},"DOI":"10.1109\/icpr.2004.1334338","type":"proceedings-article","created":{"date-parts":[[2004,11,8]],"date-time":"2004-11-08T16:27:50Z","timestamp":1099931270000},"page":"801-804 Vol.1","source":"Crossref","is-referenced-by-count":19,"title":["An FPGA-based architecture for real time image feature extraction"],"prefix":"10.1109","author":[{"given":"D.G.","family":"Bariamis","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"D.K.","family":"Iakovidis","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"D.E.","family":"Maroulis","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"S.A.","family":"Karkanis","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"doi-asserted-by":"publisher","key":"3","DOI":"10.1016\/S0169-2607(02)00007-X"},{"year":"2002","author":"hennesy","journal-title":"Computer Architecture A Quantitative Approach","key":"2"},{"doi-asserted-by":"publisher","key":"1","DOI":"10.1109\/TSMC.1973.4309314"},{"key":"7","first-page":"1418","article-title":"A face\/object recognition system using FPGA implementation of coarse region segmentation","author":"nakano","year":"2003","journal-title":"SICE Annual Conference 2003"},{"key":"6","doi-asserted-by":"crossref","first-page":"1633","DOI":"10.1109\/ICNN.1995.488863","article-title":"Implementation of simplified multilayer neural network with on-chip learning","volume":"4","author":"hikawa","year":"1999","journal-title":"Proc of the IEEE International Conference on Neural Networks (Part 4)"},{"doi-asserted-by":"publisher","key":"5","DOI":"10.1109\/ICIP.2001.958084"},{"year":"1998","author":"luk","journal-title":"Field-Programmable Logic From FPGAs to Computing Paradigm","key":"4"},{"year":"1997","author":"chang","journal-title":"Digital Design and Modeling with VHDL and Synthesis","key":"9"},{"doi-asserted-by":"publisher","key":"8","DOI":"10.1109\/ICIAP.1999.797582"}],"event":{"name":"Proceedings of the 17th International Conference on Pattern Recognition, 2004. ICPR 2004.","start":{"date-parts":[[2004,8,26]]},"location":"Cambridge, UK","end":{"date-parts":[[2004,8,26]]}},"container-title":["Proceedings of the 17th International Conference on Pattern Recognition, 2004. ICPR 2004."],"original-title":[],"link":[{"URL":"https:\/\/summer-heart-0930.chufeiyun1688.workers.dev:443\/http\/xplorestaging.ieee.org\/ielx5\/9258\/29385\/01334338.pdf?arnumber=1334338","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,16]],"date-time":"2017-06-16T11:36:52Z","timestamp":1497613012000},"score":1,"resource":{"primary":{"URL":"https:\/\/summer-heart-0930.chufeiyun1688.workers.dev:443\/http\/ieeexplore.ieee.org\/document\/1334338\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2004]]},"references-count":9,"URL":"https:\/\/summer-heart-0930.chufeiyun1688.workers.dev:443\/https\/doi.org\/10.1109\/icpr.2004.1334338","relation":{},"subject":[],"published":{"date-parts":[[2004]]}}}