{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T05:37:58Z","timestamp":1740116278588,"version":"3.37.3"},"reference-count":21,"publisher":"World Scientific Pub Co Pte Ltd","issue":"08","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2018,7]]},"abstract":"<jats:p> We present an analytical approach that is based on nonlinear programming to perform VLSI standard cell placement. Our method first clusters a netlist to reduce the number of cells and then performs quadratic optimization on the reduced netlist. Finally, it uses Nesterov\u2019s method for solving nonlinear equations for the problem. The framework of our tool, Kapees3, is scalable and generates high quality results. The experimental results for Peko Suite 1 and Peko Suite 2 benchmarks show promising improvements. Our placement tool outperforms NTUPlace3, Dragon, Feng Shui, Capo10.5, by 46%, 57%, 48% and 25%, respectively, on PEKO Suite 1. For PEKO Suite 2, our placement tool outperforms NTUPlace3, Dragon, Feng Shui, Capo10.5 and mPL6 by 30%, 47%, 57%, 69% and 2.7%, respectively. On MMS benchmarks, we obtain wirelength improvement over Capo10.5 by 56.62%, FLOP by 7.84%, FastPlace by 11.55%, ComPLx by 4.58%, POLAR by 23.67%, mPL6 by 9.96% and NTUPlace3-Unified by 2.96%. <\/jats:p>","DOI":"10.1142\/s0218126618501220","type":"journal-article","created":{"date-parts":[[2017,11,26]],"date-time":"2017-11-26T21:39:29Z","timestamp":1511732369000},"page":"1850122","source":"Crossref","is-referenced-by-count":0,"title":["<i>Kapees3<\/i>: A High-Quality VLSI Placement Tool Using Nesterov\u2019s Method for Density Penalty"],"prefix":"10.1142","volume":"27","author":[{"ORCID":"https:\/\/summer-heart-0930.chufeiyun1688.workers.dev:443\/https\/orcid.org\/0000-0001-9235-7928","authenticated-orcid":false,"given":"Sameer","family":"Pawanekar","sequence":"first","affiliation":[{"name":"Department of Electronics and Electrical Engineering, Indian Institute of Technology Guwahati, India"}]},{"given":"Kalpesh","family":"Kapoor","sequence":"additional","affiliation":[{"name":"Department of Mathematics, Indian Institute of Technology Guwahati, India"}]},{"given":"Gaurav","family":"Trivedi","sequence":"additional","affiliation":[{"name":"Department of Electronics and Electrical Engineering, Indian Institute of Technology Guwahati, India"}]}],"member":"219","published-online":{"date-parts":[[2018,4,12]]},"reference":[{"key":"S0218126618501220BIB001","doi-asserted-by":"publisher","DOI":"10.1201\/9781420013481"},{"volume-title":"Computers and Intractability; A Guide to the Theory of NP-Completeness","year":"1990","author":"Garey M. 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