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ORCIDXiaolong Guo 0001
Person information
- affiliation: Kansas State University, Manhattan, KS, USA
- affiliation: University of Florida, Department of Electrical and Computer Engineering, FL, USA
Other persons with the same name
- Xiaolong Guo — disambiguation page
- Xiaolong Guo 0002
![[0000-0002-1261-6852]](https://dblp.org/img/orcid-mark.12x12.png "0000-0002-1261-6852")
— University of Science and Technology of China (USTC), International Institute of Finance, School of Management, Hefei, China
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2020 – today
- 2026
[i6]Zhaoxiang Liu, Samuel Judson, Raj Gautam Dutta, Mark Santolucito, Xiaolong Guo, Ning Luo:
BlindMarket: Enabling Verifiable, Confidential, and Traceable IP Core Distribution in Zero-Trust Settings. CoRR abs/2603.22685 (2026)- 2025
- [j15]Zhenjiao Du, Weimin Fu, Xiaolong Guo, Doina Caragea, Yonghui Li:
FusionESP: Improved Enzyme-Substrate Pair Prediction by Fusing Protein and Chemical Knowledge. J. Chem. Inf. Model. 65(6): 2806-2817 (2025) - [j14]Weimin Fu, Shijie Li, Yifang Zhao, Kaichen Yang, Xuan Zhang, Yier Jin, Xiaolong Guo:
A Generalize Hardware Debugging Approach for Large Language Models Semi-Synthetic, Datasets. IEEE Trans. Circuits Syst. I Regul. Pap. 72(2): 623-636 (2025) - [j13]Qizhi Zhang, Ya Gao, Haocheng Ma, Jiaji He, Yiqiang Zhao, Xiaolong Guo:
Boosting Cryptographic ICs' Side-Channel Resistance: A Formal Framework for Automatic Identification and Protection of Leaky Paths. ACM Trans. Embed. Comput. Syst. 24(6): 157:1-157:25 (2025) - [c40]Weimin Fu, Zelin Lu, Gang Qu, Xiaolong Guo:
Rethinking LLM Safety on Edge Devices: Unearthing Hidden Vulnerabilities through Power Stress. AsianHOST 2025: 1-6 - [c39]Shijie Li, Weimin Fu, Yifang Zhao, Xiaolong Guo, Yier Jin:
Fixbench-RTL: A Comprehensive Benchmark for Evaluating LLMs on RTL Debugging. AsianHOST 2025: 1-6 - [c38]Yifang Zhao, Weimin Fu, Yixiang Hu, Shijie Li, Xiaolong Guo, Yier Jin:
Leveraging Large Language Models for Secure Hardware Verification and Analysis. AsianHOST 2025: 1-4 - [c37]Jian Gao, Weimin Fu, Xiaolong Guo, Weidong Cao, Xuan Zhang:
EVA: An Efficient and Versatile Generative Engine for Targeted Discovery of Novel Analog Circuits. DAC 2025: 1-7 - [c36]Yifang Zhao, Weimin Fu, Shijie Li, Yixiang Hu, Xiaolong Guo, Yier Jin:
Hardware Generation with High Flexibility using Reinforcement Learning Enhanced LLMs. DAC 2025: 1-7 - [c35]Weimin Fu, Shijie Li, Yier Jin, Xiaolong Guo:
HWFixBench: Benchmarking Tools for Hardware Understanding and Fault Repair. ACM Great Lakes Symposium on VLSI 2025: 427-434 - [c34]Shijie Li, Weimin Fu, Yifang Zhao, Xiaolong Guo, Yier Jin:
Intelligence In The Fence: Construct A Privacy and Reliable Hardware Design Assistant LLM. ACM Great Lakes Symposium on VLSI 2025: 659-666 - [c33]Ruochen Dai, Zhaoxiang Liu, Orlando Arias, Xiaolong Guo, Tuba Yavuz:
Evaluating the Effectiveness of Hardware Trojan Detection Approaches at RTL. HOST 2025: 250-260 - [c32]Weimin Fu, Shijie Li, Kaichen Yang, Xuan Silvia Zhang, Yier Jin, Xiaolong Guo:
Building Reasoning LLMs for Hardware Design Generation via Function-Aligned Differentiated Revision. ICCAD 2025: 1-8 - [c31]Yifang Zhao, Weimin Fu, Shijie Li, Yixiang Hu, Xiaolong Guo, Yier Jin:
Enhancing LLM Performance on Hardware Design Generation Task via Reinforcement Learning. ISCAS 2025: 1-5 - [c30]Hanqiu Wang, Ruochen Dai, Tuba Yavuz, Xiaolong Guo, Orlando Arias, Dean Sullivan, Michael Lee, Honggang Yu, Siqi Dai, Domenic Forte, Shuo Wang:
Cross-Layer EM Fault Injection Assessment Framework. ISQED 2025: 1-8 - [c29]Weimin Fu, Yiting Wang, Zelin Lu, Xiaolong Guo, Gang Qu:
HADA: Leveraging Multi-Source Data to Train Large Language Models for Hardware Security Assertion Generation. MLCAD 2025: 1-7 - [i5]Zining Wang, Jian Gao, Weimin Fu, Xiaolong Guo, Xuan Zhang:
AnalogSAGE: Self-evolving Analog Design Multi-Agents with Stratified Memory and Grounded Experience. CoRR abs/2512.22435 (2025) - 2024
- [j12]Huifeng Zhu, Xiaolong Guo, Yier Jin, Xuan Zhang:
PowerScout: Security-Oriented Power Delivery Network Modeling for Side-Channel Vulnerability Analysis. IEEE Trans. Emerg. Top. Comput. 12(2): 532-545 (2024) - [c28]Weimin Fu, Shijie Li, Yifang Zhao, Haocheng Ma, Raj Gautam Dutta, Xuan Zhang, Kaichen Yang, Yier Jin, Xiaolong Guo:
Hardware Phi-1.5B: A Large Language Model Encodes Hardware Domain Specific Knowledge. ASPDAC 2024: 349-354 - [c27]Zhaoxiang Liu, Kejun Chen, Dean Sullivan, Orlando Arias, Raj Gautam Dutta, Yier Jin, Xiaolong Guo:
Microscope: Causality Inference Crossing the Hardware and Software Boundary from Hardware Perspective. ASPDAC 2024: 933-938 - [c26]Zhaoxiang Liu, Ning Luo, Samuel Judson, Raj Gautam Dutta, Xiaolong Guo, Mark Santolucito:
Poster: BlindMarket: A Trustworthy Chip Designs Marketplace for IP Vendors and Users. CCS 2024: 5048-5050 - [c25]Weimin Fu, Yifang Zhao, Yier Jin, Xiaolong Guo:
Poster: Enhance Hardware Domain Specific Large Language Model with Reinforcement Learning for Resilience. CCS 2024: 5060-5062 - [c24]Ruochen Dai, Zhaoxiang Liu, Orlando Arias, Xiaolong Guo, Tuba Yavuz:
DTjRTL: A Configurable Framework for Automated Hardware Trojan Insertion at RTL. ACM Great Lakes Symposium on VLSI 2024: 465-470 - [i4]Weimin Fu, Kaichen Yang, Raj Gautam Dutta, Xiaolong Guo, Gang Qu:
LLM4SecHW: Leveraging Domain Specific Large Language Model for Hardware Debugging. CoRR abs/2401.16448 (2024) - [i3]Weimin Fu, Shijie Li, Yifang Zhao, Haocheng Ma, Raj Gautam Dutta, Xuan Zhang, Kaichen Yang, Yier Jin, Xiaolong Guo:
Hardware Phi-1.5B: A Large Language Model Encodes Hardware Domain Specific Knowledge. CoRR abs/2402.01728 (2024) - 2023
- [j11]Kejun Chen, Orlando Arias, Xiaolong Guo, Qingxu Deng, Yier Jin:
IP-Tag: Tag-Based Runtime 3PIP Hardware Trojan Detection in SoC Platforms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(1): 68-81 (2023) - [j10]Huifeng Zhu, Haoqi Shan, Dean Sullivan, Xiaolong Guo, Yier Jin, Xuan Zhang:
PDNPulse: Sensing PCB Anomaly With the Intrinsic Power Delivery Network. IEEE Trans. Inf. Forensics Secur. 18: 3590-3605 (2023) - [c23]Weimin Fu, Kaichen Yang, Raj Gautam Dutta, Xiaolong Guo, Gang Qu:
LLM4SecHW: Leveraging Domain-Specific Large Language Model for Hardware Debugging. AsianHOST 2023: 1-6 - [i2]Ruochen Dai, Michael Lee, Patrick Hoey, Weimin Fu, Tuba Yavuz, Xiaolong Guo, Shuo Wang, Dean Sullivan, Orlando Arias:
VGF: Value-Guided Fuzzing - Fuzzing Hardware as Hardware. CoRR abs/2312.06580 (2023) - 2022
- [j9]Jiaji He, Xiaolong Guo, Mark Tehranipoor, Apostol Vassilev, Yier Jin:
EM Side Channels in Hardware Security: Attacks and Defenses. IEEE Des. Test 39(2): 100-111 (2022) - [j8]Jiaji He, Haocheng Ma, Max Panoff, Hanning Wang, Yiqiang Zhao, Leibo Liu, Xiaolong Guo, Yier Jin:
Security Oriented Design Framework for EM Side-Channel Protection in RTL Implementations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(8): 2421-2434 (2022) - [j7]Kejun Chen, Orlando Arias, Qingxu Deng, Daniela Oliveira, Xiaolong Guo, Yier Jin:
FineDIFT: Fine-Grained Dynamic Information Flow Tracking for Data-Flow Integrity Using Coprocessor. IEEE Trans. Inf. Forensics Secur. 17: 559-573 (2022) - [c22]Orlando Arias, Zhaoxiang Liu, Xiaolong Guo, Yier Jin, Shuo Wang:
RTSEC: Automated RTL Code Augmentation for Hardware Security Enhancement. DATE 2022: 596-599 - [c21]Zhaoxiang Liu, Orlando Arias, Weimin Fu, Yier Jin, Xiaolong Guo:
Inter-IP Malicious Modification Detection through Static Information Flow Tracking. DATE 2022: 600-603 - [c20]Weimin Fu, Honggang Yu, Orlando Arias, Kaichen Yang, Yier Jin, Tuba Yavuz, Xiaolong Guo:
Graph Neural Network based Hardware Trojan Detection at Intermediate Representative for SoC Platforms. ACM Great Lakes Symposium on VLSI 2022: 481-486 - [i1]Huifeng Zhu, Haoqi Shan, Dean Sullivan, Xiaolong Guo, Yier Jin, Xuan Zhang:
PDNPulse: Sensing PCB Anomaly with the Intrinsic Power Delivery Network. CoRR abs/2204.02482 (2022) - 2021
- [c19]Huifeng Zhu, Xiaolong Guo, Yier Jin, Xuan Zhang:
PCBench: Benchmarking of Board-Level Hardware Attacks and Trojans. ASP-DAC 2021: 396-401 - [c18]Yichen Jiang, Huifeng Zhu, Dean Sullivan, Xiaolong Guo, Xuan Zhang, Yier Jin:
Quantifying Rowhammer Vulnerability for DRAM Security. DAC 2021: 73-78 - [c17]Xiaolong Guo, Song Han, X. Sharon Hu, Xun Jiao, Yier Jin, Fanxin Kong, Michael Lemmon:
Towards scalable, secure, and smart mission-critical IoT systems: review and vision. EMSOFT 2021: 1-10 - [c16]Yichen Jiang, Huifeng Zhu, Haoqi Shan, Xiaolong Guo, Xuan Zhang, Yier Jin:
TRRScope: Understanding Target Row Refresh Mechanism for Modern DDR Protection. HOST 2021: 239-247 - [c15]Weimin Fu, Orlando Arias, Yier Jin, Xiaolong Guo:
Fuzzing Hardware: Faith or Reality? : Invited Paper. NANOARCH 2021: 1-6 - 2020
- [c14]Qizhi Zhang, Jiaji He, Yiqiang Zhao, Xiaolong Guo:
A Formal Framework for Gate- Level Information Leakage Using Z3. AsianHOST 2020: 1-6 - [c13]Huifeng Zhu, Xiaolong Guo, Yier Jin, Xuan Zhang:
PowerScout: A Security-Oriented Power Delivery Network Modeling Framework for Cross-Domain Side-Channel Analysis. AsianHOST 2020: 1-6 - [c12]Jiaji He, Haocheng Ma, Xiaolong Guo, Yiqiang Zhao, Yier Jin:
Design for EM Side-Channel Security through Quantitative Assessment of RTL Implementations. ASP-DAC 2020: 62-67 - [c11]Jiaji He, Xiaolong Guo, Haocheng Ma, Yanjiang Liu, Yiqiang Zhao, Yier Jin:
Runtime Trust Evaluation and Hardware Trojan Detection Using On-Chip EM Sensors. DAC 2020: 1-6
2010 – 2019
- 2019
- [j6]Jiaji He, Xiaolong Guo, Travis Meade, Raj Gautam Dutta, Yiqiang Zhao, Yier Jin:
SoC interconnection protection through formal verification. Integr. 64: 143-151 (2019) - [c10]Xiaolong Guo, Huifeng Zhu, Yier Jin, Xuan Zhang:
When Capacitors Attack: Formal Method Driven Design and Detection of Charge-Domain Trojans. DATE 2019: 1727-1732 - [c9]Xiaolong Guo, Raj Gautam Dutta, Jiaji He, Mark Tehranipoor, Yier Jin:
QIF-Verilog: Quantitative Information-Flow based Hardware Description Languages for Pre-Silicon Security Assessment. HOST 2019: 91-100 - [c8]Kejun Chen, Qingxu Deng, Yumin Hou, Yier Jin, Xiaolong Guo:
Hardware and Software Co-Verification from Security Perspective. MTV 2019: 50-55 - 2017
- [j5]Xiaolong Guo, Raj Gautam Dutta, Yier Jin:
Eliminating the Hardware-Software Boundary: A Proof-Carrying Approach for Trust Evaluation on Computer Systems. IEEE Trans. Inf. Forensics Secur. 12(2): 405-417 (2017) - [j4]Yier Jin, Xiaolong Guo, Raj Gautam Dutta, Mohammad-Mahdi Bidmeshki, Yiorgos Makris:
Data Secrecy Protection Through Information Flow Tracking in Proof-Carrying Hardware IP - Part I: Framework Fundamentals. IEEE Trans. Inf. Forensics Secur. 12(10): 2416-2429 (2017) - [j3]Mohammad-Mahdi Bidmeshki, Xiaolong Guo, Raj Gautam Dutta, Yier Jin, Yiorgos Makris:
Data Secrecy Protection Through Information Flow Tracking in Proof-Carrying Hardware IP - Part II: Framework Automation. IEEE Trans. Inf. Forensics Secur. 12(10): 2430-2443 (2017) - [j2]Jiaji He, Yiqiang Zhao, Xiaolong Guo, Yier Jin:
Hardware Trojan Detection Through Chip-Free Electromagnetic Side-Channel Statistical Analysis. IEEE Trans. Very Large Scale Integr. Syst. 25(10): 2939-2948 (2017) - [j1]Xiaolong Guo, Raj Gautam Dutta, Prabhat Mishra, Yier Jin:
Automatic Code Converter Enhanced PCH Framework for SoC Trust Verification. IEEE Trans. Very Large Scale Integr. Syst. 25(12): 3390-3400 (2017) - [c7]Xiaolong Guo, Raj Gautam Dutta, Jiaji He, Yier Jin:
PCH framework for IP runtime security verification. AsianHOST 2017: 79-84 - [c6]Raj Gautam Dutta, Xiaolong Guo, Teng Zhang, Kevin A. Kwiat, Charles A. Kamhoua, Laurent Njilla, Yier Jin:
Estimation of Safe Sensor Measurements of Autonomous System Under Attack. DAC 2017: 46:1-46:6 - 2016
- [c5]Xiaolong Guo, Raj Gautam Dutta, Prabhat Mishra, Yier Jin:
Scalable SoC trust verification using integrated theorem proving and model checking. HOST 2016: 124-129 - [c4]Xiaolong Guo, Raj Gautam Dutta, Prabhat Mishra, Yier Jin:
Automatic RTL-to-Formal Code Converter for IP Security Formal Verification. MTV 2016: 35-38 - [c3]Raj Gautam Dutta, Xiaolong Guo, Yier Jin:
Quantifying trust in autonomous system under uncertainties. SoCC 2016: 362-367 - 2015
- [c2]Xiaolong Guo, Raj Gautam Dutta, Yier Jin, Farimah Farahmandi, Prabhat Mishra:
Pre-silicon security verification and validation: a formal perspective. DAC 2015: 145:1-145:6 - [c1]Xiaolong Guo, Raj Gautam Dutta, Yier Jin:
Hierarchy-Preserving Formal Verification Methods for Pre-silicon Security Assurance. MTV 2015: 48-53
Coauthor Index
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last updated on 2026-04-17 00:23 CEST by the dblp team
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