Thermal impact of extreme die thinning in bump-bonded three-dimensional integrated circuits.

Shunsuke Nemoto

Samson Melamed Naoya Watanabe Shunsuke Nemoto Haruo Shimamoto Katsuya Kikuchi Masahiro Aoyagi Thermal impact of extreme die thinning in bump-bonded three-dimensional integrated circuits. 380-386 2017 79 Microelectron. Reliab. https://doi.org/10.1016/j.microrel.2017.05.030 db/journals/mr/mr79.html#MelamedWNSKA17

Samson Melamed Naoya Watanabe Shunsuke Nemoto Haruo Shimamoto Katsuya Kikuchi Masahiro Aoyagi Impact of thinning stacked dies on the thermal resistance of bump-bonded three-dimensional integrated circuits. 2-8 2016 67 Microelectron. Reliab. https://doi.org/10.1016/j.microrel.2016.08.015 db/journals/mr/mr67.html#MelamedWNSKA16

Masahiro Aoyagi Naoya Watanabe Motohiro Suzuki Katsuya Kikuchi Shunsuke Nemoto Noriaki Arima Misaki Ishizuka Koji Suzuki Toshio Shiomi New optical three dimensional structure measurement method of cone shape micro bumps used for 3D LSI chip stacking. 1-5 2013 3DIC https://doi.org/10.1109/3DIC.2013.6702388 conf/3dic/2013 db/conf/3dic/3dic2013.html#AoyagiWSKNAISS13 Katsuya Kikuchi Fumiki Kato Shunsuke Nemoto Hiroshi Nakagawa Masahiro Aoyagi Youtaro Yasu Kohji Koshiji Investigation of optimized high-density flip-chip interconnect design including micro Au bumps for 3-D stacked LSI packaging. 1-4 2013 3DIC https://doi.org/10.1109/3DIC.2013.6702401 conf/3dic/2013 db/conf/3dic/3dic2013.html#KikuchiKNNAYK13

Hiroo Sekiya Shunsuke Nemoto Jianming Lu Takashi Yahagi Phase control for resonant DC-DC converter with class-DE inverter and class-E rectifier. 254-263 2006 53-I IEEE Trans. Circuits Syst. I Regul. Pap. 2 https://doi.org/10.1109/TCSI.2005.855741 db/journals/tcas/tcasI53.html#SekiyaNLY06

Masahiro Aoyagi Noriaki Arima Misaki Ishizuka Fumiki Kato Katsuya Kikuchi Kohji Koshiji Jianming Lu Samson Melamed Hiroshi Nakagawa Hiroo Sekiya Haruo Shimamoto Toshio Shiomi Koji Suzuki Motohiro Suzuki Naoya Watanabe Takashi Yahagi Youtaro Yasu