Invited: Post-Placement Buffering and Sizing Contest.

Yiting Liu 0002 https://orcid.org/0000-0001-8078-6717 University of California San Diego, La Jolla, CA, USA Yiting Liu Yiting Liu 0001 https://orcid.org/0009-0003-0846-7377 Nanjing University of Science and Technology, Nanjing, China Yiting Liu 0003 https://orcid.org/0009-0009-7429-1545 Tongji University, Shanghai, China Yiting Liu 0004 https://orcid.org/0000-0002-1498-5715 Xidian University, Guangzhou, China Yiting Liu 0005 https://orcid.org/0000-0003-1837-0301 Henan Key Laboratory of Network Cryptography Technology, Zhengzhou, Henan, China Yiting Liu 0006 https://orcid.org/0009-0008-6440-2195 National Computer Engineering Research Institute of China, Beijing, China Yiting Liu 0007 https://orcid.org/0000-0001-8736-1498 Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China Yiting Liu 0008 https://orcid.org/0009-0002-9475-0648 Wuhan University, Wuhan, China Yiting Liu 0009 https://orcid.org/0009-0006-9554-8205 Bern University of Applied Sciences, Bern, Switzerland Andrew B. Kahng Seokhyeong Kang Sayak Kundu Yiting Liu 0002 Davit Markarian Seonghyeon Park Zhiang Wang Invited: Post-Placement Buffering and Sizing Contest. 256-262 2026 ISPD https://doi.org/10.1145/3764386.3779616 conf/ispd/2026 db/conf/ispd/ispd2026.html#KahngKKLMPW26

Yiting Liu 0002 Hai Zhou 0001 Jia Wang 0003 Fan Yang 0001 Xuan Zeng 0001 Li Shang 0002 An Efficient Placement Speedup Technique Based on Graph Signal Processing. 3924-3937 2025 October 44 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10 https://doi.org/10.1109/TCAD.2025.3556968 db/journals/tcad/tcad44.html#LiuZWYZS25 streams/journals/tcad

Amur Ghose Andrew B. Kahng Sayak Kundu Yiting Liu 0002 Bodhisatta Pramanik Zhiang Wang Dooseok Yoon Use Cases and Deployment of ML in IC Physical Design. 669-675 2025 ASP-DAC https://doi.org/10.1145/3658617.3703143 conf/aspdac/2025 db/conf/aspdac/aspdac2025.html#GhoseKKLPWY25 Vidya A. Chhabria Amur Ghose Vikram Gopalakrishnan Andrew B. Kahng Sayak Kundu Yiting Liu 0002 Zhiang Wang Bing-Yue Wu Invited: IEEE DATC RDF-2025: Enabling an EDA Research Ecosystem. 1-9 2025 ICCAD https://doi.org/10.1109/ICCAD66269.2025.11240743 conf/iccad/2025 db/conf/iccad/iccad2025.html#ChhabriaGGKKLWW25 streams/conf/iccad Andrew B. Kahng Yiting Liu 0002 Zhiang Wang Recursive Learning-Based Virtual Buffering for Analytical Global Placement. 1-11 2025 MLCAD https://doi.org/10.1109/MLCAD65511.2025.11189114 conf/mlcad/2025 db/conf/mlcad/mlcad2025.html#KahngLW25 streams/conf/mlcad

Yiting Liu 0002 Hai Zhou 0001 Jia Wang 0003 Fan Yang 0001 Xuan Zeng 0001 Li Shang The Power of Graph Signal Processing for Chip Placement Acceleration. 2025 February abs/2502.17632 CoRR https://doi.org/10.48550/arXiv.2502.17632 db/journals/corr/corr2502.html#abs-2502-17632 streams/journals/corr

Andrew B. Kahng Yiting Liu 0002 Zhiang Wang Recursive Learning-Based Virtual Buffering for Analytical Global Placement. 2025 June abs/2506.17247 CoRR https://doi.org/10.48550/arXiv.2506.17247 db/journals/corr/corr2506.html#abs-2506-17247 streams/journals/corr

Yiting Liu 0002 Hai Zhou 0001 Jia Wang 0003 Fan Yang 0001 Xuan Zeng 0001 Li Shang Hierarchical Graph Learning-Based Floorplanning With Dirichlet Boundary Conditions. 810-822 2024 May 32 IEEE Trans. Very Large Scale Integr. Syst. 5 https://doi.org/10.1109/TVLSI.2024.3363666 db/journals/tvlsi/tvlsi32.html#LiuZWYZS24

Zihao Chen Jiangli Huang Yiting Liu 0002 Fan Yang 0001 Li Shang 0001 Dian Zhou Xuan Zeng 0001 Artisan: Automated Operational Amplifier Design via Domain-specific Large Language Model. 39:1-39:6 2024 DAC https://doi.org/10.1145/3649329.3655903 conf/dac/2024 db/conf/dac/dac2024.html#ChenHL0SZ024 Yiting Liu 0002 Hai Zhou 0001 Jia Wang 0003 Fan Yang 0001 Xuan Zeng 0001 Li Shang 0001 The Power of Graph Signal Processing for Chip Placement Acceleration. 132:1-132:8 2024 ICCAD https://doi.org/10.1145/3676536.3676669 conf/iccad/2024 db/conf/iccad/iccad2024.html#LiuZWYZS24 Hongyang Pan Cunqing Lan Yiting Liu 0002 Zhiang Wang Li Shang 0001 Xuan Zeng 0001 Fan Yang 0001 Keren Zhu 0001 Physically Aware Synthesis Revisited: Guiding Technology Mapping with Primitive Logic Gate Placement. 171:1-171:9 2024 ICCAD https://doi.org/10.1145/3676536.3676676 conf/iccad/2024 db/conf/iccad/iccad2024.html#PanLLWS00024

Hongyang Pan Cunqing Lan Yiting Liu 0002 Zhiang Wang Li Shang 0001 Xuan Zeng 0001 Fan Yang 0001 Keren Zhu 0001 Physically Aware Synthesis Revisited: Guiding Technology Mapping with Primitive Logic Gate Placement. 2024 abs/2408.07886 CoRR https://doi.org/10.48550/arXiv.2408.07886 db/journals/corr/corr2408.html#abs-2408-07886 streams/journals/corr

Yiting Liu 0002 Ziyi Ju Zhengming Li Mingzhi Dong Hai Zhou 0001 Jia Wang 0003 Fan Yang 0001 Xuan Zeng 0001 Li Shang 0001 GraphPlanner: Floorplanning with Graph Neural Network. 21:1-21:24 2023 March 28 ACM Trans. Design Autom. Electr. Syst. 2 https://doi.org/10.1145/3555804 https://www.wikidata.org/entity/Q130953694 db/journals/todaes/todaes28.html#LiuJLDZWYZS23

Yiting Liu 0002 Ziyi Ju Zhengming Li Mingzhi Dong Hai Zhou 0001 Jia Wang 0003 Fan Yang 0001 Xuan Zeng 0001 Li Shang Floorplanning with graph attention. 1303-1308 2022 DAC https://doi.org/10.1145/3489517.3530484 conf/dac/2022 db/conf/dac/dac2022.html#LiuJLDZWY0S22 Zihao Chen Vidya A. Chhabria Mingzhi Dong Amur Ghose Vikram Gopalakrishnan Jiangli Huang Ziyi Ju Andrew B. Kahng Seokhyeong Kang Sayak Kundu Cunqing Lan Zhengming Li Davit Markarian Hongyang Pan Seonghyeon Park Bodhisatta Pramanik Li Shang Li Shang 0001 Li Shang 0002 Jia Wang 0003 Zhiang Wang Bing-Yue Wu Fan Yang 0001 Dooseok Yoon Xuan Zeng 0001 Dian Zhou Hai Zhou 0001 Keren Zhu 0001