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2020 – today
- 2026
[j9]Zhuoheng Ran
, Xinmin Meng, Chong Wu, Zewen Ye, Ray C. C. Cheung, Hong Yan:
RO-SVD+: A Hardware-Based Framework Against AI Attacks for Cost-Effective GenAI Copyright Protection in Consumer Electronics. IEEE Trans. Consumer Electron. 72(1): 80-93 (2026)- [j8]Tianyu Wang, Zewen Ye, Tianshun Huang, Chengxuan Wang, Kuangye Ying, Kejie Huang:
PipFHE: Resource-Efficient Privacy-Preserving Deep CNN Inference via Padded Batch Packing and Channel Merging over FHE. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2026: 1-25 (2026) - [j7]Zewen Ye, Tianyu Wang, Tianshun Huang, Yonggen Li, Chengxuan Wang, Ray C. C. Cheung, Kejie Huang:
HTCNN: High-Throughput Batch CNN Inference With Homomorphic Encryption. IEEE Trans. Dependable Secur. Comput. 23(2): 2400-2411 (2026) - 2025
- [j6]Zewen Ye, Junhao Huang, Tianshun Huang, Yudan Bai, Jinze Li, Hao Zhang, Guangyan Li, Donglong Chen, Ray C. C. Cheung, Kejie Huang:
PQNTRU: Acceleration of NTRU-Based Schemes via Customized Post-Quantum Processor. IEEE Trans. Computers 74(5): 1649-1662 (2025) - [j5]Yile Xing, Guangyan Li, Zewen Ye, Ryan W. L. Luk, Donglong Chen, Hong Yan, Ray C. C. Cheung:
High-Radix/Mixed-Radix NTT Multiplication Algorithm/Architecture Co-Design Over Fermat Modulus. IEEE Trans. Computers 74(10): 3519-3533 (2025) - [j4]Zewen Ye, Xin Li, Chuhui Wang, Ray C. C. Cheung, Kejie Huang:
RVSLH: Acceleration of Postquantum Standard SLH-DSA With Customized RISC-V Processor. IEEE Trans. Very Large Scale Integr. Syst. 33(7): 1999-2003 (2025) - [c4]Shuaiting Li, Chengxuan Wang, Juncan Deng, Zeyu Wang, Zewen Ye, Zongsheng Wang, Haibin Shen, Kejie Huang:
MVQ: Towards Efficient DNN Compression and Acceleration with Masked Vector Quantization. ASPLOS (1) 2025: 731-745 - [c3]Zhuoheng Ran, Zewen Ye, Chong Wu, Ray C. C. Cheung, Hong Yan:
FastViT: Real-Time Linear Attention Accelerator for Dense Predictions of Vision Transformer (ViT). ISCAS 2025: 1-5 - [c2]Jiuyang Liu, Qinjun Li, Yunqian Luo, Hongbin Zhang, Jiongjia Lu, Shupei Fan, Jianhao Ye, Yang Liu, Xiaoyi Liu, Yanqi Yang, Zewen Ye, Yuhang Zeng, Ao Shen, Rui Huang, Wei Cong, Xuecheng Zou, Mingyu Gao:
Titan-I: An Open-Source, High Performance RISC-V Vector Core. MICRO 2025: 675-690 - [i5]Dan Peng, Zhihui Fu, Zewen Ye, Zhuoran Song, Jun Wang:
Accelerating Prefilling for Long-Context LLMs via Sparse Pattern Sharing. CoRR abs/2505.19578 (2025) - [i4]Hao Zhang, Zewen Ye, Teng Wang, Yuanming Zhang, Tianyu Wang, Chengxuan Wang, Kejie Huang:
A Chosen-Ciphertext Side-Channel Attack on Shuffled CRYSTALS-Kyber. IACR Cryptol. ePrint Arch. 2025: 1956 (2025) - 2024
- [j3]Zewen Ye, Ruibing Song, Hao Zhang, Donglong Chen, Ray Chak-Chung Cheung, Kejie Huang:
A Highly-efficient Lattice-based Post-Quantum Cryptography Processor for IoT Applications. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2024(2): 130-153 (2024) - [j2]Guangyan Li, Zewen Ye, Donglong Chen, Wangchen Dai, Gaoyu Mao, Kejie Huang, Ray C. C. Cheung:
ProgramGalois: A Programmable Generator of Radix-4 Discrete Galois Transformation Architecture for Lattice-Based Cryptography. ACM Trans. Reconfigurable Technol. Syst. 17(4): 53:1-53:32 (2024) - [c1]Chuhui Wang, Zewen Ye, Haibin Shen, Kejie Huang:
A Folded Computation-in-Memory Accelerator for Fast Polynomial Multiplication in BIKE. Euro-Par (2) 2024: 137-151 - [i3]Shuaiting Li, Chengxuan Wang, Juncan Deng, Zeyu Wang, Zewen Ye, Zongsheng Wang, Haibin Shen, Kejie Huang:
MVQ:Towards Efficient DNN Compression and Acceleration with Masked Vector Quantization. CoRR abs/2412.10261 (2024) - [i2]Zewen Ye, Tianshun Huang, Tianyu Wang, Yonggen Li, Chengxuan Wang, Ray C. C. Cheung, Kejie Huang:
HTCNN: High-Throughput Batch CNN Inference with Homomorphic Encryption for Edge Computing. IACR Cryptol. ePrint Arch. 2024: 1753 (2024) - [i1]Zewen Ye, Junhao Huang, Tianshun Huang, Yudan Bai, Jinze Li, Hao Zhang, Guangyan Li, Donglong Chen, Ray C. C. Cheung, Kejie Huang:
PQNTRU: Acceleration of NTRU-based Schemes via Customized Post-Quantum Processor. IACR Cryptol. ePrint Arch. 2024: 1754 (2024) - 2022
- [j1]Zewen Ye, Ray C. C. Cheung, Kejie Huang:
PipeNTT: A Pipelined Number Theoretic Transform Architecture. IEEE Trans. Circuits Syst. II Express Briefs 69(10): 4068-4072 (2022)
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last updated on 2026-04-09 00:41 CEST by the dblp team
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