An Efficient Technique for Leakage Current Estimation in Sub 65nm Scaled CMOS Circuits Based on Loading Effect.

Mon, 01 Jan 2007 00:00:00 +0100

Ashesh Rastogi, Wei Chen, Alodeep Sanyal, Sandip Kundu:
An Efficient Technique for Leakage Current Estimation in Sub 65nm Scaled CMOS Circuits Based on Loading Effect. VLSI Design 2007: 583-588