Performance evaluation on low-latency communication mechanism of DIMMnet-2.

Tomotaka Miyashiro Akira Kitamura Yasuo Miyabe Tomotaka Miyashiro Noboru Tanabe Hironori Nakajo Hideharu Amano Performance evaluation on low-latency communication mechanism of DIMMnet-2. 57-62 2007 conf/pdcn/2007 Parallel and Distributed Computing and Networks db/conf/pdcn/pdcn2007.html#KitamuraMMTNA07 Tomotaka Miyashiro Akira Kitamura Hironori Nakajo Noboru Tanabe DIMMnet-2: A Reconfigurable Board Connected Into a Memory Slot. 1-4 2006 conf/fpl/2006 FPL https://doi.org/10.1109/FPL.2006.311323 db/conf/fpl/fpl2006.html#MiyashiroKNT06 Yasuo Miyabe Akira Kitamura Yoshihiro Hamada Tomotaka Miyashiro Tetsu Izawa Noboru Tanabe Hironori Nakajo Hideharu Amano Implementation and Evaluation of the Mechanisms for Low Latency Communication on DIMMnet-2. 211-218 2005 ISHPC https://doi.org/10.1007/978-3-540-77704-5_18 conf/ishpc/2005 db/conf/ishpc/ishpc2005.html#MiyabeKHMITNA05 Akira Kitamura Yasuo Miyabe Tetsu Izawa Tomotaka Miyashiro Konosuke Watanabe Tomohiro Otsuka Hideharu Amano Yoshihiro Hamada Noboru Tanabe Hironori Nakajo Evaluation of Network Interface Controller on DIMMnet-2 Prototype Board. 778-780 2005 conf/pdcat/2005 PDCAT https://doi.org/10.1109/PDCAT.2005.136 https://doi.ieeecomputersociety.org/10.1109/PDCAT.2005.136 db/conf/pdcat/pdcat2005.html#KitamuraMIMWOAHTN05 Hideharu Amano Yoshihiro Hamada Tetsu Izawa Akira Kitamura Yasuo Miyabe Hironori Nakajo Tomohiro Otsuka Noboru Tanabe Konosuke Watanabe