Embedded wireless delay tolerant networks on chips for segmented architectures.

Pablo A. Ferreyra National University of Córdoba, Argentina

Pablo A. Ferreyra Rubén Danilo Capkob Alberto Fabián Gómez Juan Andres Fraire Carlos José Barrientos Embedded wireless delay tolerant networks on chips for segmented architectures. 578-591 2021 14 Int. J. Embed. Syst. 6 https://doi.org/10.1504/IJES.2021.121087 db/journals/ijes/ijes14.html#FerreyraCGFB21

Pablo A. Ferreyra Juan A. Fraire Fabian Gomez Raoul Velazco Daniel Sánchez 0013 Dardo Vinas Viscardi Delay-Tolerant Wireless Networks on Chip: Preliminary Analysis and Results. 1-6 2019 LATS https://doi.org/10.1109/LATW.2019.8704623 conf/latw/2019 db/conf/latw/lats2019.html#FerreyraFGVSV19 Daniel Sánchez 0013 Pablo A. Ferreyra Juan A. Fraire Fabian Gomez Raoul Velazco Dardo Vinas Viscardi A Wireless Embedded System for Measuring the Effects of Ionizing Radiations. 1-6 2019 LATS https://doi.org/10.1109/LATW.2019.8704607 conf/latw/2019 db/conf/latw/lats2019.html#SanchezFFGVV19 M. Solinas Alexandre Coelho Juan A. Fraire Nacer-Eddine Zergainoh Pablo A. Ferreyra Raoul Velazco Preliminary results of NETFI-2: An automatic method for fault injection on HDL-based designs. 1-4 2017 LATS https://doi.org/10.1109/LATW.2017.7906748 conf/latw/2017 db/conf/latw/lats2017.html#SolinasCFZFV17 Juan A. Fraire Pablo G. Madoery Jorge M. Finochietto Pablo A. Ferreyra Raoul Velazco Internetworking approaches towards along-track segmented satellite architectures. 123-128 2016 WiSEE https://doi.org/10.1109/WiSEE.2016.7877316 conf/wisee/2016 db/conf/wisee/wisee2016.html#FraireMFFV16 Ezequiel Brac Pablo A. Ferreyra Raoul Velazco Carlos A. Marqués Test and qualification of a Fault Tolerant FPGA based Active Antenna System for space applications. 1-5 2009 LATW https://doi.org/10.1109/LATW.2009.4813814 conf/latw/2009 db/conf/latw/latw2009.html#BracFVM09

Javier P. Gaspar Suei Feng Chen Alejandro Gordillo Mateo Hepp Pablo A. Ferreyra Carlos A. Marqués Digital lock in amplifier: study, design and development with a digital signal processor. 157-162 2004 28 Microprocess. Microsystems 4 https://doi.org/10.1016/j.micpro.2003.12.002 db/journals/mam/mam28.html#GasparCGHFM04

Raoul Velazco A. Corominas Pablo A. Ferreyra Injecting Bit Flip Faults by Means of a Purely Software Approach: A Case Studied. 108-116 2002 conf/dft/2002 DFT https://doi.org/10.1109/DFTVS.2002.1173507 https://doi.ieeecomputersociety.org/10.1109/DFTVS.2002.1173507 db/conf/dft/dft2002.html#VelazcoCF02 Pablo A. Ferreyra Carlos A. Marqués Javier P. Gaspar Raul Velazco Ricardo T. Ferreyra SEU-Induced-Fault Detection-Efficiency of a Watch Dog Circuit for a Micro-Satellite on Board Digital Signal Processor System. 106-108 2002 LATW conf/latw/2002 db/conf/latw/latw2002.html#FerreyraMGVF02 Pablo A. Ferreyra Carlos A. Marqués Javier P. Gaspar Ricardo T. Ferreyra A Software Tool for Simulating Single Event Upsets in a Digital Signal Processor. 19-23 2001 LATW conf/latw/2001 db/conf/latw/latw2001.html#FerreyraMGF01 Carlos José Barrientos Ezequiel Brac Rubén Danilo Capkob Suei Feng Chen Alexandre Coelho A. Corominas Ricardo T. Ferreyra Jorge M. Finochietto Juan A. FraireJuan Andres Fraire Javier P. Gaspar Alberto Fabián Gómez Fabian Gomez Alejandro Gordillo Mateo Hepp Pablo G. Madoery Carlos A. Marqués Daniel Sánchez 0013 M. Solinas Raoul Velazco Raul Velazco Dardo Vinas Viscardi Nacer-Eddine Zergainoh