U-UTM: A Cyber-Physical System for Road Traffic Monitoring Using UAVs.

Mazad S. Zaveri Mazad Zaveri https://orcid.org/0000-0002-3840-8373 https://www.wikidata.org/entity/Q83201108 Yagnik M. Bhavsar Mazad S. Zaveri Mehul S. Raval Shaheriar B. Zaveri U-UTM: A Cyber-Physical System for Road Traffic Monitoring Using UAVs. 1-6 2024 ICVES https://doi.org/10.1109/ICVES61986.2024.10927911 conf/icves/2024 db/conf/icves/icves2024.html#BhavsarZRZ24

Ankur Changela Mazad Zaveri Yogesh Kumar 0002 A New Angle Set-Based Absolute Scaling-free Reconfigurable Cordic Algorithm. 7404-7432 2023 December 42 Circuits Syst. Signal Process. 12 https://doi.org/10.1007/s00034-023-02452-w db/journals/cssp/cssp42.html#ChangelaZK23

Ankur Changela Mazad Zaveri Deepak Verma A Comparative Study on CORDIC Algorithms and Applications. 2330002:1-2330002:47 2023 March 32 J. Circuits Syst. Comput. 5 https://doi.org/10.1142/S0218126623300027 db/journals/jcsc/jcsc32.html#ChangelaZV23

Ankur Changela Mazad Zaveri Deepak Verma Mixed-radix, virtually scaling-free CORDIC algorithm based rotator for DSP applications. 70-83 2021 78 Integr. https://doi.org/10.1016/j.vlsi.2021.01.005 db/journals/integration/integration78.html#ChangelaZV21

Ankur Changela Mazad Zaveri Deepak Verma FPGA implementation of high-performance, resource-efficient Radix-16 CORDIC rotator based FFT algorithm. 89-100 2020 73 Integr. https://doi.org/10.1016/j.vlsi.2020.03.008 db/journals/integration/integration73.html#ChangelaZV20

Mehul S. Raval Tolga Kaya Mazad Zaveri Paawan Sharma Experiments with Multinational Cross-Course Project. 570-575 2020 TALE https://doi.org/10.1109/TALE48869.2020.9368362 conf/tale/2020 db/conf/tale/tale2020.html#RavalKZS20

Manan Mewada Mazad Zaveri Rajesh Amratlal Thakker Improving the performance of transmission gate and hybrid CMOS Full Adders in chain and tree structure architectures. 381-392 2019 69 Integr. https://doi.org/10.1016/j.vlsi.2019.09.002 db/journals/integration/integration69.html#MewadaZT19

Ankur Changela Mazad Zaveri Anurag Lakhlani ASIC Implementation of High Performance Radix-8 CORDIC Algorithm. 699-705 2018 ICACCI https://doi.org/10.1109/ICACCI.2018.8554883 conf/icacci/2018 db/conf/icacci/icacci2018.html#ChangelaZL18 Manan Mewada Mazad Zaveri Anurag Lakhlani Estimating the Maximum Propagation Delay of 4-bit Ripple Carry Adder Using Reduced Input Transitions. 15-23 2017 VDAT https://doi.org/10.1007/978-981-10-7470-7_2 conf/vdat/2017 db/conf/vdat/vdat2017.html#MewadaZL17 Manan Mewada Mazad Zaveri An input test pattern for characterization of a full-adder and n-bit ripple carry adder. 250-255 2016 ICACCI https://doi.org/10.1109/ICACCI.2016.7732055 conf/icacci/2016 db/conf/icacci/icacci2016.html#MewadaZ16 Manan Mewada Mazad Zaveri A low-power high-speed hybrid full adder. 1-2 2016 VDAT https://doi.org/10.1109/ISVDAT.2016.8064900 conf/vdat/2016 db/conf/vdat/vdat2016.html#MewadaZ16

Mazad S. Zaveri Dan W. Hammerstrom Performance/price estimates for cortex-scale hardware: A design space exploration. 291-304 2011 24 Neural Networks 3 https://doi.org/10.1016/j.neunet.2010.12.003 https://www.wikidata.org/entity/Q39966533 db/journals/nn/nn24.html#ZaveriH11

Dan Hammerstrom Mazad Zaveri Bayesian Memory, a Possible Hardware Building Block for Intelligent Systems. 81 2008 AAAI Fall Symposium: Biologically Inspired Cognitive Architectures http://www.aaai.org/Library/Symposia/Fall/2008/fs08-04-021.php conf/aaaifs/2008-4 db/conf/aaaifs/aaaifs2008-04.html#HammerstromZ08 Changjian Gao Mazad S. Zaveri Dan W. Hammerstrom CMOS / CMOL architectures for spiking cortical column. 2441-2448 2008 IJCNN https://doi.org/10.1109/IJCNN.2008.4634138 conf/ijcnn/2008 db/conf/ijcnn/ijcnn2008.html#GaoZH08 Yagnik M. Bhavsar Ankur Changela Changjian Gao Dan W. HammerstromDan Hammerstrom Tolga Kaya Yogesh Kumar 0002 Anurag Lakhlani Manan Mewada Mehul S. Raval Paawan Sharma Rajesh Amratlal Thakker Deepak Verma Shaheriar B. Zaveri