A System Architecture for the Detection of Insider Attacks in Big Data Systems.

N. Ranganathan Nagarajan Ranganathan University of South Florida, Tampa, FL, USA http://www.cse.usf.edu/index.php?sec=25&sub=172 https://dl.acm.org/profile/81100282996

Santosh Aditham Nagarajan Ranganathan A System Architecture for the Detection of Insider Attacks in Big Data Systems. 974-987 2018 15 IEEE Trans. Dependable Secur. Comput. 6 https://doi.org/10.1109/TDSC.2017.2768533 http://doi.ieeecomputersociety.org/10.1109/TDSC.2017.2768533 db/journals/tdsc/tdsc15.html#AdithamR18

Santosh Aditham Nagarajan Ranganathan Srinivas Katkoori LSTM-Based Memory Profiling for Predicting Data Attacks in Distributed Big Data Systems. 1259-1267 2017 IPDPS Workshops https://doi.org/10.1109/IPDPSW.2017.76 https://doi.ieeecomputersociety.org/10.1109/IPDPSW.2017.76 conf/ipps/2017w db/conf/ipps/ipdps2017w.html#AdithamRK17

Himanshu Thapliyal Nagarajan Ranganathan Design of Efficient Reversible Logic Based Binary and BCD Adder Circuits. 2017 abs/1712.02630 CoRR http://arxiv.org/abs/1712.02630 db/journals/corr/corr1712.html#abs-1712-02630

Wei-Yu Tsai Xueqing Li 0002 Matthew Jerry Baihua Xie Nikhil Shukla Huichu Liu Nandhini Chandramoorthy Matthew Cotter Arijit Raychowdhury Donald M. Chiarulli Steven P. Levitan Suman Datta John Sampson Nagarajan Ranganathan Vijaykrishnan Narayanan Enabling New Computation Paradigms with HyperFET - An Emerging Device. 30-48 2016 2 IEEE Trans. Multi Scale Comput. Syst. 1 https://doi.org/10.1109/TMSCS.2016.2519022 http://doi.ieeecomputersociety.org/10.1109/TMSCS.2016.2519022 db/journals/tmscs/tmscs2.html#TsaiLJXSLCCRCLD16

Santosh Aditham Nagarajan Ranganathan Srinivas Katkoori Memory access pattern based insider threat detection in big data systems. 3625-3628 2016 IEEE BigData https://doi.org/10.1109/BigData.2016.7841027 conf/bigdataconf/2016 db/conf/bigdataconf/bigdataconf2016.html#AdithamRK16

Santosh Aditham Nagarajan Ranganathan Srinivas Katkoori Call Trace and Memory Access Pattern based Runtime Insider Threat Detection for Big Data Platforms. 2016 abs/1611.07392 CoRR http://arxiv.org/abs/1611.07392 db/journals/corr/corr1611.html#AdithamRK16

Santosh Aditham Nagarajan Ranganathan A Novel Control-flow based Intrusion Detection Technique for Big Data Systems. 2016 abs/1611.07649 CoRR http://arxiv.org/abs/1611.07649 db/journals/corr/corr1611.html#AdithamR16

Santosh Aditham Nagarajan Ranganathan A System Architecture for the Detection of Insider Attacks in Big Data Systems. 2016 abs/1612.01587 CoRR http://arxiv.org/abs/1612.01587 db/journals/corr/corr1612.html#AdithamR16a

Saurabh Kotiyal Himanshu Thapliyal Nagarajan Ranganathan Reversible logic based multiplication computing unit using binary tree data structure. 2668-2693 2015 71 J. Supercomput. 7 https://doi.org/10.1007/s11227-015-1410-3 db/journals/tjs/tjs71.html#KotiyalTR15

Matthew A. Morrison Nagarajan Ranganathan Jay Ligatti Design of Adiabatic Dynamic Differential Logic for DPA-Resistant Secure Integrated Circuits. 1381-1389 2015 23 IEEE Trans. Very Large Scale Integr. Syst. 8 https://doi.org/10.1109/TVLSI.2014.2342034 db/journals/tvlsi/tvlsi23.html#MorrisonRL15

Santosh Aditham Nagarajan Ranganathan A novel framework for mitigating insider attacks in big data systems. 1876-1885 2015 IEEE BigData https://doi.org/10.1109/BigData.2015.7363962 https://doi.ieeecomputersociety.org/10.1109/BigData.2015.7363962 conf/bigdataconf/2015 db/conf/bigdataconf/bigdataconf2015.html#AdithamR15 Tony Casagrande Nagarajan Ranganathan GTFUZZ: a novel algorithm for robust dynamic power optimization via gate sizing with fuzzy games. 677-682 2015 DATE http://dl.acm.org/citation.cfm?id=2755908 https://ieeexplore.ieee.org/document/7092474/ conf/date/2015 db/conf/date/date2015.html#CasagrandeR15 Santosh Aditham Nagarajan Ranganathan An energy-aware scheduling heuristic for distributed systems using non-cooperative games. 1-6 2015 IGSC https://doi.org/10.1109/IGCC.2015.7393680 https://doi.ieeecomputersociety.org/10.1109/IGCC.2015.7393680 conf/green/2015 db/conf/green/green2015.html#AdithamR15

Saurabh Kotiyal Himanshu Thapliyal Nagarajan Ranganathan Efficient reversible NOR gates and their mapping in optical computing domain. 825-834 2014 45 Microelectron. J. 6 https://doi.org/10.1016/j.mejo.2014.03.001 db/journals/mj/mj45.html#KotiyalTR14

Matthew Morrison Nagarajan Ranganathan Synthesis of Dual-Rail Adiabatic Logic for Low Power Security Applications. 975-988 2014 33 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7 https://doi.org/10.1109/TCAD.2014.2313454 https://www.wikidata.org/entity/Q114985375 db/journals/tcad/tcad33.html#MorrisonR14

Saurabh Kotiyal Himanshu Thapliyal Nagarajan Ranganathan Design of Reversible Adder-Subtractor and its Mapping in Optical Computing Domain. 37-55 2014 24 Trans. Comput. Sci. https://doi.org/10.1007/978-3-662-45711-5_3 journals/tcos/2014-24 db/journals/tcos/tcos24.html#KotiyalTR14

Yue Wang Nagarajan Ranganathan A Feedback, Runtime Technique for Scaling the Frequency in GPU Architectures. 430-435 2014 ISVLSI https://doi.org/10.1109/ISVLSI.2014.34 https://doi.ieeecomputersociety.org/10.1109/ISVLSI.2014.34 conf/isvlsi/2014 db/conf/isvlsi/isvlsi2014.html#WangR14 Matthew Morrison Nagarajan Ranganathan Forward Body Biased Adiabatic Logic for Peak and Average Power Reduction in 22nm CMOS. 470-475 2014 VLSID https://doi.org/10.1109/VLSID.2014.88 https://doi.ieeecomputersociety.org/10.1109/VLSID.2014.88 conf/vlsid/2014 db/conf/vlsid/vlsid2014.html#MorrisonR14 Saurabh Kotiyal Himanshu Thapliyal Nagarajan Ranganathan Circuit for Reversible Quantum Multiplier Based on Binary Tree Optimizing Ancilla and Garbage Bits. 545-550 2014 VLSID https://doi.org/10.1109/VLSID.2014.101 https://doi.ieeecomputersociety.org/10.1109/VLSID.2014.101 conf/vlsid/2014 db/conf/vlsid/vlsid2014.html#KotiyalTR14 Himanshu Thapliyal Nagarajan Ranganathan Saurabh Kotiyal Reversible Logic Based Design and Test of Field Coupled Nanocomputing Circuits. 133-172 2014 Field-Coupled Nanocomputing https://doi.org/10.1007/978-3-662-43722-3_7 series/lncs/8280 db/series/lncs/lncs8280.html#ThapliyalRK14 Marina L. Gavrilova C. J. Kenneth Tan Himanshu Thapliyal Nagarajan Ranganathan Transactions on Computational Science XXIV - Special Issue on Reversible Computing 2014 Springer Lecture Notes in Computer Science 8911 https://doi.org/10.1007/978-3-662-45711-5 978-3-662-45710-8 Trans. Comput. Sci. db/journals/tcos/tcos24.html

Sandip Kundu Saraju P. Mohanty Nagarajan Ranganathan Guest editorial - Design methodologies for nanoelectronic digital and analogue circuits. 221-222 2013 7 IET Circuits Devices Syst. 5 https://doi.org/10.1049/iet-cds.2013.0269 db/journals/iet-cds/iet-cds7.html#KunduMR13

Himanshu Thapliyal Nagarajan Ranganathan Design of efficient reversible logic-based binary and BCD adder circuits. 17:1-17:31 2013 9 ACM J. Emerg. Technol. Comput. Syst. 3 https://doi.org/10.1145/2491682 https://www.wikidata.org/entity/Q130878667 db/journals/jetc/jetc9.html#ThapliyalR13

Ransford Hyman Jr. Nagarajan Ranganathan Thomas Bingel Deanne Tran Vo A Clock Control Strategy for Peak Power and RMS Current Reduction Using Path Clustering. 259-269 2013 21 IEEE Trans. Very Large Scale Integr. Syst. 2 https://doi.org/10.1109/TVLSI.2012.2186989 db/journals/tvlsi/tvlsi21.html#HymanRBV13

Himanshu Thapliyal Nagarajan Ranganathan Saurabh Kotiyal Design of Testable Reversible Sequential Circuits. 1201-1209 2013 21 IEEE Trans. Very Large Scale Integr. Syst. 7 https://doi.org/10.1109/TVLSI.2012.2209688 db/journals/tvlsi/tvlsi21.html#ThapliyalRK13

Matthew Morrison Nagarajan Ranganathan A novel optimization method for reversible logic circuit minimization. 182-187 2013 ISVLSI https://doi.org/10.1109/ISVLSI.2013.6654656 https://doi.ieeecomputersociety.org/10.1109/ISVLSI.2013.6654656 conf/isvlsi/2013 db/conf/isvlsi/isvlsi2013.html#MorrisonR13 Matthew Lewandowski Nagarajan Ranganathan Matthew Morrison Behavioral model of integrated qubit gates for quantum reversible logic design. 194-199 2013 ISVLSI https://doi.org/10.1109/ISVLSI.2013.6654658 https://doi.ieeecomputersociety.org/10.1109/ISVLSI.2013.6654658 conf/isvlsi/2013 db/conf/isvlsi/isvlsi2013.html#LewandowskiRM13 Himanshu Thapliyal Apeksha Bhatt Nagarajan Ranganathan A new CRL gate as super class of Fredkin gate to design reversible quantum circuits. 1067-1070 2013 MWSCAS https://doi.org/10.1109/MWSCAS.2013.6674837 conf/mwscas/2013 db/conf/mwscas/mwscas2013.html#ThapliyalBR13

Venkataraman Mahalingam Nagarajan Ranganathan Ransford Hyman Jr. Dynamic clock stretching for variation compensation in VLSI circuit design. 16:1-16:13 2012 8 ACM J. Emerg. Technol. Comput. Syst. 3 https://doi.org/10.1145/2287696.2287699 db/journals/jetc/jetc8.html#MahalingamRH12

Yue Wang Soumyaroop Roy Nagarajan Ranganathan Run-time power-gating in caches of GPUs for leakage energy savings. 300-303 2012 DATE https://doi.org/10.1109/DATE.2012.6176483 https://doi.ieeecomputersociety.org/10.1109/DATE.2012.6176483 http://dl.acm.org/citation.cfm?id=2492783 conf/date/2012 db/conf/date/date2012.html#WangRR12 Saurabh Kotiyal Himanshu Thapliyal Nagarajan Ranganathan Mach-Zehnder interferometer based design of all optical reversible binary adder. 721-726 2012 DATE https://doi.org/10.1109/DATE.2012.6176564 https://doi.ieeecomputersociety.org/10.1109/DATE.2012.6176564 http://dl.acm.org/citation.cfm?id=2492890 conf/date/2012 db/conf/date/date2012.html#KotiyalTR12 Himanshu Thapliyal Nagarajan Ranganathan Design, Synthesis and Test of Reversible Circuits for Emerging Nanotechnologies. 5-6 2012 ISVLSI https://doi.org/10.1109/ISVLSI.2012.83 https://doi.ieeecomputersociety.org/10.1109/ISVLSI.2012.83 conf/isvlsi/2012 db/conf/isvlsi/isvlsi2012.html#ThapliyalR12 Saurabh Kotiyal Himanshu Thapliyal Nagarajan Ranganathan Mach-Zehnder Interferometer Based All Optical Reversible NOR Gates. 207-212 2012 ISVLSI https://doi.org/10.1109/ISVLSI.2012.72 https://doi.ieeecomputersociety.org/10.1109/ISVLSI.2012.72 conf/isvlsi/2012 db/conf/isvlsi/isvlsi2012.html#KotiyalTR12 Matthew Morrison Nagarajan Ranganathan Analysis of Reversible Logic Based Sequential Computing Structures Using Quantum Mechanics Principles. 219-224 2012 ISVLSI https://doi.org/10.1109/ISVLSI.2012.60 https://doi.ieeecomputersociety.org/10.1109/ISVLSI.2012.60 conf/isvlsi/2012 db/conf/isvlsi/isvlsi2012.html#MorrisonR12 Matthew Morrison Matthew Lewandowski Nagarajan Ranganathan Design of a Tree-Based Comparator and Memory Unit Based on a Novel Reversible Logic Structure. 231-236 2012 ISVLSI https://doi.org/10.1109/ISVLSI.2012.61 https://doi.ieeecomputersociety.org/10.1109/ISVLSI.2012.61 conf/isvlsi/2012 db/conf/isvlsi/isvlsi2012.html#MorrisonLR12 Himanshu Thapliyal Nagarajan Ranganathan Tutorial T2: Reversible Logic: Fundamentals and Applications in Ultra-Low Power, Fault Testing and Emerging Nanotechnologies, and Challenges in Future. 13-15 2012 VLSI Design https://doi.org/10.1109/VLSID.2012.29 https://doi.ieeecomputersociety.org/10.1109/VLSID.2012.29 conf/vlsid/2012 db/conf/vlsid/vlsid2012.html#ThapliyalR12

Ransford Hyman Jr. Koustav Bhattacharya Nagarajan Ranganathan Redundancy Mining for Soft Error Detection in Multicore Processors. 1114-1125 2011 60 IEEE Trans. Computers 8 https://doi.org/10.1109/TC.2010.168 http://doi.ieeecomputersociety.org/10.1109/TC.2010.168 db/journals/tc/tc60.html#HymanBR11

Soumyaroop Roy Nagarajan Ranganathan Srinivas Katkoori State-Retentive Power Gating of Register Files in Multicore Processors Featuring Multithreaded In-Order Cores. 1547-1560 2011 60 IEEE Trans. Computers 11 https://doi.org/10.1109/TC.2010.249 http://doi.ieeecomputersociety.org/10.1109/TC.2010.249 db/journals/tc/tc60.html#RoyRK11

Koustav Bhattacharya N. Ranganathan Placement for Immunity of Transient Faults in Cell-Based Design of Nanometer Circuits. 918-923 2011 19 IEEE Trans. Very Large Scale Integr. Syst. 5 https://doi.org/10.1109/TVLSI.2010.2040295 db/journals/tvlsi/tvlsi19.html#BhattacharyaR11

Upavan Gupta Nagarajan Ranganathan A Utilitarian Approach to Variation Aware Delay, Power, and Crosstalk Noise Optimization. 1723-1726 2011 19 IEEE Trans. Very Large Scale Integr. Syst. 9 https://doi.org/10.1109/TVLSI.2010.2053394 db/journals/tvlsi/tvlsi19.html#GuptaR11

Yue Wang N. Ranganathan An Instruction-Level Energy Estimation and Optimization Methodology for GPU. 621-628 2011 CIT https://doi.org/10.1109/CIT.2011.69 https://doi.ieeecomputersociety.org/10.1109/CIT.2011.69 conf/IEEEcit/2011 db/conf/IEEEcit/IEEEcit2011.html#WangR11 Himanshu Thapliyal N. Ranganathan A new reversible design of BCD adder. 1180-1183 2011 DATE https://doi.org/10.1109/DATE.2011.5763308 https://doi.ieeecomputersociety.org/10.1109/DATE.2011.5763308 conf/date/2011 db/conf/date/date2011.html#ThapliyalR11 Matthew Morrison Nagarajan Ranganathan Design of a Reversible ALU Based on Novel Programmable Reversible Logic Gate Structures. 126-131 2011 ISVLSI https://doi.org/10.1109/ISVLSI.2011.30 https://doi.ieeecomputersociety.org/10.1109/ISVLSI.2011.30 conf/isvlsi/2011 db/conf/isvlsi/isvlsi2011.html#MorrisonR11

Himanshu Thapliyal Nagarajan Ranganathan Reversible Logic Based Concurrent Error Detection Methodology For Emerging Nanocircuits http://arxiv.org/abs/1101.4222 2011 CoRR abs/1101.4222 db/journals/corr/corr1101.html#abs-1101-4222

Himanshu Thapliyal Nagarajan Ranganathan Design of reversible sequential circuits optimizing quantum cost, delay, and garbage outputs. 14:1-14:31 2010 6 ACM J. Emerg. Technol. Comput. Syst. 4 https://doi.org/10.1145/1877745.1877748 https://www.wikidata.org/entity/Q130929397 db/journals/jetc/jetc6.html#ThapliyalR10

Upavan Gupta Nagarajan Ranganathan A Game Theoretic Approach for Simultaneous Compaction and Equipartitioning of Spatial Data Sets. 465-478 2010 22 IEEE Trans. Knowl. Data Eng. 4 https://doi.org/10.1109/TKDE.2009.110 http://doi.ieeecomputersociety.org/10.1109/TKDE.2009.110 db/journals/tkde/tkde22.html#GuptaR10

Venkataraman Mahalingam Koustav Bhattacharya N. Ranganathan Hari Chakravarthula Robin R. Murphy Kevin S. Pratt A VLSI Architecture and Algorithm for Lucas-Kanade-Based Optical Flow Computation. 29-38 2010 18 IEEE Trans. Very Large Scale Integr. Syst. 1 https://doi.org/10.1109/TVLSI.2008.2006900 db/journals/tvlsi/tvlsi18.html#MahalingamBRCMP10

Venkataraman Mahalingam N. Ranganathan Timing-Based Placement Considering Uncertainty Due to Process Variations. 1007-1011 2010 18 IEEE Trans. Very Large Scale Integr. Syst. 6 https://doi.org/10.1109/TVLSI.2009.2017540 db/journals/tvlsi/tvlsi18.html#MahalingamR10

Himanshu Thapliyal Nagarajan Ranganathan Design of Reversible Latches Optimized for Quantum Cost, Delay and Garbage Outputs. 235-240 2010 VLSI Design https://doi.org/10.1109/VLSI.Design.2010.74 https://doi.ieeecomputersociety.org/10.1109/VLSI.Design.2010.74 conf/vlsid/2010 db/conf/vlsid/vlsid2010.html#ThapliyalR10

Nagarajan Ranganathan Upavan Gupta Venkataraman Mahalingam Variation-aware multimetric optimization during gate sizing. 2009 14 ACM Trans. Design Autom. Electr. Syst. 4 https://doi.org/10.1145/1562514.1562522 db/journals/todaes/todaes14.html#RanganathanGM09 54:1-54:30

Koustav Bhattacharya Nagarajan Ranganathan Soontae Kim A Framework for Correction of Multi-Bit Soft Errors in L2 Caches Based on Redundancy. 194-206 2009 17 IEEE Trans. Very Large Scale Integr. Syst. 2 https://doi.org/10.1109/TVLSI.2008.2003236 db/journals/tvlsi/tvlsi17.html#BhattacharyaRK09

Soumyaroop Roy Nagarajan Ranganathan Srinivas Katkoori A Framework for Power-Gating Functional Units in Embedded Microprocessors. 1640-1649 2009 17 IEEE Trans. Very Large Scale Integr. Syst. 11 https://doi.org/10.1109/TVLSI.2008.2005774 db/journals/tvlsi/tvlsi17.html#RoyRK09

Soumyaroop Roy Nagarajan Ranganathan Srinivas Katkoori Compiler-directed leakage reduction in embedded microprocessors. 35-40 2009 ICCD https://doi.org/10.1109/ICCD.2009.5413178 https://doi.ieeecomputersociety.org/10.1109/ICCD.2009.5413178 conf/iccd/2009 db/conf/iccd/iccd2009.html#RoyRK09 Koustav Bhattacharya Venkataraman Mahalingam Nagarajan Ranganathan A VLSI System Architecture for Optical Flow Computation. 357-360 2009 ISCAS https://doi.org/10.1109/ISCAS.2009.5117759 conf/iscas/2009 db/conf/iscas/iscas2009.html#BhattacharyaMR09 Soumyaroop Roy Nagarajan Ranganathan Srinivas Katkoori Exploring Compiler Optimizations for Enhancing Power Gating. 1004-1007 2009 ISCAS https://doi.org/10.1109/ISCAS.2009.5117928 conf/iscas/2009 db/conf/iscas/iscas2009.html#RoyRK09 Himanshu Thapliyal Nagarajan Ranganathan Concurrently Testable FPGA Design for Molecular QCA using Conservative Reversible Logic Gate. 1815-1818 2009 ISCAS https://doi.org/10.1109/ISCAS.2009.5118130 conf/iscas/2009 db/conf/iscas/iscas2009.html#ThapliyalR09 Ransford Hyman Jr. Koustav Bhattacharya N. Ranganathan A Strategy for Soft Error Reduction in Multi Core Designs. 2217-2220 2009 ISCAS https://doi.org/10.1109/ISCAS.2009.5118238 conf/iscas/2009 db/conf/iscas/iscas2009.html#HymanBR09 Koustav Bhattacharya Nagarajan Ranganathan A unified gate sizing formulation for optimizing soft error rate, cross-talk noise and power under process variations. 388-393 2009 ISQED https://doi.org/10.1109/ISQED.2009.4810326 https://doi.ieeecomputersociety.org/10.1109/ISQED.2009.4810326 conf/isqed/2009 db/conf/isqed/isqed2009.html#BhattacharyaR09 Koustav Bhattacharya Nagarajan Ranganathan A New Placement Algorithm for Reduction of Soft Errors in Macrocell Based Design of Nanometer Circuits. 91-96 2009 ISVLSI https://doi.org/10.1109/ISVLSI.2009.37 https://doi.ieeecomputersociety.org/10.1109/ISVLSI.2009.37 conf/isvlsi/2009 db/conf/isvlsi/isvlsi2009.html#BhattacharyaR09 Himanshu Thapliyal Nagarajan Ranganathan Design of Efficient Reversible Binary Subtractors Based on a New Reversible Gate. 229-234 2009 ISVLSI https://doi.org/10.1109/ISVLSI.2009.49 https://doi.ieeecomputersociety.org/10.1109/ISVLSI.2009.49 conf/isvlsi/2009 db/conf/isvlsi/isvlsi2009.html#ThapliyalR09 Koustav Bhattacharya Nagarajan Ranganathan RADJAM: A Novel Approach for Reduction of Soft Errors in Logic Circuits. 453-458 2009 VLSI Design https://doi.org/10.1109/VLSI.Design.2009.76 https://doi.ieeecomputersociety.org/10.1109/VLSI.Design.2009.76 conf/vlsid/2009 db/conf/vlsid/vlsid2009.html#BhattacharyaR09 Himanshu Thapliyal Nagarajan Ranganathan Conservative QCA Gate (CQCA) for Designing Concurrently Testable Molecular QCA Circuits. 511-516 2009 VLSI Design https://doi.org/10.1109/VLSI.Design.2009.75 https://doi.ieeecomputersociety.org/10.1109/VLSI.Design.2009.75 conf/vlsid/2009 db/conf/vlsid/vlsid2009.html#ThapliyalR09

Venkataraman Mahalingam N. Ranganathan J. E. Harlow A Fuzzy Optimization Approach for Variation Aware Power Minimization During Gate Sizing. 975-984 2008 16 IEEE Trans. Very Large Scale Integr. Syst. 8 https://doi.org/10.1109/TVLSI.2008.2000597 db/journals/tvlsi/tvlsi16.html#MahalingamRH08

N. Ranganathan Upavan Gupta Venkataraman Mahalingam Simultaneous optimization of total power, crosstalk noise, and delay under uncertainty. 171-176 2008 ACM Great Lakes Symposium on VLSI https://doi.org/10.1145/1366110.1366154 conf/glvlsi/2008 db/conf/glvlsi/glvlsi2008.html#RanganathanGM08 Koustav Bhattacharya Nagarajan Ranganathan A linear programming formulation for security-aware gate sizing. 273-278 2008 ACM Great Lakes Symposium on VLSI https://doi.org/10.1145/1366110.1366176 https://www.wikidata.org/entity/Q130971110 conf/glvlsi/2008 db/conf/glvlsi/glvlsi2008.html#BhattacharyaR08 Upavan Gupta Nagarajan Ranganathan A microeconomic approach to multi-objective spatial clustering. 1-4 2008 ICPR https://doi.org/10.1109/ICPR.2008.4761210 https://doi.ieeecomputersociety.org/10.1109/ICPR.2008.4761210 conf/icpr/2008 db/conf/icpr/icpr2008.html#GuptaR08 Upavan Gupta Nagarajan Ranganathan An expected-utility based approach to variation aware VLSI optimization under scarce information. 81-86 2008 ISLPED https://doi.org/10.1145/1393921.1393945 conf/islped/2008 db/conf/islped/islped2008.html#GuptaR08 Koustav Bhattacharya Nagarajan Ranganathan Reliability-centric gate sizing with simultaneous optimization of soft error rate, delay and power. 99-104 2008 ISLPED https://doi.org/10.1145/1393921.1393948 https://www.wikidata.org/entity/Q130993685 conf/islped/2008 db/conf/islped/islped2008.html#BhattacharyaR08 Venkataraman Mahalingam Nagarajan Ranganathan A Fuzzy Approach for Variation Aware Buffer Insertion and Driver Sizing. 329-334 2008 ISVLSI https://doi.org/10.1109/ISVLSI.2008.63 https://doi.ieeecomputersociety.org/10.1109/ISVLSI.2008.63 conf/isvlsi/2008 db/conf/isvlsi/isvlsi2008.html#MahalingamR08

Saraju P. Mohanty Elias Kougianos Nagarajan Ranganathan VLSI architecture and chip for combined invisible robust and fragile watermarking. 600-611 2007 1 IET Comput. Digit. Tech. 5 https://doi.org/10.1049/iet-cdt:20070057 db/journals/iet-cdt/iet-cdt1.html#MohantyKR07

K. P. Subbalakshmi Rajarathnam Chandramouli Nagarajan Ranganathan A Sequential Distinguisher for Covert Channel Identification. 274-282 2007 5 Int. J. Netw. Secur. 3 http://ijns.jalaxy.com.tw/contents/ijns-v5-n3/ijns-2007-v5-n3-p274-282.pdf db/journals/ijnsec/ijnsec5.html#SubbalakshmiCR07

Upavan Gupta Nagarajan Ranganathan Multievent Crisis Management Using Noncooperative Multistep Games. 577-589 2007 56 IEEE Trans. Computers 5 https://doi.org/10.1109/TC.2007.1023 https://doi.ieeecomputersociety.org/10.1109/TC.2007.1023 db/journals/tc/tc56.html#GuptaR07

Koustav Bhattacharya Soontae Kim Nagarajan Ranganathan Improving the reliability of on-chip L2 cache using redundancy. 224-229 2007 ICCD https://doi.org/10.1109/ICCD.2007.4601906 https://doi.ieeecomputersociety.org/10.1109/ICCD.2007.4601906 conf/iccd/2007 db/conf/iccd/iccd2007.html#BhattacharyaKR07 Upavan Gupta Nagarajan Ranganathan A microeconomic approach to multi-robot team formation. 3019-3024 2007 IROS https://doi.org/10.1109/IROS.2007.4399435 conf/iros/2007 db/conf/iros/iros2007.html#GuptaR07 Venkataraman Mahalingam N. Ranganathan Variation Aware Timing Based Placement Using Fuzzy Programming. 327-332 2007 conf/isqed/2007 ISQED https://doi.org/10.1109/ISQED.2007.167 https://doi.ieeecomputersociety.org/10.1109/ISQED.2007.167 db/conf/isqed/isqed2007.html#MahalingamR07 Narender Hanchate Nagarajan Ranganathan Integrated Gate and Wire Sizing at Post Layout Level. 225-232 2007 conf/isvlsi/2007 ISVLSI https://doi.org/10.1109/ISVLSI.2007.59 https://doi.ieeecomputersociety.org/10.1109/ISVLSI.2007.59 db/conf/isvlsi/isvlsi2007.html#HanchateR07 Narender Hanchate Nagarajan Ranganathan Statistical Gate Sizing for Yield Enhancement at Post Layout Level. 245-252 2007 conf/isvlsi/2007 ISVLSI https://doi.org/10.1109/ISVLSI.2007.92 https://doi.ieeecomputersociety.org/10.1109/ISVLSI.2007.92 db/conf/isvlsi/isvlsi2007.html#HanchateR07a Soumyaroop Roy Srinivas Katkoori Nagarajan Ranganathan A Compiler Based Leakage Reduction Technique by Power-Gating Functional Units in Embedded Microprocessors. 215-220 2007 conf/vlsid/2007 VLSI Design https://doi.org/10.1109/VLSID.2007.10 https://doi.ieeecomputersociety.org/10.1109/VLSID.2007.10 db/conf/vlsid/vlsid2007.html#RoyKR07

Narender Hanchate Nagarajan Ranganathan Simultaneous Interconnect Delay and Crosstalk Noise Optimization through Gate Sizing Using Game Theory. 1011-1023 2006 55 IEEE Trans. Computers 8 https://doi.org/10.1109/TC.2006.131 http://doi.ieeecomputersociety.org/10.1109/TC.2006.131 db/journals/tc/tc55.html#HanchateR06

Venkataraman Mahalingam Nagarajan Ranganathan Improving Accuracy in Mitchell's Logarithmic Multiplication Using Operand Decomposition. 1523-1535 2006 55 IEEE Trans. Computers 12 https://doi.org/10.1109/TC.2006.198 http://doi.ieeecomputersociety.org/10.1109/TC.2006.198 db/journals/tc/tc55.html#MahalingamR06

Saraju P. Mohanty Nagarajan Ranganathan Karthikeyan Balakrishnan A dual voltage-frequency VLSI chip for image watermarking in DCT domain. 394-398 2006 53-II IEEE Trans. Circuits Syst. II Express Briefs 5 https://doi.org/10.1109/TCSII.2006.870216 db/journals/tcas/tcasII53.html#MohantyRB06

Saraju P. Mohanty N. Ranganathan Sunil K. Chappidi ILP models for simultaneous energy and transient power minimization during behavioral synthesis. 186-212 2006 11 ACM Trans. Design Autom. Electr. Syst. 1 https://doi.org/10.1145/1124713.1124725 db/journals/todaes/todaes11.html#MohantyRC06

Narender Hanchate Nagarajan Ranganathan A game-theoretic framework for multimetric optimization of interconnect delay, power, and crosstalk noise during wire sizing. 711-739 2006 11 ACM Trans. Design Autom. Electr. Syst. 3 https://doi.org/10.1145/1142980.1142988 db/journals/todaes/todaes11.html#HanchateR06

Sanjukta Bhanja Karthikeyan Lingasubramanian N. Ranganathan A stimulus-free graphical probabilistic switching model for sequential circuits using dynamic bayesian networks. 773-796 2006 11 ACM Trans. Design Autom. Electr. Syst. 3 https://doi.org/10.1145/1142980.1142990 db/journals/todaes/todaes11.html#BhanjaLR06

Venkataraman Mahalingam N. Ranganathan Justin E. Harlow III A novel approach for variation aware power minimization during gate sizing. 174-179 2006 conf/islped/2006 ISLPED https://doi.org/10.1145/1165573.1165614 db/conf/islped/islped2006.html#MahalingamRH06 Narender Hanchate Nagarajan Ranganathan Post-Layout Gate Sizing for Interconnect Delay and Crosstalk Noise Optimization. 92-97 2006 conf/isqed/2006 ISQED https://doi.org/10.1109/ISQED.2006.101 https://doi.ieeecomputersociety.org/10.1109/ISQED.2006.101 db/conf/isqed/isqed2006.html#HanchateR06 Upavan Gupta N. Ranganathan Social Fairness in Multi-Emergency Resource Management. 1-9 2006 ISTAS https://doi.org/10.1109/ISTAS.2006.4375884 conf/istas/2006 db/conf/istas/istas2006.html#GuptaR06 Nagarajan Ranganathan Ravi Namballa Narender Hanchate CHESS: A Comprehensive Tool for CDFG Extraction and Synthesis of Low Power Designs from VHDL. 329-334 2006 conf/isvlsi/2006 ISVLSI https://doi.org/10.1109/ISVLSI.2006.27 https://doi.ieeecomputersociety.org/10.1109/ISVLSI.2006.27 db/conf/isvlsi/isvlsi2006.html#RanganathanNH06 Narender Hanchate Nagarajan Ranganathan A Linear Time Algorithm for Wire Sizing with Simultaneous Optimization of Interconnect Delay and Crosstalk Noise. 283-290 2006 conf/vlsid/2006 VLSI Design https://doi.org/10.1109/VLSID.2006.11 https://doi.ieeecomputersociety.org/10.1109/VLSID.2006.11 db/conf/vlsid/vlsid2006.html#HanchateR06 Venkataraman Mahalingam N. Ranganathan An Efficient and Accurate Logarithmic Multiplier Based on Operand Decomposition. 393-398 2006 conf/vlsid/2006 VLSI Design https://doi.org/10.1109/VLSID.2006.42 https://doi.ieeecomputersociety.org/10.1109/VLSID.2006.42 db/conf/vlsid/vlsid2006.html#MahalingamR06 Viswanath Sairaman Nagarajan Ranganathan Neeta S. Singh An Automatic Code Generation Tool for Partitioned Software in Distributed Systems. 477-480 2006 conf/vlsid/2006 VLSI Design https://doi.org/10.1109/VLSID.2006.41 https://doi.ieeecomputersociety.org/10.1109/VLSID.2006.41 db/conf/vlsid/vlsid2006.html#SairamanRS06 Aswath Oruganti Nagarajan Ranganathan Leakage Power Reduction in Dual-Vdd and Dual-Vth Designs through Probabilistic Analysis of Vth Variation. 766-769 2006 conf/vlsid/2006 VLSI Design https://doi.org/10.1109/VLSID.2006.110 https://doi.ieeecomputersociety.org/10.1109/VLSID.2006.110 db/conf/vlsid/vlsid2006.html#OrugantiR06

Saraju P. Mohanty N. Ranganathan Energy-efficient datapath scheduling using multiple voltages and dynamic clocking. 330-353 2005 10 ACM Trans. Design Autom. Electr. Syst. 2 https://doi.org/10.1145/1059876.1059883 db/journals/todaes/todaes10.html#MohantyR05

Saraju P. Mohanty Nagarajan Ranganathan Ravi Namballa A VLSI architecture for watermarking in a secure still digital camera (S2DC) design. 808-818 2005 13 IEEE Trans. Very Large Scale Integr. Syst. 7 https://doi.org/10.1109/TVLSI.2005.850095 db/journals/tvlsi/tvlsi13.html#MohantyRN05

Saraju P. Mohanty Nagarajan Ranganathan Ravi Namballa A VLSI architecture for visible watermarking in a secure still digital camera (S2/DC) design (Corrected)*. 1002-1012 2005 13 IEEE Trans. Very Large Scale Integr. Syst. 8 https://doi.org/10.1109/TVLSI.2005.857991 db/journals/tvlsi/tvlsi13.html#MohantyRN05a

Venkataraman Mahalingam N. Ranganathan A Nonlinear Programming Based Power Optimization Methodology for Gate Sizing and Voltage Selection. 180-185 2005 conf/isvlsi/2005 ISVLSI https://doi.org/10.1109/ISVLSI.2005.12 https://doi.ieeecomputersociety.org/10.1109/ISVLSI.2005.12 db/conf/isvlsi/isvlsi2005.html#MahalingamR05 Saraju P. Mohanty N. Ranganathan Karthikeyan Balakrishnan Design of a Low Power Image Watermarking Encoder Using Dual Voltage and Frequency. 153-158 2005 conf/vlsid/2005 VLSI Design https://doi.org/10.1109/ICVD.2005.73 https://doi.ieeecomputersociety.org/10.1109/ICVD.2005.73 db/conf/vlsid/vlsid2005.html#MohantyRB05 Sanjukta Bhanja Karthikeyan Lingasubramanian N. Ranganathan Estimation of Switching Activity in Sequential Circuits Using Dynamic Bayesian Networks. 586-591 2005 conf/vlsid/2005 VLSI Design https://doi.org/10.1109/ICVD.2005.93 https://doi.ieeecomputersociety.org/10.1109/ICVD.2005.93 db/conf/vlsid/vlsid2005.html#BhanjaLR05

Ramamurti Chandramouli Koduvayur P. Subbalakshmi N. Ranganathan Stochastic channel-adaptive rate control for wireless video transmission. 793-806 2004 25 Pattern Recognit. Lett. 7 https://doi.org/10.1016/j.patrec.2004.01.003 db/journals/prl/prl25.html#ChandramouliSR04

N. Ranganathan Editorial. 1-11 2004 12 IEEE Trans. Very Large Scale Integr. Syst. 1 db/journals/tvlsi/tvlsi12.html#Ranganathan04 https://doi.org/10.1109/TVLSI.2003.822591

Narender Hanchate Nagarajan Ranganathan LECTOR: a technique for leakage reduction in CMOS circuits. 196-205 2004 12 IEEE Trans. Very Large Scale Integr. Syst. 2 db/journals/tvlsi/tvlsi12.html#HanchateR04 https://doi.org/10.1109/TVLSI.2003.821547

Saraju P. Mohanty Nagarajan Ranganathan A framework for energy and transient power reduction during behavioral synthesis. 562-572 2004 12 IEEE Trans. Very Large Scale Integr. Syst. 6 https://doi.org/10.1109/TVLSI.2004.827568 db/journals/tvlsi/tvlsi12.html#MohantyR04

Sanjukta Bhanja N. Ranganathan Cascaded Bayesian inferencing for switching activity estimation with correlated inputs. 1360-1370 2004 12 IEEE Trans. Very Large Scale Integr. Syst. 12 https://doi.org/10.1109/TVLSI.2004.837991 db/journals/tvlsi/tvlsi12.html#BhanjaR04

Ravi Namballa Nagarajan Ranganathan Abdel Ejnioui Control and Data Flow Graph Extraction for High-Level Synthesis. 187-192 2004 conf/isvlsi/2004 ISVLSI https://doi.org/10.1109/ISVLSI.2004.1339528 https://doi.ieeecomputersociety.org/10.1109/ISVLSI.2004.1339528 db/conf/isvlsi/isvlsi2004.html#NamballaRE04 Ashok K. Murugavel N. Ranganathan Gate Sizing and Buffer Insertion using Economic Models for Power Optimization. 195-200 2004 conf/vlsid/2004 VLSI Design https://doi.org/10.1109/ICVD.2004.1260924 https://doi.ieeecomputersociety.org/10.1109/ICVD.2004.1260924 db/conf/vlsid/vlsid2004.html#MurugavelR04 Narender Hanchate Nagarajan Ranganathan A New Technique for Leakage Reduction in CMOS Circuits using Self-Controlled Stacked Transistors. 228-233 2004 conf/vlsid/2004 VLSI Design https://doi.org/10.1109/ICVD.2004.1260929 https://doi.ieeecomputersociety.org/10.1109/ICVD.2004.1260929 db/conf/vlsid/vlsid2004.html#HanchateR04 Ashok K. Murugavel N. Ranganathan Game Theoretic Modeling of Voltage and Frequency Scaling during Behavioral Synthesis. 670- 2004 conf/vlsid/2004 VLSI Design https://doi.org/10.1109/ICVD.2004.1261000 https://doi.ieeecomputersociety.org/10.1109/ICVD.2004.1261000 db/conf/vlsid/vlsid2004.html#MurugavelR04a Saraju P. Mohanty Nagarajan Ranganathan Sunil K. Chappidi ILP Models for Energy and Transient Power Minimization During Behavioral Synthesis. 745-748 2004 conf/vlsid/2004 VLSI Design https://doi.org/10.1109/ICVD.2004.1261017 https://doi.ieeecomputersociety.org/10.1109/ICVD.2004.1261017 db/conf/vlsid/vlsid2004.html#MohantyRC04 Saraju P. Mohanty Nagarajan Ranganathan Ravi Namballa VLSI Implementation of Visible Watermarking for a Secure Digital Still Camera Design. 1063- 2004 conf/vlsid/2004 VLSI Design https://doi.org/10.1109/ICVD.2004.1261070 https://doi.ieeecomputersociety.org/10.1109/ICVD.2004.1261070 https://www.wikidata.org/entity/Q56455029 db/conf/vlsid/vlsid2004.html#MohantyRN04

Abdel Ejnioui N. Ranganathan Multiterminal net routing for partial crossbar-based multi-FPGA systems. 71-78 2003 11 IEEE Trans. Very Large Scale Integr. Syst. 1 https://doi.org/10.1109/TVLSI.2002.800523 db/journals/tvlsi/tvlsi11.html#EjniouiR03

Abdel Ejnioui N. Ranganathan Routing on field-programmable switch matrices. 283-287 2003 11 IEEE Trans. Very Large Scale Integr. Syst. 2 https://doi.org/10.1109/TVLSI.2003.810778 db/journals/tvlsi/tvlsi11.html#EjniouiR03a

Sanjukta Bhanja N. Ranganathan Switching activity estimation of VLSI circuits using Bayesian networks. 558-567 2003 11 IEEE Trans. Very Large Scale Integr. Syst. 4 https://doi.org/10.1109/TVLSI.2003.816144 db/journals/tvlsi/tvlsi11.html#BhanjaR03

Ashok K. Murugavel N. Ranganathan Petri net modeling of gate and interconnect delays for power estimation. 921-927 2003 11 IEEE Trans. Very Large Scale Integr. Syst. 5 https://doi.org/10.1109/TVLSI.2003.817110 db/journals/tvlsi/tvlsi11.html#MurugavelR03

Ashok K. Murugavel N. Ranganathan A game theoretic approach for power optimization during behavioral synthesis. 1031-1043 2003 11 IEEE Trans. Very Large Scale Integr. Syst. 6 https://doi.org/10.1109/TVLSI.2003.819566 db/journals/tvlsi/tvlsi11.html#MurugavelR03a

N. Ranganathan Ashok K. Murugavel A low power scheduler using game theory. 126-131 2003 conf/codes/2003 CODES+ISSS https://doi.org/10.1145/944645.944681 db/conf/codes/codes2003.html#RanganathanM03 Saraju P. Mohanty N. Ranganathan Sunil K. Chappidi Simultaneous peak and average power minimization during datapath scheduling for DSP processors. 215-220 2003 conf/glvlsi/2003 ACM Great Lakes Symposium on VLSI https://doi.org/10.1145/764808.764864 db/conf/glvlsi/glvlsi2003.html#MohantyRC03 N. Ranganathan Ashok K. Murugavel A Microeconomic Model for Simultaneous Gate Sizing and Voltage Scaling for Power Optimization. 276-281 2003 conf/iccd/2003 ICCD https://doi.org/10.1109/ICCD.2003.1240907 https://doi.ieeecomputersociety.org/10.1109/ICCD.2003.1240907 db/conf/iccd/iccd2003.html#RanganathanM03 Saraju P. Mohanty N. Ranganathan Sunil K. Chappidi Power Fluctuation Minimization During Behavioral Synthesis using ILP-Based Datapath Scheduling. 441-443 2003 conf/iccd/2003 ICCD https://doi.org/10.1109/ICCD.2003.1240937 https://doi.ieeecomputersociety.org/10.1109/ICCD.2003.1240937 db/conf/iccd/iccd2003.html#MohantyRC03 Saraju P. Mohanty Nagarajan Ranganathan Sunil K. Chappidi Transient power minimization through datapath scheduling in multiple supply voltage environment. 300-303 2003 ICECS https://doi.org/10.1109/ICECS.2003.1302036 conf/icecsys/2003 db/conf/icecsys/icecsys2003.html#MohantyRC03 Saraju P. Mohanty N. Ranganathan Sunil K. Chappidi An ILP-based scheduling scheme for energy efficient high performance datapath synthesis. 313-316 2003 conf/iscas/2003 ISCAS (5) https://doi.org/10.1109/ISCAS.2003.1206265 db/conf/iscas/iscas2003-5.html#MohantyRC03 Saraju P. Mohanty N. Ranganathan Sunil K. Chappidi Peak Power Minimization Through Datapath Scheduling. 121-126 2003 conf/isvlsi/2003 ISVLSI https://doi.org/10.1109/ISVLSI.2003.1183362 https://doi.ieeecomputersociety.org/10.1109/ISVLSI.2003.1183362 db/conf/isvlsi/isvlsi2003.html#MohantyRC03 Saraju P. Mohanty N. Ranganathan Energy Efficient Scheduling for Datapath Synthesis. 446-451 2003 conf/vlsid/2003 VLSI Design https://doi.org/10.1109/ICVD.2003.1183175 https://doi.ieeecomputersociety.org/10.1109/ICVD.2003.1183175 db/conf/vlsid/vlsid2003.html#MohantyR03 Ashok K. Murugavel N. Ranganathan A Game-Theoretic Approach for Binding in Behavioral Synthesis. 452- 2003 conf/vlsid/2003 VLSI Design https://doi.org/10.1109/ICVD.2003.1183176 https://doi.ieeecomputersociety.org/10.1109/ICVD.2003.1183176 db/conf/vlsid/vlsid2003.html#MurugavelR03 Saraju P. Mohanty N. Ranganathan A Framework for Energy and Transient Power Reduction during Behavioral Synthesis. 539-545 2003 conf/vlsid/2003 VLSI Design https://doi.org/10.1109/ICVD.2003.1183190 https://doi.ieeecomputersociety.org/10.1109/ICVD.2003.1183190 db/conf/vlsid/vlsid2003.html#MohantyR03a

Hitoshi Oi N. Ranganathan A comparative study of bidirectional ring and crossbar interconnection networks. 43-57 2002 28 Comput. Electr. Eng. 1 https://doi.org/10.1016/S0045-7906(00)00044-6 https://www.wikidata.org/entity/Q126352898 db/journals/cee/cee28.html#OiR02

Ashok K. Murugavel N. Ranganathan Ramamurti Chandramouli Srinath Chavali Least-square estimation of average power in digital CMOS circuits. 55-58 2002 10 IEEE Trans. Very Large Scale Integr. Syst. 1 https://doi.org/10.1109/92.988730 db/journals/tvlsi/tvlsi10.html#MurugavelRCC02

K. Sitaraman N. Ranganathan Abdel Ejnioui A VLSI Architecture for Object Recognition Using Tree Matching. 325-334 2002 conf/asap/2002 ASAP https://doi.org/10.1109/ASAP.2002.1030731 https://doi.ieeecomputersociety.org/10.1109/ASAP.2002.1030731 db/conf/asap/asap2002.html#SitaramanRE02 Ashok K. Murugavel N. Ranganathan Petri net modeling of gate and interconnect delays for power estimation. 455-460 2002 conf/dac/2002 DAC https://doi.org/10.1145/513918.514034 db/conf/dac/dac2002.html#MurugavelR02 Sanjukta Bhanja N. Ranganathan Modeling Switching Activity Using Cascaded Bayesian Networks for Correlated Input Streams. 388-390 2002 conf/iccd/2002 ICCD https://doi.org/10.1109/ICCD.2002.1106799 https://doi.ieeecomputersociety.org/10.1109/ICCD.2002.1106799 db/conf/iccd/iccd2002.html#BhanjaR02 Ashok K. Murugavel N. Ranganathan Power estimation of sequential circuits using hierarchical colored hardware petri net modeling. 267-270 2002 conf/islped/2002 ISLPED https://doi.org/10.1145/566408.566478 db/conf/islped/islped2002.html#MurugavelR02 Saraju P. Mohanty N. Ranganathan Vamsi Krishna Datapath Scheduling using Dynamic Frequency Clocking. 65-70 2002 conf/isvlsi/2002 ISVLSI https://doi.org/10.1109/ISVLSI.2002.1016876 https://doi.ieeecomputersociety.org/10.1109/ISVLSI.2002.1016876 db/conf/isvlsi/isvlsi2002.html#MohantyRK02 Ashok K. Murugavel N. Ranganathan A Real Delay Switching Activity Simulator Based on Petri Net Modeling. 181-186 2002 conf/vlsid/2002 ASP-DAC/VLSI Design https://doi.org/10.1109/ASPDAC.2002.994915 https://doi.ieeecomputersociety.org/10.1109/ASPDAC.2002.994915 https://dl.acm.org/doi/10.5555/832284.835485 db/conf/vlsid/vlsid2002.html#MurugavelR02 Sanjukta Bhanja N. Ranganathan Switching Activity Estimation of Large Circuits using Multiple Bayesian Networks. 187-192 2002 conf/vlsid/2002 ASP-DAC/VLSI Design https://doi.org/10.1109/ASPDAC.2002.994917 https://doi.ieeecomputersociety.org/10.1109/ASPDAC.2002.994917 https://dl.acm.org/doi/10.5555/832284.835487 db/conf/vlsid/vlsid2002.html#BhanjaR02

Veeru N. Ramaswamy Kameswara Rao Namuduri N. Ranganathan Context-based lossless image coding using EZW framework. 554-559 2001 11 IEEE Trans. Circuits Syst. Video Technol. 4 db/journals/tcsv/tcsv11.html#RamaswamyNR01 https://doi.org/10.1109/76.915361

N. Ranganathan Minesh I. Patel R. Sathyamurthy An intelligent system for failure detection and control in an autonomous underwater vehicle. 762-767 2001 31 IEEE Trans. Syst. Man Cybern. Part A 6 db/journals/tsmc/tsmca31.html#RanganathanPS01 https://doi.org/10.1109/3468.983434

Abdel Ejnioui N. Ranganathan A partitioning algorithm for technoiogy-mapped designs on single-chip emulation systems. 407-410 2001 9 IEEE Trans. Very Large Scale Integr. Syst. 2 https://doi.org/10.1109/92.924064 db/journals/tvlsi/tvlsi9.html#EjniouiR01

Minesh I. Patel N. Ranganathan IDUTC: an intelligent decision-making system for urban traffic-control applications. 816-829 2001 50 IEEE Trans. Veh. Technol. 3 https://doi.org/10.1109/25.933315 db/journals/tvt/tvt50.html#PatelR01

Sanjukta Bhanja N. Ranganathan Dependency Preserving Probabilistic Modeling of Switching Activity using Bayesian Networks. 209-214 2001 conf/dac/2001 DAC https://doi.org/10.1145/378239.378465 db/conf/dac/dac2001.html#BhanjaR01 Ashok K. Murugavel N. Ranganathan Ramamurti Chandramouli Srinath Chavali Average Power in Digital CMOS Circuits using Least Square Estimation. 215-220 2001 conf/vlsid/2001 VLSI Design https://doi.org/10.1109/ICVD.2001.902663 https://doi.ieeecomputersociety.org/10.1109/ICVD.2001.902663 db/conf/vlsid/vlsid2001.html#MurugavelRCC01

Girish Chiruvolu Ravi Sankar Nagarajan Ranganathan VBR video traffic management using a predictor-based architecture. 62-70 2000 23 Comput. Commun. 1 https://doi.org/10.1016/S0140-3664(99)00137-1 db/journals/comcom/comcom23.html#ChiruvoluSR00

Hitoshi Oi N. Ranganathan Utilization of cache area in on-chip multiprocessor. 429-436 2000 24 Microprocess. Microsystems 8 https://doi.org/10.1016/S0141-9331(00)00094-6 db/journals/mam/mam24.html#OiR00

Raju D. Venkataramana N. Ranganathan New Cost Metrics for Iterative Task Assignment Algorithms in Heterogeneous Computing Systems. 160-167 2000 conf/hcw/2000 Heterogeneous Computing Workshop https://doi.org/10.1109/HCW.2000.843741 https://doi.ieeecomputersociety.org/10.1109/HCW.2000.843741 db/conf/hcw/hcw2000.html#VenkataramanaR00 Vamsi K. Srikantam N. Ranganathan Srikanth Srinivasan 0002 CREAM: Combined Register and Module Assignment with Floorplanning for Low Power Datapath Synthesis. 228-233 2000 conf/vlsid/2000 VLSI Design https://doi.org/10.1109/ICVD.2000.812613 https://doi.ieeecomputersociety.org/10.1109/ICVD.2000.812613 db/conf/vlsid/vlsid2000.html#SrikantamRS00 Abdel Ejnioui N. Ranganathan Design Partitioning on Single-Chip Emulation Systems. 234-239 2000 conf/vlsid/2000 VLSI Design https://doi.org/10.1109/ICVD.2000.812614 https://doi.ieeecomputersociety.org/10.1109/ICVD.2000.812614 db/conf/vlsid/vlsid2000.html#EjniouiR00 Abdel Ejnioui N. Ranganathan Routing on Switch Matrix Multi-FPGA Systems. 248-253 2000 conf/vlsid/2000 VLSI Design https://doi.org/10.1109/ICVD.2000.812616 https://doi.ieeecomputersociety.org/10.1109/ICVD.2000.812616 db/conf/vlsid/vlsid2000.html#EjniouiR00a

Ramamurti Chandramouli N. Ranganathan Computing the bivariate Gaussian probability integral. 129-131 1999 6 IEEE Signal Process. Lett. 6 https://doi.org/10.1109/97.763142 db/journals/spl/spl6.html#ChandramouliR99

Veeru N. Ramaswamy N. Ranganathan Kameswara Rao Namuduri Performance analysis of wavelets in embedded zerotree-based lossless image coding schemes. 884-889 1999 47 IEEE Trans. Signal Process. 3 https://doi.org/10.1109/78.747797 db/journals/tsp/tsp47.html#RamaswamyRN99

Vamsi Krishna Ramamurti Chandramouli N. Ranganathan Computation of lower bounds for switching activity using decision theory. 125-129 1999 7 IEEE Trans. Very Large Scale Integr. Syst. 1 https://doi.org/10.1109/92.748209 db/journals/tvlsi/tvlsi7.html#KrishnaCR99

Vamsi Krishna N. Ranganathan Abdel Ejnioui A tree-matching chip. 277-280 1999 7 IEEE Trans. Very Large Scale Integr. Syst. 2 https://doi.org/10.1109/92.766755 db/journals/tvlsi/tvlsi7.html#KrishnaRE99

Narayanan Vijaykrishnan N. Ranganathan Tuning Branch Predictors to Support Virtual Method Invocation in Java. 217-228 1999 conf/coots/1999 COOTS http://www.usenix.org/publications/library/proceedings/coots99/vijaykrishnan.html db/conf/coots/coots1999.html#VijaykrishnanR99 Abdel Ejnioui N. Ranganathan Multi-Terminal Net Routing for Partial Crossbar-Based Multi-FPGA Systems. 176-185 1999 conf/fpga/1999 FPGA https://doi.org/10.1145/296399.296454 db/conf/fpga/fpga99.html#EjniouiR99 Raju D. Venkataramana N. Ranganathan Multiple Cost Optimization for Task Assignment in Heterogeneous Computing Systems Using Learning Automata. 137-145 1999 conf/hcw/1999 Heterogeneous Computing Workshop https://doi.org/10.1109/HCW.1999.765118 https://doi.ieeecomputersociety.org/10.1109/HCW.1999.765118 db/conf/hcw/hcw1999.html#VenkataramanaR99 Veeraraghavan N. Ramaswamy Kamesh Namuduri Nagarajan Ranganathan Context modeling of wavelet coefficients in EZW-based lossless image coding. 3165-3168 1999 ICASSP https://doi.org/10.1109/ICASSP.1999.757513 https://doi.ieeecomputersociety.org/10.1109/ICASSP.1999.757513 conf/icassp/1999 db/conf/icassp/icassp1999.html#RamaswamyNR99 Veeru N. Ramaswamy Kameswara Rao Namuduri N. Ranganathan Context based lossless intraframe coding of video sequence using embedded zerotree wavelets. 323-326 1999 conf/iscas/1999 ISCAS (4) https://doi.org/10.1109/ISCAS.1999.780007 db/conf/iscas/iscas1999-4.html#RamaswamyNR99 Hitoshi Oi N. Ranganathan Utilization of Cache Area in On-Chip Multiprocessor. 373-380 1999 conf/ishpc/1999 ISHPC db/conf/ishpc/ishpc1999.html#OiR99 https://doi.org/10.1007/BFb0094939 Raju D. Venkataramana N. Ranganathan A Learning Automata Based Framework for Task Assignment in Heterogeneous Computing Systems. 541-547 1999 conf/sac/1999 SAC https://doi.org/10.1145/298151.298435 db/conf/sac/sac99.html#VenkataramanaR99 Vamsi Krishna N. Ranganathan Narayanan Vijaykrishnan Energy Efficient Datapath Synthesis Using Dynamic Frequency Clocking and Multiple Voltages. 440- 1999 conf/vlsid/1999 VLSI Design https://doi.org/10.1109/ICVD.1999.745195 https://doi.ieeecomputersociety.org/10.1109/ICVD.1999.745195 db/conf/vlsid/vlsid1999.html#KrishnaRV99

Girish Chiruvolu Ravi Sankar N. Ranganathan Adaptive VBR video traffic management for higher utilization of ATM networks. 27-40 1998 28 Comput. Commun. Rev. 3 https://doi.org/10.1145/293927.293929 db/journals/ccr/ccr28.html#ChiruvoluSR98

N. Ranganathan A Forum for VLSI Practitioners. 86 1998 31 Computer 10 db/journals/computer/computer31.html#Ranganathan98 http://doi.ieeecomputersociety.org/10.1109/MC.1998.10108

N. Ranganathan Raghu Sastry Raguveer Venkatesan SMAC: A VLSI Architecture for Scene Matching. 171-180 1998 4 Real Time Imaging 3 https://doi.org/10.1006/rtim.1998.0093 db/journals/rti/rti4.html#RanganathanSV98

Ramamurti Chandramouli N. Ranganathan A generalized sequential sign detector for binary hypothesis testing. 295-297 1998 5 IEEE Signal Process. Lett. 11 https://doi.org/10.1109/97.728473 db/journals/spl/spl5.html#ChandramouliR98

Raghu Sastry N. Ranganathan A VLSI Architecture for Approximate Tree Matching. 346-352 1998 47 IEEE Trans. Computers 3 db/journals/tc/tc47.html#SastryR98 https://doi.org/10.1109/12.660171 http://doi.ieeecomputersociety.org/10.1109/12.660171

Ramamurti Chandramouli N. Ranganathan Shivaraman J. Ramadoss Adaptive quantization and fast error-resilient entropy coding for image transmission. 411-421 1998 8 IEEE Trans. Circuits Syst. Video Technol. 4 https://doi.org/10.1109/76.709408 db/journals/tcsv/tcsv8.html#ChandramouliRR98

Nagarajan Ranganathan Narayanan Vijaykrishnan N. Bhavanishankar A linear array processor with dynamic frequency clocking for image processing applications. 435-445 1998 8 IEEE Trans. Circuits Syst. Video Technol. 4 https://doi.org/10.1109/76.709410 db/journals/tcsv/tcsv8.html#RanganathanVB98

Ramamurti Chandramouli N. Ranganathan Shivaraman J. Ramadoss Empirical Channel Matched Quantizer Design and UEP for Robust Image Transmission. 531 1998 conf/dcc/1998 Data Compression Conference https://doi.org/10.1109/DCC.1998.672245 https://doi.ieeecomputersociety.org/10.1109/DCC.1998.672245 db/conf/dcc/dcc98.html#ChandramouliRR98 Narayanan Vijaykrishnan N. Ranganathan Ravi Gadekarla Object-Oriented Architectural Support for a Java Processor. 330-354 https://doi.org/10.1007/BFb0054098 1998 conf/ecoop/1998 ECOOP db/conf/ecoop/ecoop98.html#VijaykrishnanRG98 Vamsi Krishna N. Ranganathan A Methodology for High Level Power Estimation and Exploration. 420-425 1998 conf/glvlsi/1998 Great Lakes Symposium on VLSI https://doi.org/10.1109/GLSV.1998.665337 https://doi.ieeecomputersociety.org/10.1109/GLSV.1998.665337 db/conf/glvlsi/glvlsi1998.html#KrishnaR98 Girish Chiruvolu Tapas K. Das Ravi Sankar N. Ranganathan A scene-based generalized Markov chain model for VBR video traffic. 554-558 1998 ICC https://doi.org/10.1109/ICC.1998.682940 conf/icc/1998 db/conf/icc/icc1998.html#ChiruvoluDSR98 Raju D. Venkataramana N. Ranganathan A simple adaptive wormhole routing algorithm for MIMD systems. 205-207 1998 conf/iccd/1998 ICCD https://doi.org/10.1109/ICCD.1998.727048 https://doi.ieeecomputersociety.org/10.1109/ICCD.1998.727048 db/conf/iccd/iccd1998.html#VenkataramanaR98 Ramamurti Chandramouli Sharad Kumar N. Ranganathan Joint Optimization of Quantization and On-Line Channel Estimation for Low Bit-Rate Video Transmission. 649-653 1998 conf/icip/1998 ICIP (1) db/conf/icip/icip1998-1.html#ChandramouliKR98 https://doi.org/10.1109/ICIP.1998.723583 https://doi.ieeecomputersociety.org/10.1109/ICIP.1998.723583 Girish Chiruvolu Ravi Sankar Nagarajan Ranganathan An adaptive scheme for better utilization with QoS constraints for VBR video traffic in ATM networks. 3-7 1998 ISCC https://doi.org/10.1109/ISCC.1998.702423 https://doi.ieeecomputersociety.org/10.1109/ISCC.1998.702423 conf/iscc/1998 db/conf/iscc/iscc1998.html#ChiruvoluSR98 Ramamurti Chandramouli Sharad Kumar N. Ranganathan Rate control for a video coder using learning automata. 4630-4635 1998 SMC https://doi.org/10.1109/ICSMC.1998.727582 conf/smc/1998 db/conf/smc/smc1998.html#ChandramouliKR98 Vamsi Krishna Ramamurti Chandramouli N. Ranganathan Computation of Lower and Upper Bounds for Switching Activity: A Unified Approach. 230-233 1998 conf/vlsid/1998 VLSI Design db/conf/vlsid/vlsid1998.html#KrishnaCR98 https://doi.org/10.1109/ICVD.1998.646608 https://doi.ieeecomputersociety.org/10.1109/ICVD.1998.646608 Nagarajan Ranganathan Rajat Anand Girish Chiruvolu A VLSI ATM Switch Architecture for VBR Traffic. 420-427 1998 conf/vlsid/1998 VLSI Design db/conf/vlsid/vlsid1998.html#RanganathanAC98 https://doi.org/10.1109/ICVD.1998.646644 https://doi.ieeecomputersociety.org/10.1109/ICVD.1998.646644 Hitoshi Oi N. Ranganathan Effect of Message Length and Processor Speed on the Performance of the Bidirectional Ring-Based Multiprocessor. 267-272 1997 conf/iccd/1997 ICCD db/conf/iccd/iccd97.html#OiR97 https://doi.org/10.1109/ICCD.1997.628878 https://doi.ieeecomputersociety.org/10.1109/ICCD.1997.628878 Veeru N. Ramaswamy Kameswara Rao Namuduri N. Ranganathan Performance Analysis of Wavelets in Embedded Zerotree-Based Lossless Image Coding Schemes. 278-281 1997 conf/icip/1997 ICIP (2) https://doi.org/10.1109/ICIP.1997.638742 https://doi.ieeecomputersociety.org/10.1109/ICIP.1997.638742 db/conf/icip/icip1997-2.html#RamaswamyNR97 Ashley Rasquinha N. Ranganathan C3L: A Chip for Connected Component Labeling. 446-450 1997 conf/vlsid/1997 VLSI Design https://doi.org/10.1109/ICVD.1997.568174 https://doi.ieeecomputersociety.org/10.1109/ICVD.1997.568174 db/conf/vlsid/vlsid1997.html#RasquinhaR97 Minesh I. Patel N. Ranganathan A VLSI System Architecture For Real-Time Intelligent Decision Making. 221-230 1996 conf/asap/1996 ASAP https://doi.org/10.1109/ASAP.1996.542817 https://doi.ieeecomputersociety.org/10.1109/ASAP.1996.542817 db/conf/asap/asap1996.html#PatelR96 Nagarajan Ranganathan Rajesh Chandra A linear systolic algorithm and architecture for convex bipartite matching. 379-384 1996 HiPC https://doi.org/10.1109/HIPC.1996.565851 https://doi.ieeecomputersociety.org/10.1109/HIPC.1996.565851 conf/hipc/1996 db/conf/hipc/hipc1996.html#RanganathanC96 N. Ranganathan Narayanan Vijaykrishnan N. Bhavanishankar A VLSI array architecture with dynamic frequency clocking. 137-140 1996 conf/iccd/1996 ICCD https://doi.org/10.1109/ICCD.1996.563547 https://doi.ieeecomputersociety.org/10.1109/ICCD.1996.563547 db/conf/iccd/iccd1996.html#RanganathanVB96 S. B. Aruru N. Ranganathan Kameswara Rao Namuduri A VLSI chip for image compression using variable block size segmentation. 500-505 1996 conf/iccd/1996 ICCD https://doi.org/10.1109/ICCD.1996.563599 https://doi.ieeecomputersociety.org/10.1109/ICCD.1996.563599 db/conf/iccd/iccd1996.html#AruruRN96 Narayanan Vijaykrishnan Nagarajan Ranganathan N. Bhavanishankar DFLAP: a dynamic frequency linear array processor. 1007-1010 1996 conf/icip/1996 ICIP (2) https://doi.org/10.1109/ICIP.1996.561076 db/conf/icip/icip1996-2.html#VijaykrishnanRB96 Minesh I. Patel N. Ranganathan PANTHER: a parallel neuro-systolic architecture for real-time processing. 1006-1011 1996 ICNN https://doi.org/10.1109/ICNN.1996.549035 conf/icnn/1996 db/conf/icnn/icnn1996.html#PatelR96 S. B. Aruru N. Ranganathan Kameswara Rao Namuduri A VLSI system architecture for lossless image compression. 594-598 1996 ICPR https://doi.org/10.1109/ICPR.1996.547634 https://doi.ieeecomputersociety.org/10.1109/ICPR.1996.547634 conf/icpr/1996 db/conf/icpr/icpr1996.html#AruruRN96 N. Ranganathan N. Bhavanishankar Narayanan Vijaykrishnan A dynamic frequency linear array processor for image processing. 611-615 1996 ICPR https://doi.org/10.1109/ICPR.1996.547637 https://doi.ieeecomputersociety.org/10.1109/ICPR.1996.547637 conf/icpr/1996 db/conf/icpr/icpr1996.html#RanganathanBV96 S. Arumugavelu N. Ranganathan SIMD algorithms for single link and complete link pattern clustering. 625-629 1996 ICPR https://doi.org/10.1109/ICPR.1996.547640 https://doi.ieeecomputersociety.org/10.1109/ICPR.1996.547640 conf/icpr/1996 db/conf/icpr/icpr1996.html#ArumugaveluR96 Kameswara Rao Namuduri N. Ranganathan Hooman Rashedi SVBS: a high-resolution medical image compression algorithm using slicing with variable block size segmentation. 919-923 1996 ICPR https://doi.org/10.1109/ICPR.1996.547302 https://doi.ieeecomputersociety.org/10.1109/ICPR.1996.547302 conf/icpr/1996 db/conf/icpr/icpr1996.html#NamuduriRR96 Veeru N. Ramaswamy Kameswara Rao Namuduri N. Ranganathan Lossless image compression using wavelet decomposition. 924-928 1996 ICPR https://doi.org/10.1109/ICPR.1996.547303 https://doi.ieeecomputersociety.org/10.1109/ICPR.1996.547303 conf/icpr/1996 db/conf/icpr/icpr1996.html#RamaswamyNR96 Minesh I. Patel N. Ranganathan An intelligent system architecture for urban traffic control applications. 10-17 1996 SPDP https://doi.org/10.1109/SPDP.1996.570311 https://doi.ieeecomputersociety.org/10.1109/SPDP.1996.570311 conf/spdp/1996 db/conf/spdp/spdp96.html#PatelR96 Nina Saxena Sudeep Sarkar N. Ranganathan Mapping and parallel implementation of Bayesian belief networks. 608-611 1996 SPDP https://doi.org/10.1109/SPDP.1996.570391 conf/spdp/1996 db/conf/spdp/spdp96.html#SaxenaSR96 Vamsi Krishna Abdel Ejnioui N. Ranganathan A tree matching chip. 280-285 1996 conf/vlsid/1996 VLSI Design https://doi.org/10.1109/ICVD.1996.489611 https://doi.ieeecomputersociety.org/10.1109/ICVD.1996.489611 db/conf/vlsid/vlsid1996.html#KrishnaER96 Narayanan Vijaykrishnan N. Ranganathan SUBGEN: a genetic approach for subcircuit extraction. 343-345 1996 conf/vlsid/1996 VLSI Design https://doi.org/10.1109/ICVD.1996.489632 https://doi.ieeecomputersociety.org/10.1109/ICVD.1996.489632 db/conf/vlsid/vlsid1996.html#VijaykrishnanR96

N. Ranganathan Sharad C. Seth Conference Reports. 5, 81 1995 12 IEEE Des. Test Comput. 2 db/journals/dt/dt12.html#RanganathanS95

Raghu Sastry N. Ranganathan PMAC: A Polygon Matching Chip. 367-385 1995 9 Int. J. Pattern Recognit. Artif. Intell. 2 db/journals/ijprai/ijprai9.html#SastryR95 https://doi.org/10.1142/S0218001495000171

Raghu Sastry N. Ranganathan Klinton Remedios CASM: A VLSI Chip for Approximate String Matching. 824-830 1995 17 IEEE Trans. Pattern Anal. Mach. Intell. 8 https://doi.org/10.1109/34.400575 http://doi.ieeecomputersociety.org/10.1109/34.400575 db/journals/pami/pami17.html#SastryRR95

Raghu Sastry N. Ranganathan Ramesh C. Jain VLSI Architectures for High-Speed Range Estimation. 894-899 1995 17 IEEE Trans. Pattern Anal. Mach. Intell. 9 https://doi.org/10.1109/34.406655 http://doi.ieeecomputersociety.org/10.1109/34.406655 db/journals/pami/pami17.html#SastryRJ95

Mario Kovac N. Ranganathan JAGUAR: a fully pipelined VLSI architecture for JPEG image compression standard. 247-258 1995 83 Proc. IEEE 2 https://doi.org/10.1109/5.364464 db/journals/pieee/pieee83.html#KovacR95

Nagarajan Ranganathan Steve G. Romaniuk Kameswara Rao Namuduri A lossless image compression algorithm using variable block size segmentation. 1396-1406 1995 4 IEEE Trans. Image Process. 10 https://doi.org/10.1109/83.465104 https://www.wikidata.org/entity/Q39835896 db/journals/tip/tip4.html#RanganathanRN95

Nagarajan Ranganathan Rajiv Mehrotra S. Subramaniam 0001 A high speed systolic architecture for labeling connected components in an image. 415-423 1995 25 IEEE Trans. Syst. Man Cybern. 3 https://doi.org/10.1109/21.364855 db/journals/tsmc/tsmc25.html#RanganathanMS95

Mario Kovac N. Ranganathan Martin Zagar A prototype VLSI chip architecture for JPEG image compression. 2-6 1995 ED&TC https://doi.org/10.1109/EDTC.1995.470428 https://doi.ieeecomputersociety.org/10.1109/EDTC.1995.470428 https://dl.acm.org/doi/10.5555/787258.787410 conf/date/1995 db/conf/date/edtc1995.html#KovacRZ95 N. Ranganathan K. B. Doreswamy A systolic algorithm and architecture for image thinning. 138-143 1995 conf/glvlsi/1995 Great Lakes Symposium on VLSI https://doi.org/10.1109/GLSV.1995.516040 https://doi.ieeecomputersociety.org/10.1109/GLSV.1995.516040 http://dl.acm.org/citation.cfm?id=797369 db/conf/glvlsi/glvlsi1995.html#RanganathanD95 Raghu Sastry N. Ranganathan A VLSI Architecture for Computer the Tree-to-Tree Distance. 330-339 1995 conf/hpca/1995 HPCA db/conf/hpca/hpca1995.html#SastryR95 https://doi.org/10.1109/HPCA.1995.386530 https://doi.ieeecomputersociety.org/10.1109/HPCA.1995.386530 Abdel Ejnioui N. Ranganathan Systolic algorithms for tree pattern matching. 650-702 1995 conf/iccd/1995 ICCD https://doi.org/10.1109/ICCD.1995.528937 https://doi.ieeecomputersociety.org/10.1109/ICCD.1995.528937 db/conf/iccd/iccd1995.html#EjniouiR95 Mario Kovac N. Ranganathan JAGUAR: a high speed VLSI chip for JPEG image compression standard. 220-224 1995 conf/vlsid/1995 VLSI Design https://doi.org/10.1109/ICVD.1995.512112 https://doi.ieeecomputersociety.org/10.1109/ICVD.1995.512112 db/conf/vlsid/vlsid1995.html#KovacR95

N. Ranganathan Raghu Sastry VLSI Architectures for Pattern Matching. 815-843 1994 8 Int. J. Pattern Recognit. Artif. Intell. 4 db/journals/ijprai/ijprai8.html#RanganathanS94 https://doi.org/10.1142/S0218001494000425

Ken Hughes N. Ranganathan Modeling Sensor Confidence for Sensor Integration Tasks. 1301-1318 1994 8 Int. J. Pattern Recognit. Artif. Intell. 6 db/journals/ijprai/ijprai8.html#HughesR94 https://doi.org/10.1142/S0218001494000656

Kameswara Rao Namuduri Rajiv Mehrotra Nagarajan Ranganathan Efficient computation of gabor filter based multiresolution responses. 925-938 1994 27 Pattern Recognit. 7 https://doi.org/10.1016/0031-3203(94)90158-9 db/journals/pr/pr27.html#NamuduriMR94

N. Ranganathan Satish Venugopal A VLSI Chip for Template Matching. 542-545 1994 conf/iccd/1994 ICCD db/conf/iccd/iccd1994.html#RanganathanV94 https://doi.org/10.1109/ICCD.1994.331971 https://doi.ieeecomputersociety.org/10.1109/ICCD.1994.331971 N. Ranganathan Satish Venugopal An Efficient VLSI Architecture for Template Matching. 224-231 1994 conf/icpp/1994-1 ICPP (1) db/conf/icpp/icpp1994-1.html#RanganathanV94 https://doi.org/10.1109/ICPP.1994.54 https://doi.ieeecomputersociety.org/10.1109/ICPP.1994.54 N. Ranganathan Steve G. Romaniuk Kameswara Rao Namuduri A lossless image compression algorithm using variable block size segmentation. 40-44 1994 ICPR (3) https://doi.org/10.1109/ICPR.1994.577118 https://doi.ieeecomputersociety.org/10.1109/ICPR.1994.577118 conf/icpr/1994-3 db/conf/icpr/icpr1994-3.html#RanganathanRN94 N. Ranganathan Satish Venugopal An efficient VLSI architecture for template matching based on moment preserving pattern matching. 388-390 1994 ICPR (3) https://doi.org/10.1109/ICPR.1994.577211 https://doi.ieeecomputersociety.org/10.1109/ICPR.1994.577211 conf/icpr/1994-3 db/conf/icpr/icpr1994-3.html#RanganathanV94 N. Ranganathan Bharadwaj Parthasarathy Ken Hughes A Parallel Algorithm and Architecture for Robot Path Planning. 275-279 1994 conf/ipps/1994 IPPS db/conf/ipps/ipps1994.html#RanganathanPH94 https://doi.org/10.1109/IPPS.1994.288289 https://doi.ieeecomputersociety.org/10.1109/IPPS.1994.288289 Mario Kovac N. Ranganathan ACE: A VLSI Chip for Galois Field GF (2m) Based Exponentiation. 291-296 1994 conf/vlsid/1994 VLSI Design db/conf/vlsid/vlsid1994.html#KovacR94 https://doi.org/10.1109/ICVD.1994.282705

Mario Kovac N. Ranganathan M. Varanasi SIGMA: a VLSI systolic array implementation of a Galois field GF(2 m) based multiplication and division algorithm. 22-30 1993 1 IEEE Trans. Very Large Scale Integr. Syst. 1 https://doi.org/10.1109/92.219904 db/journals/tvlsi/tvlsi1.html#KovacRV93

Amar Mukherjee N. Ranganathan Jeffrey W. Flieder Tinku Acharya MARVLE: a VLSI chip for data compression using tree-based codes. 203-214 1993 1 IEEE Trans. Very Large Scale Integr. Syst. 2 https://doi.org/10.1109/92.238415 db/journals/tvlsi/tvlsi1.html#MukherjeeRFA93

Raghu Sastry N. Ranganathan Horst Bunke VLSI architectures for polygon recognition. 398-407 1993 1 IEEE Trans. Very Large Scale Integr. Syst. 4 https://doi.org/10.1109/92.250186 db/journals/tvlsi/tvlsi1.html#SastryRB93

N. Ranganathan Raghu Sastry Raguveer Venkatesan Joseph W. Yoder David C. Keezer SMAC: A Scene Matching Chip. 184-187 1993 conf/iccd/1993 ICCD db/conf/iccd/iccd1993.html#RanganathanSVYK93 https://doi.org/10.1109/ICCD.1993.393384 https://doi.ieeecomputersociety.org/10.1109/ICCD.1993.393384 Raghu Sastry N. Ranganathan A Systolic Array for Approximate String Matching. 402-405 1993 conf/iccd/1993 ICCD db/conf/iccd/iccd1993.html#SastryR93 https://doi.org/10.1109/ICCD.1993.393344 https://doi.ieeecomputersociety.org/10.1109/ICCD.1993.393344 Ken Hughes N. Ranganathan A Model for Determining Sensor Confidence. 136-141 1993 conf/icra/1993 ICRA (2) db/conf/icra/icra1993-2.html#HughesR93 https://doi.org/10.1109/ROBOT.1993.292137 Raghu Sastry N. Ranganathan Ramesh C. Jain VLSI Architectures for Depth Estimation Using Intensity Gradient Analysis. 700-704 1993 conf/ipps/1993 IPPS db/conf/ipps/ipps1993.html#SastryRJ93 https://doi.org/10.1109/IPPS.1993.262795 https://doi.ieeecomputersociety.org/10.1109/IPPS.1993.262795 Mario Kovac N. Ranganathan M. Varanasi SIGMA: A VLSI Chip for Galois Field GF(2m) Based Multiplication and Division. 25-30 1993 conf/vlsid/1993 VLSI Design db/conf/vlsid/vlsid1993.html#KovacRV93 https://doi.org/10.1109/ICVD.1993.669630 https://doi.ieeecomputersociety.org/10.1109/ICVD.1993.669630 Raghu Sastry N. Ranganathan Horst Bunke Hardware Algorithms for Polygon Matching. 41-44 1993 conf/vlsid/1993 VLSI Design db/conf/vlsid/vlsid1993.html#SastryRB93 https://doi.org/10.1109/ICVD.1993.669635 https://doi.ieeecomputersociety.org/10.1109/ICVD.1993.669635

N. Ranganathan K. R. Balaji Hassan N. Srinidhi A VLSI systolic array processor chip for computing joins in a relational database. 227-236 1992 16 Microprocess. Microsystems 5 https://doi.org/10.1016/0141-9331(92)90065-2 db/journals/mam/mam16.html#RanganathanBS92

Rajiv Mehrotra Kameswara Rao Namuduri Nagarajan Ranganathan Gabor filter-based edge detection. 1479-1494 1992 25 Pattern Recognit. 12 https://doi.org/10.1016/0031-3203(92)90121-X db/journals/pr/pr25.html#MehrotraaR92

Amar Mukherjee Jeffrey W. Flieder N. Ranganathan MARVLE: A VLSI Chip for Variable Length Encoding and Decoding. 170-173 1992 conf/iccd/1992 ICCD db/conf/iccd/iccd1992.html#MukherjeeFR92 https://doi.org/10.1109/ICCD.1992.276242 https://doi.ieeecomputersociety.org/10.1109/ICCD.1992.276242 Minesh I. Patel Patrick McCabe N. Ranganathan SIBA: a VLSI systolic array chip for image processing. 15-18 1992 ICPR (4) https://doi.org/10.1109/ICPR.1992.202118 conf/icpr/1992-4 db/conf/icpr/icpr1992-4.html#PatelMR92 V. K. Sundaresan Sanjay Nichani N. Ranganathan Ravi Sankar A VLSI hardware accelerator for dynamic time warping. 27-30 1992 ICPR (4) https://doi.org/10.1109/ICPR.1992.202121 conf/icpr/1992-4 db/conf/icpr/icpr1992-4.html#SundaresanNRS92 R. Venkatesan Raghu Sastry N. Ranganathan A VLSI architecture for hierarchical scene matching. 214-217 1992 ICPR (4) https://doi.org/10.1109/ICPR.1992.202169 conf/icpr/1992-4 db/conf/icpr/icpr1992-4.html#VenkatesanSR92 Kameswara Rao Namuduri Rajiv Mehrotra N. Ranganathan Edge detection models based on Gabor filters. 729-732 1992 ICPR (3) https://doi.org/10.1109/ICPR.1992.202090 conf/icpr/1992-3 db/conf/icpr/icpr1992-3.html#NamuduriMR92 Mario Kovac N. Ranganathan M. Varanasi A Systolic Algorithm and Architecture for Galois Field Arithmetic. 283-288 1992 conf/ipps/1992 IPPS db/conf/ipps/ipps1992.html#KovacRV92 https://doi.org/10.1109/IPPS.1992.223032 https://doi.ieeecomputersociety.org/10.1109/IPPS.1992.223032 Ken Hughes Alade Tokuta N. Ranganathan trulla : An Algorithm For Path Planning Among Weighted Regions By Localized Propagations. 469-476 1992 IROS https://doi.org/10.1109/IROS.1992.587377 conf/iros/1992 db/conf/iros/iros1992.html#HughesTR92 N. Ranganathan Rajiv Mehrotra S. Kurji A CMOS VLSI Chip for Motion Detection. 209-214 1992 VLSI Design https://doi.org/10.1109/ICVD.1992.658049 https://doi.ieeecomputersociety.org/10.1109/ICVD.1992.658049 conf/vlsid/1992 db/conf/vlsid/vlsid1992.html#RanganathanMK92 N. Ranganathan Minesh I. Patel Patrick McCabe A Two-dimensional Systolic Array Processor for Image Processing. 215-220 1992 VLSI Design https://doi.org/10.1109/ICVD.1992.658050 https://doi.ieeecomputersociety.org/10.1109/ICVD.1992.658050 conf/vlsid/1992 db/conf/vlsid/vlsid1992.html#RanganathanPM92

N. Ranganathan Rajiv Mehrotra A VLSI architecture for dynamic scene analysis. 189-197 1991 53 CVGIP Image Underst. 2 https://doi.org/10.1016/1049-9660(91)90026-L db/journals/cviu/cviu53.html#RanganathanM91

N. Ranganathan Sanjay Nichani Rajiv Mehrotra A VLSI architecture for a half-edge-based corner detector. 165-181 1991 4 Mach. Vis. Appl. 3 https://doi.org/10.1007/BF01230199 db/journals/mva/mva4.html#RanganathanNM91

N. Ranganathan Rajiv Mehrotra Kameswara Rao Namuduri An architecture to implement multiresolution. 1157-1160 1991 ICASSP https://doi.org/10.1109/ICASSP.1991.150577 conf/icassp/1991 db/conf/icassp/icassp1991.html#RanganathanMN91 Nagarajan Ranganathan Rajiv Mehrotra S. Subramaniam 0001 A high speed systolic architecture for labeling connected components in an image. 818-825 1991 SPDP https://doi.org/10.1109/SPDP.1991.218236 https://doi.ieeecomputersociety.org/10.1109/SPDP.1991.218236 conf/spdp/1991 db/conf/spdp/spdp1991.html#RanganathanMS91

Rajiv Mehrotra Sanjay Nichani Nagarajan Ranganathan Corner detection. 1223-1233 1990 23 Pattern Recognit. 11 https://doi.org/10.1016/0031-3203(90)90118-5 db/journals/pr/pr23.html#MehrotraNR90

Sanjay Nichani N. Ranganathan SAP: design of a systolic array processor for computation in vision. 315-318 1990 ICCD https://doi.org/10.1109/ICCD.1990.130237 https://doi.ieeecomputersociety.org/10.1109/ICCD.1990.130237 conf/iccd/1990 db/conf/iccd/iccd1990.html#NichaniR90 K. R. Namaduri Rajiv Mehrotra N. Ranganathan Fast spatiotemporal filters. 479-483 1990 ICPR (2) https://doi.org/10.1109/ICPR.1990.119405 conf/icpr/1990-2 db/conf/icpr/icpr1990-2.html#NamaduriMR90 N. Ranganathan Rajiv Mehrotra A VLSI architecture for difference picture-based dynamic scene analysis. 506-508 1990 ICPR (2) https://doi.org/10.1109/ICPR.1990.119411 conf/icpr/1990-2 db/conf/icpr/icpr1990-2.html#RanganathanM90 N. Ranganathan Hassan N. Srinidhi Effect of Data Compression Hardware on the Performance of a Relational Database Machine. 144-146 1990 conf/parbase/1990 PARBASE db/conf/parbase/parbase90.html#RanganathanS90 https://doi.org/10.1109/PARBSE.1990.77134 Selwyn Henriques N. Ranganathan A parallel architecture for data compression. 260-266 1990 conf/spdp/1990 SPDP https://doi.org/10.1109/SPDP.1990.143545 https://doi.ieeecomputersociety.org/10.1109/SPDP.1990.143545 db/conf/spdp/spdp90.html#HenriquesR90

Mostafa A. Bassiouni Amar Mukherjee N. Ranganathan Enhancing arithmetic and tree-based coding. 293-305 1989 25 Inf. Process. Manag. 3 https://doi.org/10.1016/0306-4573(89)90046-0 db/journals/ipm/ipm25.html#BassiouniMR89

Amar Mukherjee N. Ranganathan Mostafa A. Bassiouni Adaptive and pipelined VLSI designs for tree-based codes. 369-372 1989 ICCD https://doi.org/10.1109/ICCD.1989.63390 conf/iccd/1989 db/conf/iccd/iccd1989.html#MukherjeeRB89 Mostafa A. Bassiouni Amar Mukherjee N. Ranganathan On Software and Hardware Techniques of Data Engineering. 208-215 ICDE89/P208.pdf 1989 ICDE db/conf/icde/icde89.html#BassiouniMR89 conf/icde/89 https://doi.org/10.1109/ICDE.1989.47216 https://doi.ieeecomputersociety.org/10.1109/ICDE.1989.47216 journals/tse/Bassiouni85 journals/is/VassiouniO86 ... conf/vldb/EggersS80 conf/vldb/EggersOS81 conf/sigmod/X82 ... conf/sigir/MukherjeeB87 journals/computer/Welch84 journals/cacm/WittenNC87 N. Ranganathan Rajiv Mehrotra A VLSI system for difference picture-based motion analysis. 592-597 1989 TAI https://doi.org/10.1109/TAI.1989.65372 https://doi.ieeecomputersociety.org/10.1109/TAI.1989.65372 conf/ictai/1989 db/conf/ictai/ictai1989.html#RanganathanM89

N. Ranganathan Mubarak Shah A VLSI architecture for computing scale space. 178-204 1988 43 Comput. Vis. Graph. Image Process. 2 https://doi.org/10.1016/0734-189X(88)90060-6 db/journals/cvgip/cvgip43.html#RanganathanS88

Mostafa A. Bassiouni N. Ranganathan Amar Mukherjee A scheme for data compression in supercomputers. 272-278 1988 conf/sc/1988 SC https://doi.org/10.1109/SUPERC.1988.44663 https://doi.ieeecomputersociety.org/10.1109/SUPERC.1988.44663 http://dl.acm.org/citation.cfm?id=63008 db/conf/sc/sc1988.html#BassiouniRM88 Mostafa A. Bassiouni N. Ranganathan Amar Mukherjee Software and Hardware Enhancement of Arithmetic Coding. 120-132 SSDBM88/P120.pdf 1988 SSDBM db/conf/ssdbm/ssdbm88.html#BassiouniRM88 conf/ssdbm/88 https://doi.org/10.1007/BFb0027509 https://dl.acm.org/doi/10.5555/646492.695119 ... journals/is/VassiouniO86 conf/vldb/EggersS80 conf/vldb/EggersOS81 journals/jacm/SmithS85 conf/vldb/Hawthorn82 ... journals/cj/Lea78 conf/sigir/MukherjeeB87 ... journals/computer/Welch84 journals/cacm/WittenNC87 Tinku Acharya Santosh Aditham Rajat Anand S. Arumugavelu S. B. Aruru K. R. Balaji Karthikeyan Balakrishnan Mostafa A. Bassiouni Sanjukta Bhanja Apeksha Bhatt Koustav Bhattacharya N. Bhavanishankar Thomas Bingel Horst Bunke Tony Casagrande Hari Chakravarthula Rajesh Chandra Nandhini Chandramoorthy Rajarathnam Chandramouli Ramamurti Chandramouli Sunil K. Chappidi Srinath Chavali Donald M. Chiarulli Girish Chiruvolu Matthew Cotter Tapas K. Das Suman Datta K. B. Doreswamy Abdel Ejnioui Jeffrey W. Flieder Ravi Gadekarla Marina L. Gavrilova Upavan Gupta Narender Hanchate J. E. Harlow Justin E. Harlow III Selwyn Henriques Ken Hughes Ransford Hyman Jr. Ramesh C. Jain Matthew Jerry Srinivas Katkoori David C. Keezer Soontae Kim Saurabh Kotiyal Elias Kougianos Mario Kovac Vamsi Krishna Sharad Kumar Sandip Kundu S. Kurji Steven P. Levitan Matthew Lewandowski Xueqing Li 0002 Jay Ligatti Karthikeyan Lingasubramanian Huichu Liu Venkataraman Mahalingam Patrick McCabe Rajiv Mehrotra Saraju P. Mohanty Matthew MorrisonMatthew A. Morrison Amar Mukherjee Robin R. Murphy Ashok K. Murugavel K. R. Namaduri Ravi Namballa Kamesh NamuduriKameswara Rao Namuduri Sanjay Nichani Hitoshi Oi Aswath Oruganti Bharadwaj Parthasarathy Minesh I. Patel Kevin S. Pratt Shivaraman J. Ramadoss Veeru N. RamaswamyVeeraraghavan N. Ramaswamy Hooman Rashedi Ashley Rasquinha Arijit Raychowdhury Klinton Remedios Steve G. Romaniuk Soumyaroop Roy Viswanath Sairaman Jack SampsonJohn Sampson Ravi Sankar Sudeep Sarkar Raghu Sastry R. Sathyamurthy Nina Saxena Sharad C. Seth Mubarak Shah Nikhil Shukla Neeta S. Singh K. Sitaraman Vamsi K. Srikantam Hassan N. Srinidhi Srikanth Srinivasan 0002 K. P. SubbalakshmiKoduvayur P. Subbalakshmi S. Subramaniam 0001 V. K. Sundaresan C. J. Kenneth Tan Himanshu Thapliyal Alade O. TokutaAlade Tokuta Wei-Yu Tsai M. Varanasi Raju D. Venkataramana R. Venkatesan Raguveer Venkatesan Satish Venugopal Narayanan VijaykrishnanVijaykrishnan Narayanan Deanne Tran Vo Yue Wang Baihua Xie Joseph W. Yoder Martin Zagar