"FPGA and ASIC square root designs for high performance and power efficiency."

Shashank Suresh, Spiridon F. Beldianu, Sotirios G. Ziavras (2013)

> Home

Details and statistics

DOI: 10.1109/ASAP.2013.6567588

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

- view
  authority control:
- export record
  dblp key:
  - conf/asap/SureshBZ13
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/asap/SureshBZ13
Shashank Suresh, Spiridon F. Beldianu, Sotirios G. Ziavras:
FPGA and ASIC square root designs for high performance and power efficiency. ASAP 2013: 269-272

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.