"A topology optimization method for low-power logic circuits with ..."

Haotian Zhu et al. (2017)

> Home

Details and statistics

DOI: 10.1109/PATMOS.2017.8106953

access: closed

type: Conference or Workshop Paper

metadata version: 2017-11-23

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/patmos/ZhuHYXY17
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/patmos/ZhuHYXY17
Haotian Zhu, Jianping Hu, Huishan Yang, Yang Xiong, Tingfeng Yang:
A topology optimization method for low-power logic circuits with dual-threshold independent-gate FinFETs. PATMOS 2017: 1-6

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.