Xiaoyun Li

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Weiliang Jing

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Publications

2017
[j21]
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Yuan Du, Yong Ye, Weiliang Jing, Zhenhua Li, Xiaoyun Li, Zhitang Song, Bomy Chen:
Multi-core architecture with asynchronous clocks to prevent power analysis attacks. IEICE Electron. Express 14(4): 20161220 (2017)
[j19]
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Yong Ye, Yuan Du, Weiliang Jing, Xiaoyun Li, Zhitang Song, Bomy Chen:
CAM-based retention-aware DRAM (CRA-DRAM) for refresh power reduction. IEICE Electron. Express 14(10): 20170053 (2017)
[j18]
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Yong Ye, Yuan Du, Weiliang Jing, Xiaoyun Li, Zhitang Song, Bomy Chen:
Erratum: CAM-based retention-aware DRAM (CRA-DRAM) for refresh power reduction [IEICE Electronics Express Vol. 14 (2017) No. 10 pp. 20170053]. IEICE Electron. Express 14(11): 20178001 (2017)
[j15]
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Yuan Du, Yong Ye, Weiliang Jing, Xiaoyun Li, Zhitang Song, Bomy Chen:
Logic area reduction using the deep trench isolation technique based on 40 nm embedded PCM process. IEICE Electron. Express 14(15): 20170628 (2017)

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