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Comparison of ARM processors: Difference between revisions

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→ARMv8-A: Splitted column of DMIPS and clock speed
Line 169: Line 169:
! rowspan="2" | L3 cache
! rowspan="2" | L3 cache
! rowspan="2" | Core<br />configu-<br />rations
! rowspan="2" | Core<br />configu-<br />rations
! rowspan="2" | [[Dhrystone#Results|DMIPS/<br />MHz]]{{refn|group=note|name=first|As [[Dhrystone]] (implied in "DMIPS") is a synthetic benchmark developed in 1980s, it is no longer representative of prevailing workloads{{snd}} use with caution.}}
! rowspan="2" | Speed per core ([[Dhrystone#Results|DMIPS/<br />MHz]]{{refn|group=note|name=first|As [[Dhrystone]] (implied in "DMIPS") is a synthetic benchmark developed in 1980s, it is no longer representative of prevailing workloads{{snd}} use with caution.}})
! rowspan="2" | [[Clock rate]]
! rowspan="2" | ARM part number (in the main ID register)
! rowspan="2" | ARM part number (in the main ID register)
|-
|-
Line 180: Line 181:
| ARMv8.0-A<br /><small>(only [[32-bit]])</small> || 2-wide || 8 || {{No}} || 0 || {{dunno}} || {{Yes|LITTLE}} || {{dunno}} || {{dunno}}
| ARMv8.0-A<br /><small>(only [[32-bit]])</small> || 2-wide || 8 || {{No}} || 0 || {{dunno}} || {{Yes|LITTLE}} || {{dunno}} || {{dunno}}
| 28<ref>{{Cite web|url=https://www.arm.com/about/newsroom/new-ultra-efficient-arm-cortex-a32-processor-expands-embedded-and-iot-portfolio.php|title=New Ultra-efficient ARM Cortex-A32 Processor Expands… – ARM|website=arm.com|access-date=2016-10-01}}</ref>
| 28<ref>{{Cite web|url=https://www.arm.com/about/newsroom/new-ultra-efficient-arm-cortex-a32-processor-expands-embedded-and-iot-portfolio.php|title=New Ultra-efficient ARM Cortex-A32 Processor Expands… – ARM|website=arm.com|access-date=2016-10-01}}</ref>
| {{No}} || {{No}} || 8–64 + 8–64 || 0–1&nbsp;MiB || {{No}} || 1–4+ || {{dunno}} || 0xD01
| {{No}} || {{No}} || 8–64 + 8–64 || 0–1&nbsp;MiB || {{No}} || 1–4+ || {{dunno}} || {{dunno}} || 0xD01
|-
|-
![[Arm Cortex-A34|Cortex-A34 (64-bit)]]<ref>{{Cite web|url=https://developer.arm.com/ip-products/processors/cortex-a/cortex-a34|title=Cortex-A34|last=Ltd|first=Arm|website=ARM Developer|language=en|access-date=2019-10-10}}</ref>
![[Arm Cortex-A34|Cortex-A34 (64-bit)]]<ref>{{Cite web|url=https://developer.arm.com/ip-products/processors/cortex-a/cortex-a34|title=Cortex-A34|last=Ltd|first=Arm|website=ARM Developer|language=en|access-date=2019-10-10}}</ref>
| 2019
| 2019
|ARMv8.0-A<br /><small>(only [[64-bit computing|64-bit]])</small>|| 2-wide || 8 || {{No}} || 0 || {{dunno}} || {{Yes|LITTLE}} || {{dunno}} || {{dunno}}
|ARMv8.0-A<br /><small>(only [[64-bit computing|64-bit]])</small>|| 2-wide || 8 || {{No}} || 0 || {{dunno}} || {{Yes|LITTLE}} || {{dunno}} || {{dunno}}
| {{dunno}} || {{No}} || {{No}} ||8–64 + 8–64 || 0–1&nbsp;MiB || {{No}} || 1–4+ || {{dunno}} || 0xD02
| {{dunno}} || {{No}} || {{No}} ||8–64 + 8–64 || 0–1&nbsp;MiB || {{No}} || 1–4+ || {{dunno}} || {{dunno}} || 0xD02
|-
|-
! [[ARM Cortex-A35|Cortex-A35]]<ref name="cortex-a35">{{cite web|title=Cortex-A35 Processor|url=https://www.arm.com/products/processors/cortex-a/cortex-a35-processor.php|website=ARM|publisher=ARM Ltd}}</ref>
! [[ARM Cortex-A35|Cortex-A35]]<ref name="cortex-a35">{{cite web|title=Cortex-A35 Processor|url=https://www.arm.com/products/processors/cortex-a/cortex-a35-processor.php|website=ARM|publisher=ARM Ltd}}</ref>
| 2017
| 2017
| ARMv8.0-A || 2-wide<ref>{{cite web|url=http://anandtech.com/show/9769/arm-announces-cortex-a35|title=ARM Announces New Cortex-A35 CPU – Ultra-High Efficiency For Wearables & More|first=Andrei|last=Frumusanu}}</ref>|| 8 || {{No}} || 0 || {{Yes}} || {{Yes|LITTLE}} || {{dunno}} || {{dunno}}
| ARMv8.0-A || 2-wide<ref>{{cite web|url=http://anandtech.com/show/9769/arm-announces-cortex-a35|title=ARM Announces New Cortex-A35 CPU – Ultra-High Efficiency For Wearables & More|first=Andrei|last=Frumusanu}}</ref>|| 8 || {{No}} || 0 || {{Yes}} || {{Yes|LITTLE}} || {{dunno}} || {{dunno}}
| 28&nbsp;/&nbsp;16&nbsp;/<br />14&nbsp;/&nbsp;10 || {{No}} || {{No}} || 8–64 + 8–64 || 0 / 128&nbsp;KiB–1&nbsp;MiB || {{No}} || 1–4+ || 1.78 || 0xD04
| 28&nbsp;/&nbsp;16&nbsp;/<br />14&nbsp;/&nbsp;10 || {{No}} || {{No}} || 8–64 + 8–64 || 0 / 128&nbsp;KiB–1&nbsp;MiB || {{No}} || 1–4+ || 1.78 || {{dunno}} || 0xD04
|-
|-
! [[ARM Cortex-A53|Cortex-A53]]<ref name="a53-page">{{cite web|title=Cortex-A53 Processor|url=http://www.arm.com/products/processors/cortex-a/cortex-a53-processor.php|website=ARM|publisher=ARM Ltd}}</ref>
! [[ARM Cortex-A53|Cortex-A53]]<ref name="a53-page">{{cite web|title=Cortex-A53 Processor|url=http://www.arm.com/products/processors/cortex-a/cortex-a53-processor.php|website=ARM|publisher=ARM Ltd}}</ref>
| 2014
| 2014
| ARMv8.0-A || 2-wide || 8 || {{No}} || 0 || rowspan="2" | Conditional+<br />Indirect branch<br />prediction || {{Yes|big/LITTLE}} || 2 || {{dunno}}
| ARMv8.0-A || 2-wide || 8 || {{No}} || 0 || rowspan="2" | Conditional+<br />Indirect branch<br />prediction || {{Yes|big/LITTLE}} || 2 || {{dunno}}
| 28&nbsp;/&nbsp;20&nbsp;/<br />16&nbsp;/&nbsp;14&nbsp;/&nbsp;10 || {{No}} || {{No}} || 8–64 + 8–64 || 128&nbsp;KiB–2&nbsp;MiB || {{No}} || 1–4+ || 2.24 || 0xD03
| 28&nbsp;/&nbsp;20&nbsp;/<br />16&nbsp;/&nbsp;14&nbsp;/&nbsp;10 || {{No}} || {{No}} || 8–64 + 8–64 || 128&nbsp;KiB–2&nbsp;MiB || {{No}} || 1–4+ || 2.24 || {{dunno}} || 0xD03
|-
|-
! [[ARM Cortex-A55|Cortex-A55]]<ref name="a55-page">{{cite news|last1=Matt|first1=Humrick |title=Exploring DynamIQ and ARM's New CPUs: Cortex-A75, Cortex-A55|url=http://www.anandtech.com/show/11441/dynamiq-and-arms-new-cpus-cortex-a75-a55|access-date=29 May 2017|publisher=Anandtech.com|date=29 May 2017}}</ref>
! [[ARM Cortex-A55|Cortex-A55]]<ref name="a55-page">{{cite news|last1=Matt|first1=Humrick |title=Exploring DynamIQ and ARM's New CPUs: Cortex-A75, Cortex-A55|url=http://www.anandtech.com/show/11441/dynamiq-and-arms-new-cpus-cortex-a75-a55|access-date=29 May 2017|publisher=Anandtech.com|date=29 May 2017}}</ref>
Line 201: Line 202:
| ARMv8.2-A || 2-wide || 8 || {{No}} || 0 || {{Yes|big/LITTLE}} || 2 || {{dunno}}
| ARMv8.2-A || 2-wide || 8 || {{No}} || 0 || {{Yes|big/LITTLE}} || 2 || {{dunno}}
| 28&nbsp;/&nbsp;20&nbsp;/<br />16&nbsp;/&nbsp;14&nbsp;/&nbsp;12&nbsp;/&nbsp;10&nbsp;/&nbsp;5<ref name="a55-5nm">{{cite web|title=Qualcomm Snapdragon 888 5G Mobile Platform |url=https://www.qualcomm.com/products/snapdragon-888-5g-mobile-platform|access-date=6 January 2021}}</ref>
| 28&nbsp;/&nbsp;20&nbsp;/<br />16&nbsp;/&nbsp;14&nbsp;/&nbsp;12&nbsp;/&nbsp;10&nbsp;/&nbsp;5<ref name="a55-5nm">{{cite web|title=Qualcomm Snapdragon 888 5G Mobile Platform |url=https://www.qualcomm.com/products/snapdragon-888-5g-mobile-platform|access-date=6 January 2021}}</ref>
| {{No}} || {{No}} || 16–64 + 16–64 || 0–256&nbsp;KiB/core || {{Yes|0–4&nbsp;MiB}} || 1–8+ || 2.65<ref name="a55-perf">Based on 18% perf. increment over Cortex-A53 {{cite web|title=Arm Cortex-A55: Efficient performance from edge to cloud|url=https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/arm-cortex-a55-efficient-performance-from-edge-to-cloud|website=ARM|publisher=ARM Ltd}}</ref>
| {{No}} || {{No}} || 16–64 + 16–64 || 0–256&nbsp;KiB/core || {{Yes|0–4&nbsp;MiB}} || 1–8+ || 2.65<ref name="a55-perf">Based on 18% perf. increment over Cortex-A53 {{cite web|title=Arm Cortex-A55: Efficient performance from edge to cloud|url=https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/arm-cortex-a55-efficient-performance-from-edge-to-cloud|website=ARM|publisher=ARM Ltd}}</ref> || {{dunno}}
|0xD05
|0xD05
|-
|-
Line 207: Line 208:
| 2013
| 2013
| ARMv8.0-A || 3-wide || 15 || {{Yes}}<br /> 3-wide dispatch || {{dunno}} || {{dunno}} || {{Yes|big}} || 8 || {{dunno}}
| ARMv8.0-A || 3-wide || 15 || {{Yes}}<br /> 3-wide dispatch || {{dunno}} || {{dunno}} || {{Yes|big}} || 8 || {{dunno}}
| 28&nbsp;/&nbsp;20&nbsp;/<br />16<ref name="TSMC-HiSilicon-16nm" />&nbsp;/&nbsp;14 || {{No}} || {{No}} || 48 + 32 || 0.5–2&nbsp;MiB || {{No}} || 1–4+ || 4.8 ||0xD07
| 28&nbsp;/&nbsp;20&nbsp;/<br />16<ref name="TSMC-HiSilicon-16nm" />&nbsp;/&nbsp;14 || {{No}} || {{No}} || 48 + 32 || 0.5–2&nbsp;MiB || {{No}} || 1–4+ || 4.8 || {{dunno}} ||0xD07
|-
|-
! [[ARM Cortex-A65|Cortex-A65]]<ref name="arm-cortexa65">{{cite web|title=Cortex-A65 – Arm Developer|url=https://developer.arm.com/ip-products/processors/cortex-a/cortex-a65|website=ARM Ltd.|access-date=14 July 2020}}</ref>
! [[ARM Cortex-A65|Cortex-A65]]<ref name="arm-cortexa65">{{cite web|title=Cortex-A65 – Arm Developer|url=https://developer.arm.com/ip-products/processors/cortex-a/cortex-a65|website=ARM Ltd.|access-date=14 July 2020}}</ref>
Line 215: Line 216:
| || {{dunno}}
| || {{dunno}}
|No
|No
|No|| {{dunno}} || {{dunno}} || {{dunno}} || {{dunno}} || {{dunno}}
|No|| {{dunno}} || {{dunno}} || {{dunno}} || {{dunno}} || {{dunno}} || {{dunno}}
|0xD06
|0xD06
|-
|-
Line 224: Line 225:
| || {{dunno}}
| || {{dunno}}
|SMT2
|SMT2
|No|| 16–64 + 16–64 || 64–256&nbsp;KiB || 0–4&nbsp;MB || 1–8 || {{dunno}}
|No|| 16–64 + 16–64 || 64–256&nbsp;KiB || 0–4&nbsp;MB || 1–8 || {{dunno}} || {{dunno}}
|0xD43
|0xD43
|-
|-
Line 234: Line 235:
| || 28&nbsp;/&nbsp;16
| || 28&nbsp;/&nbsp;16
|No
|No
|No|| 48 + 32 || 0.5–4&nbsp;MiB || No || 1–4+ ||6.3–7,3<ref name="users.nik.uni-obuda.hu" />
|No|| 48 + 32 || 0.5–4&nbsp;MiB || No || 1–4+ ||6.3–7.3<ref name="users.nik.uni-obuda.hu" /> || {{dunno}}
|0xD08
|0xD08
|-
|-
Line 244: Line 245:
| || 28&nbsp;/&nbsp;16&nbsp;/&nbsp;10
| || 28&nbsp;/&nbsp;16&nbsp;/&nbsp;10
|No
|No
|No|| 64 + 32/64 || 1–8&nbsp;MiB || No || 1–4+ || 7.4–8.5<ref name="users.nik.uni-obuda.hu" />
|No|| 64 + 32/64 || 1–8&nbsp;MiB || No || 1–4+ || 7.4–8.5<ref name="users.nik.uni-obuda.hu" /> || {{dunno}}
|0xD09
|0xD09
|-
|-
Line 266: Line 267:
|1–8+
|1–8+
|8.2–9.5<ref name="users.nik.uni-obuda.hu">{{Cite web |date=November 2018 |title=ARM’s processor lines |url=http://users.nik.uni-obuda.hu/sima/letoltes/Processor_families_Knowledge_Base_2019/ARM_processors_lecture_2018_12_02.pdf |access-date=October 24, 2023 |website=users.nik.uni-obuda.hu}}</ref>
|8.2–9.5<ref name="users.nik.uni-obuda.hu">{{Cite web |date=November 2018 |title=ARM’s processor lines |url=http://users.nik.uni-obuda.hu/sima/letoltes/Processor_families_Knowledge_Base_2019/ARM_processors_lecture_2018_12_02.pdf |access-date=October 24, 2023 |website=users.nik.uni-obuda.hu}}</ref>
|{{dunno}}
|0xD0A
|0xD0A
|-
|-
Line 284: Line 286:
|1–4
|1–4
|10.7–12.4<ref name="users.nik.uni-obuda.hu"/>
|10.7–12.4<ref name="users.nik.uni-obuda.hu"/>
|{{dunno}}
|0xD0B
|0xD0B
|-
|-
Line 300: Line 303:
|No
|No
|No
|No
|{{dunno}}
|{{dunno}}
|{{dunno}}
|{{dunno}}
|{{dunno}}
Line 324: Line 328:
|1–4
|1–4
|13–16<ref>According to ARM, the Cortex-A77 has a 20% IPC single-thread performance improvement over its predecessor in Geekbench 4, 23% in SPECint2006, 35% in SPECfp2006, 20% in SPECint2017, and 25% in SPECfp2017</ref>
|13–16<ref>According to ARM, the Cortex-A77 has a 20% IPC single-thread performance improvement over its predecessor in Geekbench 4, 23% in SPECint2006, 35% in SPECfp2006, 20% in SPECint2017, and 25% in SPECfp2017</ref>
|{{dunno}}
|0xD0D
|0xD0D
|-
|-
Line 344: Line 349:
|1–4&nbsp;MiB
|1–4&nbsp;MiB
|1–4
|1–4
|{{dunno}}
|{{dunno}}
|{{dunno}}
|0xD41
|0xD41
Line 365: Line 371:
|up to 8 MiB<ref name=":2" />
|up to 8 MiB<ref name=":2" />
|custom<ref name=":2" />
|custom<ref name=":2" />
|{{dunno}}
|{{dunno}}
|{{dunno}}
|0xD44
|0xD44
Line 375: Line 382:
| || 28<ref name="Chipworks-A7" />
| || 28<ref name="Chipworks-A7" />
|No
|No
|No|| 64 + 64<ref name="AnandTech-Cyclone" />|| 1&nbsp;MiB<ref name="AnandTech-Cyclone" />|| 4&nbsp;MiB<ref name="AnandTech-Cyclone" />|| 2<ref name="AnandTech-iPhone5s-A7" />|| 1.3–1.4&nbsp;GHz
|No|| 64 + 64<ref name="AnandTech-Cyclone" />|| 1&nbsp;MiB<ref name="AnandTech-Cyclone" />|| 4&nbsp;MiB<ref name="AnandTech-Cyclone" />|| 2<ref name="AnandTech-iPhone5s-A7" /> || {{dunno}} || 1.3–1.4&nbsp;GHz
|
|
|-
|-
Line 384: Line 391:
| || 20
| || 20
|No
|No
|No|| 64 + 64<ref name="AnandTech-Cyclone" />|| 1&nbsp;MiB<ref name="AnandTech-Twister" />|| 4&nbsp;MiB<ref name="AnandTech-Cyclone" />|| 2, 3 (A8X) || 1.1–1.5&nbsp;GHz
|No|| 64 + 64<ref name="AnandTech-Cyclone" />|| 1&nbsp;MiB<ref name="AnandTech-Twister" />|| 4&nbsp;MiB<ref name="AnandTech-Cyclone" />|| 2, 3 (A8X) || {{dunno}} || 1.1–1.5&nbsp;GHz
|
|
|-
|-
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| || 16&nbsp;/&nbsp;14
| || 16&nbsp;/&nbsp;14
|No
|No
|No|| 64 + 64<ref name="AnandTech-Twister" />|| 3&nbsp;MiB<ref name="AnandTech-Twister" />|| 4&nbsp;MiB<ref name="AnandTech-Twister" /><br />No ([[Apple A9X|A9X]])|| 2 || 1.85–2.26&nbsp;GHz
|No|| 64 + 64<ref name="AnandTech-Twister" />|| 3&nbsp;MiB<ref name="AnandTech-Twister" />|| 4&nbsp;MiB<ref name="AnandTech-Twister" /><br />No ([[Apple A9X|A9X]])|| 2 || {{dunno}} || 1.85–2.26&nbsp;GHz
|
|
|-
|-
Line 414: Line 421:
|4 MiB<ref name=":0" /> ([[Apple A10|A10]])<br />No ([[Apple A10X|A10X]])
|4 MiB<ref name=":0" /> ([[Apple A10|A10]])<br />No ([[Apple A10X|A10X]])
|2x [[Apple A10 Fusion|Hurricane]] (A10) <br /> 3x [[Apple A10 Fusion|Hurricane]] (A10X)
|2x [[Apple A10 Fusion|Hurricane]] (A10) <br /> 3x [[Apple A10 Fusion|Hurricane]] (A10X)
|{{dunno}}
|2.34–2.36&nbsp;GHz
|2.34–2.36&nbsp;GHz
|
|
Line 434: Line 442:
|4 MiB<ref name=":0" /> ([[Apple A10|A10]])<br />No ([[Apple A10X|A10X]])
|4 MiB<ref name=":0" /> ([[Apple A10|A10]])<br />No ([[Apple A10X|A10X]])
|2x [[Apple A10 Fusion|Zephyr]] (A10) <br /> 3x [[Apple A10 Fusion|Zephyr]] (A10X)
|2x [[Apple A10 Fusion|Zephyr]] (A10) <br /> 3x [[Apple A10 Fusion|Zephyr]] (A10X)
|{{dunno}}
|1.09–1.3&nbsp;GHz
|1.09–1.3&nbsp;GHz
|
|
Line 455: Line 464:
|No
|No
|2x [[Apple A11|Monsoon]]
|2x [[Apple A11|Monsoon]]
|{{dunno}}
|2.39&nbsp;GHz
|2.39&nbsp;GHz
|
|
Line 475: Line 485:
|No
|No
|4× [[Apple A11|Mistral]]
|4× [[Apple A11|Mistral]]
|{{dunno}}
|1.19&nbsp;GHz
|1.19&nbsp;GHz
|
|
Line 496: Line 507:
|No
|No
|2x [[Apple A12|Vortex]] (A12) <br /> 4x [[Apple A12|Vortex]] (A12X/A12Z)
|2x [[Apple A12|Vortex]] (A12) <br /> 4x [[Apple A12|Vortex]] (A12X/A12Z)
|{{dunno}}
|2.49&nbsp;GHz
|2.49&nbsp;GHz
|
|
Line 516: Line 528:
|No
|No
|4x [[Apple A12|Tempest]]
|4x [[Apple A12|Tempest]]
|{{dunno}}
|1.59&nbsp;GHz
|1.59&nbsp;GHz
|
|
Line 537: Line 550:
|No
|No
|2x [[Apple A13|Lightning]]
|2x [[Apple A13|Lightning]]
|{{dunno}}
|2.65&nbsp;GHz
|2.65&nbsp;GHz
|
|
Line 557: Line 571:
|No
|No
|4x [[Apple A13|Thunder]]
|4x [[Apple A13|Thunder]]
|{{dunno}}
|1.8&nbsp;GHz
|1.8&nbsp;GHz
|
|
Line 581: Line 596:
8x [[Apple A14|Firestorm]] (M1 Max)<br />
8x [[Apple A14|Firestorm]] (M1 Max)<br />
16x Firestorm (M1 Ultra)
16x Firestorm (M1 Ultra)
|{{dunno}}
|3.0–3.23&nbsp;GHz
|3.0–3.23&nbsp;GHz
|
|
Line 601: Line 617:
|No
|No
|4x [[Apple A14|Icestorm]] (A14/M1) <br /> 2x [[Apple A14|Icestorm]] (M1 Pro/Max) <br /> 4x Icestorm (M1 Ultra)
|4x [[Apple A14|Icestorm]] (A14/M1) <br /> 2x [[Apple A14|Icestorm]] (M1 Pro/Max) <br /> 4x Icestorm (M1 Ultra)
|{{dunno}}
|1.82–2.06&nbsp;GHz
|1.82–2.06&nbsp;GHz
|
|
Line 623: Line 640:
|2x [[Apple A15|Avalanche]] (A15) <br /> 4x [[Apple A15|Avalanche]] (M2) <br /> 6x or 8x [[Apple A15|Avalanche]] (M2 Pro)<br />
|2x [[Apple A15|Avalanche]] (A15) <br /> 4x [[Apple A15|Avalanche]] (M2) <br /> 6x or 8x [[Apple A15|Avalanche]] (M2 Pro)<br />
8x [[Apple A15|Avalanche]] (M2 Max)<br /> 16x [[Apple A15|Avalanche]] (M2 Ultra)
8x [[Apple A15|Avalanche]] (M2 Max)<br /> 16x [[Apple A15|Avalanche]] (M2 Ultra)
|{{dunno}}
|2.93–3.49&nbsp;GHz
|2.93–3.49&nbsp;GHz
|
|
Line 643: Line 661:
|No
|No
|4x [[Apple A15|Blizzard]]
|4x [[Apple A15|Blizzard]]
|{{dunno}}
|2.02–2.42&nbsp;GHz
|2.02–2.42&nbsp;GHz
|
|
Line 664: Line 683:
|No
|No
|2x [[Apple A16|Everest]]
|2x [[Apple A16|Everest]]
|{{dunno}}
|3.46&nbsp;GHz
|3.46&nbsp;GHz
|
|
Line 684: Line 704:
|No
|No
|4x [[Apple A16|Sawtooth]]
|4x [[Apple A16|Sawtooth]]
|{{dunno}}
|2.02&nbsp;GHz
|2.02&nbsp;GHz
|
|
Line 706: Line 727:
| No
| No
| 2
| 2
|{{dunno}}
| {{dunno}}
| {{dunno}}
|
|
Line 727: Line 749:
| No
| No
| 2|| {{dunno}}
| 2|| {{dunno}}
|{{dunno}}
|
|
|-
|-
Line 738: Line 761:
| Direct+<br />Indirect branch<br />prediction
| Direct+<br />Indirect branch<br />prediction
|
|
| {{dunno}}
| {{dunno}}
|
|
| 12
| 12
Line 747: Line 770:
| (4&nbsp;MiB @ 8 cores)
| (4&nbsp;MiB @ 8 cores)
| 2 (+ 8)
| 2 (+ 8)
| {{dunno}}
| {{dunno}}
| {{dunno}}
|
|
Line 757: Line 781:
| || 28
| || 28
|No
|No
|No|| 78 + 32<ref name="electronic-design" /><ref name="Cavium" />|| 16&nbsp;MiB<ref name="electronic-design" /><ref name="Cavium" />|| No || 8–16, 24–48 || {{dunno}}
|No|| 78 + 32<ref name="electronic-design" /><ref name="Cavium" />|| 16&nbsp;MiB<ref name="electronic-design" /><ref name="Cavium" />|| No || 8–16, 24–48 || {{dunno}} || {{dunno}}
|
|
|-
|-
Line 766: Line 790:
| || 16<ref name="Vulcan-Announce" />
| || 16<ref name="Vulcan-Announce" />
|SMT4
|SMT4
|No|| 32 + 32<br />(data 8-way) || 256&nbsp;KiB<br />per core<ref name="tx2_bench">{{cite news|last1=Kennedy|first1=Patrick|title=Cavium ThunderX2 Review and Benchmarks a Real Arm Server Option|url=https://www.servethehome.com/cavium-thunderx2-review-benchmarks-real-arm-server-option/|access-date=10 May 2018|publisher=Serve the Home|date=9 May 2018}}</ref>|| 1&nbsp;MiB<br />per core<ref name="tx2_bench" />|| 16–32<ref name="tx2_bench" />|| {{dunno}}
|No|| 32 + 32<br />(data 8-way) || 256&nbsp;KiB<br />per core<ref name="tx2_bench">{{cite news|last1=Kennedy|first1=Patrick|title=Cavium ThunderX2 Review and Benchmarks a Real Arm Server Option|url=https://www.servethehome.com/cavium-thunderx2-review-benchmarks-real-arm-server-option/|access-date=10 May 2018|publisher=Serve the Home|date=9 May 2018}}</ref>|| 1&nbsp;MiB<br />per core<ref name="tx2_bench" />|| 16–32<ref name="tx2_bench" />|| {{dunno}} || {{dunno}}
|
|
|-
|-
Line 776: Line 800:
| || 7<ref name="thunderX3" />
| || 7<ref name="thunderX3" />
|SMT4<ref name="thunderX3" />
|SMT4<ref name="thunderX3" />
|{{dunno}} || 64 + 32 || 512&nbsp;KiB<br />per core || 90&nbsp;MiB || 60 || {{dunno}}
|{{dunno}} || 64 + 32 || 512&nbsp;KiB<br />per core || 90&nbsp;MiB || 60 || {{dunno}} || {{dunno}}
|
|
|-
|-
Line 786: Line 810:
| || 40&nbsp;/&nbsp;28
| || 40&nbsp;/&nbsp;28
|No
|No
|No|| rowspan="3" | 32 + 32 (per core;<br />write-through<br />w/parity)<ref>{{cite news |url=http://anandtech.com/show/8588/armv8-goes-embedded-with-applied-micros-helix-socs |title=ARMv8 Goes Embedded with Applied Micro's HeliX SoCs |author=Ganesh T S |publisher=AnandTech|date=3 October 2014 |access-date=9 October 2014}}</ref>|| rowspan="3" | 256&nbsp;KiB shared<br />per core pair (with ECC) || 1&nbsp;MiB/core || 2, 4, 8 || {{dunno}}
|No|| rowspan="3" | 32 + 32 (per core;<br />write-through<br />w/parity)<ref>{{cite news |url=http://anandtech.com/show/8588/armv8-goes-embedded-with-applied-micros-helix-socs |title=ARMv8 Goes Embedded with Applied Micro's HeliX SoCs |author=Ganesh T S |publisher=AnandTech|date=3 October 2014 |access-date=9 October 2014}}</ref>|| rowspan="3" | 256&nbsp;KiB shared<br />per core pair (with ECC) || 1&nbsp;MiB/core || 2, 4, 8 || {{dunno}} || {{dunno}}
|
|
|-
|-
Line 795: Line 819:
| || 40<ref>{{cite news |url=http://www.enterprisetech.com/2014/08/12/applied-micro-plots-x-gene-arm-server-future/ |title=Applied Micro Plots Out X-Gene ARM Server Future |first=Timothy Prickett |last=Morgan |publisher=Enterprisetech |date=12 August 2014 |access-date=9 October 2014}}</ref>
| || 40<ref>{{cite news |url=http://www.enterprisetech.com/2014/08/12/applied-micro-plots-x-gene-arm-server-future/ |title=Applied Micro Plots Out X-Gene ARM Server Future |first=Timothy Prickett |last=Morgan |publisher=Enterprisetech |date=12 August 2014 |access-date=9 October 2014}}</ref>
|No
|No
|No|| 8&nbsp;MiB || 8 || 4.2
|No|| 8&nbsp;MiB || 8 || 4.2 || {{dunno}}
|
|
|-
|-
Line 804: Line 828:
| || 28<ref name="AT_XG3">{{cite news|last1=De Gelas|first1=Johan|title=AppliedMicro's X-Gene 3 SoC Begins Sampling|url=http://www.anandtech.com/show/11189/appliedmicro-x-gene-3-soc-starts-sampling|access-date=15 March 2017|publisher=Anandtech|date=15 March 2017}}</ref>
| || 28<ref name="AT_XG3">{{cite news|last1=De Gelas|first1=Johan|title=AppliedMicro's X-Gene 3 SoC Begins Sampling|url=http://www.anandtech.com/show/11189/appliedmicro-x-gene-3-soc-starts-sampling|access-date=15 March 2017|publisher=Anandtech|date=15 March 2017}}</ref>
|No
|No
|No|| 8&nbsp;MiB || 8 || 4.2
|No|| 8&nbsp;MiB || 8 || 4.2 || {{dunno}}
|
|
|-
|-
Line 813: Line 837:
| || 16
| || 16
|No
|No
|No|| {{dunno}} || {{dunno}} || 32&nbsp;MiB || 32 || {{dunno}}
|No|| {{dunno}} || {{dunno}} || 32&nbsp;MiB || 32 || {{dunno}} || {{dunno}}
|
|
|-
|-
Line 823: Line 847:
| || 14<ref name="Kryo-ann">{{cite web|url=https://www.qualcomm.com/news/snapdragon/2015/09/02/snapdragon-820-and-kryo-cpu-heterogeneous-computing-and-role-custom |title=Snapdragon 820 and Kryo CPU: heterogeneous computing and the role of custom compute |publisher=Qualcomm |date=2 September 2015 |access-date=6 September 2015}}</ref>
| || 14<ref name="Kryo-ann">{{cite web|url=https://www.qualcomm.com/news/snapdragon/2015/09/02/snapdragon-820-and-kryo-cpu-heterogeneous-computing-and-role-custom |title=Snapdragon 820 and Kryo CPU: heterogeneous computing and the role of custom compute |publisher=Qualcomm |date=2 September 2015 |access-date=6 September 2015}}</ref>
|No
|No
|No|| 32+24<ref>{{cite web|url=http://www.anandtech.com/show/9837/snapdragon-820-preview/|title=The Qualcomm Snapdragon 820 Performance Preview: Meet Kryo|first=Ryan Smith, Andrei|last=Frumusanu}}</ref>|| 0.5–1 MiB || || 2+2 || 6.3
|No|| 32+24<ref>{{cite web|url=http://www.anandtech.com/show/9837/snapdragon-820-preview/|title=The Qualcomm Snapdragon 820 Performance Preview: Meet Kryo|first=Ryan Smith, Andrei|last=Frumusanu}}</ref>|| 0.5–1 MiB || || 2+2 || 6.3 || {{dunno}}
|
|
|-
|-
Line 840: Line 864:
|512&nbsp;KiB/Gold Core
|512&nbsp;KiB/Gold Core
| rowspan="2" |No
| rowspan="2" |No
|4||1.8–2.45&nbsp;GHz
|4||{{dunno}}||1.8–2.45&nbsp;GHz
|
|
|-
|-
Line 852: Line 876:
|8–64? + 8–64?
|8–64? + 8–64?
|256&nbsp;KiB/Silver Core
|256&nbsp;KiB/Silver Core
|4||1.8–1.9&nbsp;GHz
|4||{{dunno}}||1.8–1.9&nbsp;GHz
|
|
|-
|-
Line 869: Line 893:
|256&nbsp;KiB/Gold Core
|256&nbsp;KiB/Gold Core
| rowspan="2" |2 MiB
| rowspan="2" |2 MiB
|2, 4||2.0–2.95&nbsp;GHz
|2, 4||{{dunno}}||2.0–2.95&nbsp;GHz
|
|
|-
|-
Line 881: Line 905:
|16–64? + 16–64?
|16–64? + 16–64?
|128&nbsp;KiB/Silver
|128&nbsp;KiB/Silver
|4, 6||1.7–1.8&nbsp;GHz
|4, 6||{{dunno}}||1.7–1.8&nbsp;GHz
|
|
|-
|-
Line 899: Line 923:
256&nbsp;KiB/Gold
256&nbsp;KiB/Gold
| rowspan="2" |2&nbsp;MiB
| rowspan="2" |2&nbsp;MiB
|2, 1+1, 4, 1+3|| 2.0–2.96&nbsp;GHz
|2, 1+1, 4, 1+3 || {{dunno}} || 2.0–2.96&nbsp;GHz
|
|
|-
|-
Line 912: Line 936:
|128&nbsp;KiB/Silver
|128&nbsp;KiB/Silver
|4, 6
|4, 6
|{{dunno}}
|1.7–1.8&nbsp;GHz
|1.7–1.8&nbsp;GHz
|
|
Line 931: Line 956:
| rowspan="2" |3&nbsp;MiB
| rowspan="2" |3&nbsp;MiB
|2, 1+3
|2, 1+3
|{{dunno}}
|2.0–3.2&nbsp;GHz
|2.0–3.2&nbsp;GHz
|
|
Line 945: Line 971:
|128&nbsp;KiB/Silver
|128&nbsp;KiB/Silver
|4, 6
|4, 6
|{{dunno}}
|1.7–1.8&nbsp;GHz
|1.7–1.8&nbsp;GHz
|
|
Line 965: Line 992:
| rowspan="2" |4 MiB
| rowspan="2" |4 MiB
|2, 1+3
|2, 1+3
|{{dunno}}
|2.2–3.0&nbsp;GHz
|2.2–3.0&nbsp;GHz
|
|
Line 979: Line 1,007:
|128&nbsp;KiB/Silver
|128&nbsp;KiB/Silver
|4, 6
|4, 6
|{{dunno}}
|1.7–1.8&nbsp;GHz
|1.7–1.8&nbsp;GHz
|
|
Line 989: Line 1,018:
| || 10
| || 10
|No
|No
|24 KiB|| 88<ref name="Falkor" /> + 32 || 500KiB || 1.25MiB || 40–48 || {{dunno}}
|24 KiB|| 88<ref name="Falkor" /> + 32 || 500KiB || 1.25MiB || 40–48 || {{dunno}} || {{dunno}}
|
|
|-
|-
Line 1,000: Line 1,029:
| || 14
| || 14
|No
|No
|No|| 64 + 32 || 2 MiB<ref>{{cite web|url=https://www.theregister.co.uk/2016/08/22/samsung_m1_core/|title='Neural network' spotted deep inside Samsung's Galaxy S7 silicon brain|website=[[The Register]] }}</ref>|| No || 4 || 2.6&nbsp;GHz
|No|| 64 + 32 || 2 MiB<ref>{{cite web|url=https://www.theregister.co.uk/2016/08/22/samsung_m1_core/|title='Neural network' spotted deep inside Samsung's Galaxy S7 silicon brain|website=[[The Register]] }}</ref>|| No || 4 || {{dunno}} || 2.6&nbsp;GHz
|
|
|-
|-
Line 1,019: Line 1,048:
|No
|No
|4
|4
|{{dunno}}
|2.3&nbsp;GHz
|2.3&nbsp;GHz
|
|
Line 1,028: Line 1,058:
| || 10
| || 10
|No
|No
|No|| 64 + 64 || 512 KiB per core || 4096KB || 4 || 2.7&nbsp;GHz
|No|| 64 + 64 || 512 KiB per core || 4096KB || 4 || {{dunno}} || 2.7&nbsp;GHz
|
|
|-
|-
Line 1,046: Line 1,076:
|3072KB
|3072KB
|2
|2
|{{dunno}}
|2.73&nbsp;GHz
|2.73&nbsp;GHz
|
|
Line 1,064: Line 1,095:
|3072KB
|3072KB
|2
|2
|{{dunno}}
|2.73&nbsp;GHz
|2.73&nbsp;GHz
|
|
Line 1,083: Line 1,115:
|No
|No
|48+4
|48+4
|{{dunno}}
|1.9&nbsp;GHz+; 15GF/W+.
|1.9&nbsp;GHz+
|
|
|-
|-
Line 1,104: Line 1,137:
|512 KiB per core
|512 KiB per core
|1 MiB per core
|1 MiB per core
|{{dunno}}
|?
|{{dunno}}
|?
|{{dunno}}
|
|
|-
|-
Line 1,126: Line 1,160:
! L3 cache
! L3 cache
! Core<br />configu-<br />rations
! Core<br />configu-<br />rations
! Speed per core ([[Dhrystone#Results|DMIPS/<br />MHz]]{{refn|group=note|name=first|As [[Dhrystone]] (implied in "DMIPS") is a synthetic benchmark developed in 1980s, it is no longer representative of prevailing workloads{{snd}} use with caution.}})
![[Dhrystone#Results|DMIPS/<br />MHz]]
![[Clock rate]]
!ARM part number (in the main ID register)
!ARM part number (in the main ID register)
|-
|-

Revision as of 06:36, 9 November 2023

This is a comparison of ARM instruction set architecture application processor cores designed by ARM Holdings (ARM Cortex-A) and 3rd parties. It does not include ARM Cortex-R, ARM Cortex-M, or legacy ARM cores.

ARMv7-A

This is a table comparing 32-bit central processing units that implement the ARMv7-A (A means Application[1]) instruction set architecture and mandatory or optional extensions of it, the last AArch32.

Core Decode
width		 Execution
ports		 Pipeline
depth		 Out-of-order execution FPU Pipelined
VFP		 FPU
registers		 NEON
(SIMD)		 big.LITTLE
role		 Virtualization[2] Process
technology		 L0
cache		 L1
cache		 L2
cache		 Core
configurations		 Speed
per
core
(DMIPS
/ MHz)		 ARM part number
(in the main ID register)
ARM Cortex-A5 1 8 No VFPv4 (optional) 16 × 64-bit 64-bit wide (optional) No No 40/28 nm 4–64 KiB / core 1, 2, 4 1.57 0xC05
ARM Cortex-A7 2 5[3] 8 No VFPv4 Yes 16 × 64-bit 64-bit wide LITTLE Yes[4] 40/28 nm 8–64 KiB / core up to 1 MiB (optional) 1, 2, 4, 8 1.9 0xC07
ARM Cortex-A8 2 2[5] 13 No VFPv3 No 32 × 64-bit 64-bit wide No No 65/55/45 nm 32 KiB + 32 KiB 256 or 512 (typical) KiB 1 2.0 0xC08
ARM Cortex-A9 2 3[6] 8–11[7] Yes VFPv3 (optional) Yes (16 or 32) × 64-bit 64-bit wide (optional) Companion Core No[7] 65/45/40/32/28 nm 32 KiB + 32 KiB 1 MiB 1, 2, 4 2.5 0xC09
ARM Cortex-A12 2 11 Yes VFPv4 Yes 32 × 64-bit 128-bit wide No[8] Yes 28 nm 32–64 KiB + 32 KiB 256 KiB, to 8 MiB 1, 2, 4 3.0 0xC0D
ARM Cortex-A15 3 8[3] 15/17-25 Yes VFPv4 Yes 32 × 64-bit 128-bit wide big Yes[9] 32/28/20 nm 32 KiB + 32 KiB per core up to 4 MiB per cluster, up to 8 MiB per chip 2, 4, 8 (4×2) 3.5 to 4.01 0xC0F
ARM Cortex-A17 2[10] 11+ Yes VFPv4 Yes 32 × 64-bit 128-bit wide big Yes 28 nm 32 KiB + 32 KiB per core 256 KiB, up to 8 MiB up to 4 4.0 0xC0E
Qualcomm Scorpion 2 3[11] 10 Yes (FXU&LSU only)[12] VFPv3 Yes 128-bit wide No 65/45 nm 32 KiB + 32 KiB 256 KiB (single-core)
512 KiB (dual-core) 		1, 2 2.1 0x00F
Qualcomm Krait[13] 3 7 11 Yes VFPv4[14] Yes 128-bit wide No 28 nm 4 KiB + 4 KiB direct mapped 16 KiB + 16 KiB 4-way set associative 1 MiB 8-way set associative (dual-core) / 2 MiB (quad-core) 2, 4 3.3 (Krait 200)
3.39 (Krait 300)
3.39 (Krait 400)
3.51 (Krait 450) 		0x04D

0x06F
Swift 3 5 12 Yes VFPv4 Yes 32 × 64-bit 128-bit wide No 32 nm 32 KiB + 32 KiB 1 MiB 2 3.5 ?
Core Decode
width 		Execution
ports 		Pipeline
depth 		Out-of-order execution FPU Pipelined
VFP 		FPU
registers 		NEON
(SIMD) 		big.LITTLE
role 		Virtualization[2] Process
technology 		L0
cache 		L1
cache 		L2
cache 		Core
configurations 		Speed
per
core
(DMIPS
/ MHz) 		ARM part number
(in the main ID register)

ARMv8-A

This is a table of 64/32-bit central processing units that implement the ARMv8-A instruction set architecture and mandatory or optional extensions of it. Most chips support the 32-bit ARMv7-A for legacy applications. All chips of this type have a floating-point unit (FPU) that is better than the one in older ARMv7-A and NEON (SIMD) chips. Some of these chips have coprocessors also include cores from the older 32-bit architecture (ARMv7). Some of the chips are SoCs and can combine both ARM Cortex-A53 and ARM Cortex-A57, such as the Samsung Exynos 7 Octa.

Company Core Released Revision Decode Pipeline
depth 		Out-of-order
execution 		Branch
prediction 		big.LITTLE role Exec.
ports 		SIMD Fab
(in nm) 		Simult. MT L0 cache L1 cache
Instr + Data
(in KiB) 		L2 cache L3 cache Core
configu-
rations 		Speed per core (DMIPS/
MHz[note 1]) 		Clock rate ARM part number (in the main ID register)
Have it Entries
ARM Cortex-A32 (32-bit)[15] 2017 ARMv8.0-A
(only 32-bit)		 2-wide 8 No 0 ? LITTLE ? ? 28[16] No No 8–64 + 8–64 0–1 MiB No 1–4+ ? ? 0xD01
Cortex-A34 (64-bit)[17] 2019 ARMv8.0-A
(only 64-bit)		 2-wide 8 No 0 ? LITTLE ? ? ? No No 8–64 + 8–64 0–1 MiB No 1–4+ ? ? 0xD02
Cortex-A35[18] 2017 ARMv8.0-A 2-wide[19] 8 No 0 Yes LITTLE ? ? 28 / 16 /
14 / 10		 No No 8–64 + 8–64 0 / 128 KiB–1 MiB No 1–4+ 1.78 ? 0xD04
Cortex-A53[20] 2014 ARMv8.0-A 2-wide 8 No 0 Conditional+
Indirect branch
prediction		 big/LITTLE 2 ? 28 / 20 /
16 / 14 / 10		 No No 8–64 + 8–64 128 KiB–2 MiB No 1–4+ 2.24 ? 0xD03
Cortex-A55[21] 2017 ARMv8.2-A 2-wide 8 No 0 big/LITTLE 2 ? 28 / 20 /
16 / 14 / 12 / 10 / 5[22] 		No No 16–64 + 16–64 0–256 KiB/core 0–4 MiB 1–8+ 2.65[23] ? 0xD05
Cortex-A57[24] 2013 ARMv8.0-A 3-wide 15 Yes
3-wide dispatch		 ? ? big 8 ? 28 / 20 /
16[25] / 14		 No No 48 + 32 0.5–2 MiB No 1–4+ 4.8 ? 0xD07
Cortex-A65[26] 2019 ARMv8.2-A ? ? Yes Two-level ? 2 ? No No ? ? ? ? ? ? 0xD06
Cortex-A65AE[27] 2019 ARMv8.2-A ? ? Yes Two-level ? 2 ? SMT2 No 16–64 + 16–64 64–256 KiB 0–4 MB 1–8 ? ? 0xD43
Cortex-A72[28] 2015 ARMv8.0-A 3-wide 15 Yes
5-wide dispatch 		Two-level big 8 28 / 16 No No 48 + 32 0.5–4 MiB No 1–4+ 6.3–7.3[29] ? 0xD08
Cortex-A73[30] 2016 ARMv8.0-A 2-wide 11–12 Yes
4-wide dispatch 		Two-level big 7 28 / 16 / 10 No No 64 + 32/64 1–8 MiB No 1–4+ 7.4–8.5[29] ? 0xD09
Cortex-A75[21] 2017 ARMv8.2-A 3-wide 11–13 Yes
6-wide dispatch 		Two-level big 8? 2*128b 28 / 16 / 10 No No 64 + 64 256–512 KiB/core 0–4 MiB 1–8+ 8.2–9.5[29] ? 0xD0A
Cortex-A76[31] 2018 ARMv8.2-A 4-wide 11–13 Yes
8-wide dispatch 		128 Two-level big 8 2*128b 10 / 7 No No 64 + 64 256–512 KiB/core 1–4 MiB 1–4 10.7–12.4[29] ? 0xD0B
Cortex-A76AE[32] 2018 ARMv8.2-A ? ? Yes 128 Two-level big ? ? No No ? ? ? ? ? ? 0xD0E
Cortex-A77[33] 2019 ARMv8.2-A 4-wide 11–13 Yes
10-wide dispatch 		160 Two-level big 12 2*128b 7 No 1.5K entries 64 + 64 256–512 KiB/core 1–4 MiB 1–4 13–16[34] ? 0xD0D
Cortex-A78[35][36] 2020 ARMv8.2-A 4-wide Yes 160 Yes big 13 2*128b No 1.5K entries 32/64 + 32/64 256–512 KiB/core 1–4 MiB 1–4 ? ? 0xD41
Cortex-X1[37] 2020 ARMv8.2-A 5-wide[37] ? Yes 224 Yes big 15 4*128b No 3K entries 64 + 64 up to 1 MiB[37] up to 8 MiB[37] custom[37] ? ? 0xD44
Apple Cyclone[38] 2013 ARMv8.0-A 6-wide[39] 16[39] Yes[39] 192 Yes No 9[39] 28[40] No No 64 + 64[39] 1 MiB[39] 4 MiB[39] 2[41] ? 1.3–1.4 GHz
Typhoon 2014 ARMv8.0‑A 6-wide[42] 16[42] Yes[42] Yes No 9 20 No No 64 + 64[39] 1 MiB[42] 4 MiB[39] 2, 3 (A8X) ? 1.1–1.5 GHz
Twister 2015 ARMv8.0‑A 6-wide[42] 16[42] Yes[42] Yes No 9 16 / 14 No No 64 + 64[42] 3 MiB[42] 4 MiB[42]
No (A9X)		 2 ? 1.85–2.26 GHz
Hurricane 2016 ARMv8.0‑A 6-wide[43] 16 Yes "big" (In A10/A10X paired with "LITTLE" Zephyr
cores) 		9 3*128b 16 (A10)
10 (A10X) 		No No 64 + 64[44] 3 MiB[44] (A10)
8 MiB (A10X) 		4 MiB[44] (A10)
No (A10X) 		2x Hurricane (A10)
3x Hurricane (A10X) 		? 2.34–2.36 GHz
Zephyr ARMv8.0‑A 3-wide 12 Yes LITTLE 5 16 (A10)
10 (A10X) 		No No 32 + 32[45] 1 MiB 4 MiB[44] (A10)
No (A10X) 		2x Zephyr (A10)
3x Zephyr (A10X) 		? 1.09–1.3 GHz
Monsoon 2017 ARMv8.2‑A[46] 7-wide 16 Yes "big" (In Apple A11 paired with "LITTLE" Mistral
cores) 		11 3*128b 10 No No 64 + 64[45] 8 MiB No 2x Monsoon ? 2.39 GHz
Mistral ARMv8.2‑A[46] 3-wide 12 Yes LITTLE 5 10 No No 32 + 32[45] 1 MiB No 4× Mistral ? 1.19 GHz
Vortex 2018 ARMv8.3‑A[47] 7-wide 16 Yes "big" (In Apple A12/Apple A12X/Apple A12Z paired with "LITTLE" Tempest
cores) 		11 3*128b 7 No No 128 + 128[45] 8 MiB No 2x Vortex (A12)
4x Vortex (A12X/A12Z) 		? 2.49 GHz
Tempest ARMv8.3‑A[47] 3-wide 12 Yes LITTLE 5 7 No No 32 + 32[45] 2 MiB No 4x Tempest ? 1.59 GHz
Lightning 2019 ARMv8.4‑A[48] 8-wide 16 Yes 560 "big" (In Apple A13 paired with "LITTLE" Thunder
cores) 		11 3*128b 7 No No 128 + 128[49] 8 MiB No 2x Lightning ? 2.65 GHz
Thunder ARMv8.4‑A[48] 3-wide 12 Yes LITTLE 5 7 No No 96 + 48[50] 4 MiB No 4x Thunder ? 1.8 GHz
Firestorm 2020 ARMv8.4-A[51] 8-wide[52] Yes 630[53] "big" (In Apple A14 and Apple M1/M1 Pro/M1 Max/M1 Ultra paired with "LITTLE" Icestorm
cores) 		14 4*128b 5 No 192 + 128 8 MiB (A14)
12 MiB (M1)
24 MiB (M1 Pro/M1 Max)
48 MiB (M1 Ultra) 		No 2x Firestorm (A14)
4x Firestorm (M1)

6x or 8x Firestorm (M1 Pro)
8x Firestorm (M1 Max)
16x Firestorm (M1 Ultra)

? 3.0–3.23 GHz
Icestorm ARMv8.4-A[51] 4-wide Yes 110 LITTLE 7 2*128b 5 No 128 + 64 4 MiB
8 MiB (M1 Ultra) 		No 4x Icestorm (A14/M1)
2x Icestorm (M1 Pro/Max)
4x Icestorm (M1 Ultra) 		? 1.82–2.06 GHz
Avalanche 2021 ARMv8.6‑A[51] 8-wide Yes "big" (In Apple A15 and Apple M2/M2 Pro/M2 Max/M2 Ultra paired with "LITTLE" Blizzard
cores) 		14 4*128b 5 No 192 + 128 12 MiB (A15)
16 MiB (M2)
32 MiB (M2 Pro/M2 Max)
64 MiB (M2 Ultra) 		No 2x Avalanche (A15)
4x Avalanche (M2)
6x or 8x Avalanche (M2 Pro)

8x Avalanche (M2 Max)
16x Avalanche (M2 Ultra)

? 2.93–3.49 GHz
Blizzard ARMv8.6‑A[51] 4-wide Yes LITTLE 8 2*128b 5 No 128 + 64 4 MiB
8 MiB (M2 Ultra) 		No 4x Blizzard ? 2.02–2.42 GHz
Everest 2022 ARMv8.6‑A[51] 8-wide Yes "big" (In Apple A16 paired with "LITTLE" Sawtooth
cores) 		14 4*128b 5 No 192 + 128 16 MiB No 2x Everest ? 3.46 GHz
Sawtooth ARMv8.6‑A[51] 4-wide Yes LITTLE 8 2*128b 5 No 128 + 64 4 MiB No 4x Sawtooth ? 2.02 GHz
Nvidia Denver[54][55] 2014 ARMv8‑A 2-wide hardware
decoder, up to
7-wide variable-
length VLIW
micro-ops 		13 Not if the hardware
decoder is in use.
Can be provided
by dynamic software
translation into VLIW. 		Direct+
Indirect branch
prediction 		No 7 28 No No 128 + 64 2 MiB No 2 ? ?
Denver 2[56] 2016 ARMv8‑A ? 13 Not if the hardware
decoder is in use.
Can be provided
by dynamic software
translation into VLIW. 		Direct+
Indirect branch
prediction 		"Super" Nvidia's own implementation ? 16 No No 128 + 64 2 MiB No 2 ? ?
Carmel 2018 ARMv8.2‑A ? Direct+
Indirect branch
prediction 		? 12 No No 128 + 64 2 MiB (4 MiB @ 8 cores) 2 (+ 8) ? ?
Cavium ThunderX[57][58] 2014 ARMv8-A 2-wide 9[58] Yes[57] Two-level ? 28 No No 78 + 32[59][60] 16 MiB[59][60] No 8–16, 24–48 ? ?
ThunderX2
[61](ex. Broadcom Vulcan[62]) 		2018[63] ARMv8.1-A
[64]		 4-wide
"4 μops"[65][66]		 ? Yes[67] Multi-level ? ? 16[68] SMT4 No 32 + 32
(data 8-way)		 256 KiB
per core[69]		 1 MiB
per core[69]		 16–32[69] ? ?
Marvell ThunderX3 2020[70] ARMv8.3+[70] 8-wide ? Yes
4-wide dispatch 		Multi-level ? 7 7[70] SMT4[70] ? 64 + 32 512 KiB
per core		 90 MiB 60 ? ?
Applied

Micro

Helix 2014 ? ? ? ? ? ? ? 40 / 28 No No 32 + 32 (per core;
write-through
w/parity)[71]		 256 KiB shared
per core pair (with ECC)		 1 MiB/core 2, 4, 8 ? ?
X-Gene 2013 ? 4-wide 15 Yes ? ? ? 40[72] No No 8 MiB 8 4.2 ?
X-Gene 2 2015 ? 4-wide 15 Yes ? ? ? 28[73] No No 8 MiB 8 4.2 ?
X-Gene 3[73] 2017 ? ? ? ? ? ? ? 16 No No ? ? 32 MiB 32 ? ?
Qualcomm Kryo 2015 ARMv8-A ? ? Yes Two-level? "big" or "LITTLE"
Qualcomm's own similar implementation		 ? 14[74] No No 32+24[75] 0.5–1 MiB 2+2 6.3 ?
Kryo 200 2016 ARMv8-A 2-wide 11–12 Yes
7-wide dispatch 		Two-level big 7 14 / 11 / 10 / 6[76] No No 64 + 32/64? 512 KiB/Gold Core No 4 ? 1.8–2.45 GHz
2-wide 8 No 0 Conditional+
Indirect branch
prediction 		LITTLE 2 8–64? + 8–64? 256 KiB/Silver Core 4 ? 1.8–1.9 GHz
Kryo 300 2017 ARMv8.2-A 3-wide 11–13 Yes
8-wide dispatch 		Two-level big 8 10[76] No No 64+64[76] 256 KiB/Gold Core 2 MiB 2, 4 ? 2.0–2.95 GHz
2-wide 8 No 0 Conditional+
Indirect branch
prediction 		LITTLE 28 16–64? + 16–64? 128 KiB/Silver 4, 6 ? 1.7–1.8 GHz
Kryo 400 2018 ARMv8.2-A 4-wide 11–13 Yes
8-wide dispatch 		Yes big 8 11 / 8 / 7 No No 64 + 64 512 KiB/Gold Prime

256 KiB/Gold

2 MiB 2, 1+1, 4, 1+3 ? 2.0–2.96 GHz
2-wide 8 No 0 Conditional+
Indirect branch
prediction 		LITTLE 2 16–64? + 16–64? 128 KiB/Silver 4, 6 ? 1.7–1.8 GHz
Kryo 500 2019 ARMv8.2-A 4-wide 11–13 Yes
8-wide dispatch 		Yes big 8 / 7 No ? 512 KiB/Gold Prime

256 KiB/Gold

3 MiB 2, 1+3 ? 2.0–3.2 GHz
2-wide 8 No 0 Conditional+
Indirect branch
prediction 		LITTLE 2 ? 128 KiB/Silver 4, 6 ? 1.7–1.8 GHz
Kryo 600 2020 ARMv8.4-A 4-wide 11–13 Yes
8-wide dispatch 		Yes big 6 / 5 No ? 64 + 64 1024 KiB/Gold Prime

512 KiB/Gold

4 MiB 2, 1+3 ? 2.2–3.0 GHz
2-wide 8 No 0 Conditional+
Indirect branch
prediction 		LITTLE 2 ? 128 KiB/Silver 4, 6 ? 1.7–1.8 GHz
Falkor[77][78] 2017[79] "ARMv8.1-A features";[78] AArch64 only (not 32-bit)[78] 4-wide 10–15 Yes
8-wide dispatch 		Yes ? 8 10 No 24 KiB 88[78] + 32 500KiB 1.25MiB 40–48 ? ?
Samsung M1[80][81] 2016 ARMv8-A 4-wide 13[82] Yes
9-wide dispatch[83] 		96 big 8 14 No No 64 + 32 2 MiB[84] No 4 ? 2.6 GHz
M2[80][81] 2017 ARMv8-A 4-wide 100 Two-level big 10 No No 64 + 64 2 MiB No 4 ? 2.3 GHz
M3[82][85] 2018 ARMv8.2-A 6-wide 15 Yes
12-wide dispatch 		228 Two-level big 12 10 No No 64 + 64 512 KiB per core 4096KB 4 ? 2.7 GHz
M4[86] 2019 ARMv8.2-A 6-wide 15 Yes
12-wide dispatch 		228 Two-level big 12 8 / 7 No No 64 + 64 512 KiB per core 3072KB 2 ? 2.73 GHz
M5[87] 2020 ARMv8.2-A 6-wide Yes
12-wide dispatch 		228 Two-level big 7 No No 64 + 64 512 KiB per core 3072KB 2 ? 2.73 GHz
Fujitsu A64FX[88][89] 2019 ARMv8.2-A 4/2-wide 7+ Yes
5-way? 		Yes n/a 8+ 2*512b[90] 7 No No 64 + 64 8MiB per 12+1 cores No 48+4 ? 1.9 GHz+
HiSilicon TaiShan V110[91] 2019 ARMv8.2-A 4-wide ? Yes n/a 8 7 No No 64 + 64 512 KiB per core 1 MiB per core ? ? ?
Company Core Released Revision Decode Pipeline
depth 		Out-of-order
execution 		Branch
prediction 		big.LITTLE role Exec.
ports 		SIMD Fab
(in nm) 		Simult. MT L0 cache L1 cache
Instr + Data
(in KiB) 		L2 cache L3 cache Core
configu-
rations 		Speed per core (DMIPS/
MHz[note 1]) 		Clock rate ARM part number (in the main ID register)

See also

Notes

  1. ^ a b As Dhrystone (implied in "DMIPS") is a synthetic benchmark developed in 1980s, it is no longer representative of prevailing workloads – use with caution.

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