WDC 65C816

W65C816S microprocessor in PDIP40 package.

The W65C816S (also 65C816 or 65816) is an 8/16-bit microprocessor (MPU) developed and sold by the Western Design Center (WDC). Introduced in 1983, the W65C816S is an enhanced version of the WDC 65C02 8-bit MPU, itself a CMOS enhancement of the venerable MOS Technology 6502 NMOS MPU. The 65 in the part's designation comes from its 65C02 compatibility mode, and the 816 signifies that the MPU has selectable 8– and 16–bit register sizes.

In addition to the availability of 16 bit registers, the W65C816S features extended memory addressing to 24-bits, supporting up to 16 megabytes of random-access memory, an enhanced instruction set, and a 16 bit stack pointer, as well as several new electrical signals for improved system hardware management.

At reset, the W65C816S starts in "emulation mode," meaning it behaves as a 65C02. Following reset, the W65C816S may be switched to "native mode" with a two instruction sequence, causing it to enable all enhanced features, yet still maintain a substantial degree of backward compatibility with most 65C02 software. However, unlike the PDIP40 version of the 65C02, which is a pin-compatible replacement for its NMOS ancestor, the PDIP40 W65C816S is not pin-compatible with any other 6502 family MPU.

Related to the W65C816S is the obsolete W65C802 chip.

History

PLCC-44 version of W65C816S microprocessor, shown mounted on a single-board computer.

Development of the W65C816S commenced in 1982 after Bill Mensch, founder and CEO of WDC, as well as the designer of the 65C02 microprocessor, consulted with Apple Computer on a new version of the Apple II series of personal computers that would, among other things, have improved graphics and sound. Apple wanted an MPU that would be software compatible with the 6502 then in use in the Apple II but with the ability to address more memory, and to load and store 16 bit words.

The result was the 65C816, finished in March 1984, with samples provided to both Apple and Atari. Apple subsequently integrated the 65C816 into the Apple IIGS computer. Mensch was aided during the design process by his sister Kathryn, who was responsible for part of the device's layout.

In the 1990s, the 65C816 (as well as its antecedent, the 65C02) was converted to a fully static core, which made it possible to completely stop the processor clock without losing data in any of the registers. This feature, along with the use of asynchronous static RAM, made it possible to produce designs that used minimal power when in a standby state.

The basic 65C816 design was second-sourced by GTE, Sanyo and others from the mid-to-late 1980s to the early 1990s.

As of 2019, the W65C816S is available from WDC in a 40 pin PDIP or PLCC44 package, as well as a core for ASIC integration (for example Winbond's W55V9x series of TV Edutainment ICs). WDC, itself a fabless semiconductor company, works with various foundries to produce the W65C816S, as well as other compatible products. Discrete processors are available through a number of electronics distributors. For designers who wish to include W65C816S functionality into a custom ASIC, WDC offers RTL (register-transfer level) code in Verilog.

W65C802P

W65C802

In the past, WDC offered a 65(C)02 PDIP40 pin-compatible variant of the W65C816S referred to as the W65C802. The 65C802 was fully hardware-compatible with the 65C02 in all respects, but was 100 percent software compatible with the 65C816, including the use of 16-bit registers. The W65C802 lacked the ability to generate a full 24-bit address, thus limiting it to 64 kilobytes of memory like the 65C02. The 65C802 was produced by WDC and GTE during the mid-to-late 1980s and early 1990s. Typically, when hardware manufacturers designed a project from the ground up, they used the 65C816 rather than the 65C802, resulting in the latter being withdrawn from production.

Features

WDC 65816 features:

WDC 65816 registers

23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 (bit position) Main registers B A Accumulators Index registers X X index Y Y index 0 0 0 0 0 0 0 0 DP Direct Page register 0 0 0 0 0 0 0 0 SP Stack Pointer DB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Data Bank register Program counter PB PC Program Counter Status register N V m x D I Z C SR Status register

• Fully static CMOS design for low power consumption (300µA at 1MHz) and increased noise immunity.
• Wide operating voltage range: 1.8V to 5.0V ± 5%.
• Wide operating frequency range, up to 14 MHz, using a single-phase clock source.
• Emulation mode allows software compatibility with the 65C02, excepting undocumented opcodes (which in 65C02 act as NOPs).
• 24-bit memory addressing provides access to 16MB of memory space.
• 16-bit ALU, accumulator (A), stack pointer (SP), and index registers (X and Y).
• 16-bit Direct Page register (D).
• 8-bit Data Bank (DB) and Program Bank (PB) registers, generating bits 16-23 of 24-bit data and code addresses.
• Valid Data Address (VDA) and Valid Program Address (VPA) outputs for dual cache and cycle steal DMA implementation.
• Vector Pull (VPB) output to indicate when an interrupt vector is being addressed.
• Abort (ABORTB) input and associated vector supports processor repairs of bus error conditions, such as page faults and memory access violations.
• Separate program and data bank registers allow program segmentation or 16MB linear addressing (data only).
• Direct register and stack relative addressing provides capability for reentrant, recursive and re-locatable programming.
• 24 addressing modes—13 original 6502 modes with 92 instructions using 256 op codes, including most new opcodes implemented in the 65C02.
• Block-copy instructions, allowing rapid copying of data structures from one area of RAM to another with minimal code.
• Wait-for-Interrupt (WAI) and Stop-the-Clock (STP) instructions further reduce power consumption, decrease interrupt latency and allows synchronization with external events.
• Co-Processor (COP) instruction with associated vector supports co-processor configurations, e.g., floating point processors
• Reserved "escape" (WDM) instruction for future two-byte opcodes and a link to future designs. (WDM is the initials of W65C816S designer William D. Mensch.)

Applications

Notable

• Acorn Communicator
• Apple IIGS
• Super Nintendo Entertainment System (the console's Ricoh 5A22 CPU is based on the 65C816)
• Nintendo SA-1 (a co-processor chip used in several SNES game cartridges; based on the 65C816)

Less notable

• C-One
• SuperCPU accelerator for the Commodore 64

See also

• Interrupts in 65xx processors

Further reading

• Eyes, David; Lichty, Ron (1986). Programming the 65816 including the 6502, 65C02, and 65802. New York: Brady Books/Prentice Hall Press (Simon & Schuster, Inc). ISBN 0-89303-789-3.
• Ebook on WDC's Documentation page: Programming the 65816, Including the 6502, 65C02 and 65802

External links

• W65C816S website - Western Design Center
• W65C816S datasheet - Western Design Center
• 6502/65C02/65C816 Instruction Set Decoded – From Neil Parker's Apple II page
• A 6502 Programmer's Introduction to the 65816 – A Commodore World article by Brett Tabke; includes CMD's instruction set summary
• 65816/65C816 Technical Documents – Hosted by Zophar's Domain
• Investigating 65C816 Interrupts – An extensive discussion of interrupt processing on the 65C816

This article is based on material taken from the Free On-line Dictionary of Computing prior to 1 November 2008 and incorporated under the "relicensing" terms of the GFDL, version 1.3 or later.