Overview • Architecture • Development • Version • License • Notes
The OBDH 2.0 board is composed of the following main components: MCU, non-volatile memory, voltage monitor with watchdog timer, TTC interface, EPS interface, payloads interface, daughterboard interface, I2C buffers, RS-485 transceiver, and current sensor. It is a FR-4 standard 2 layers PCB with a CubeSat form factor shape and size (90 x 93 mm).
The board design is a microcontroller based hardware connecting different interfaces and peripherals. For more information refer to the documentation in the "Hardware" chapter.
This image refers to the v0.5 release.
The folder fabrication contain 3 "ready to go" files: the gerbers and nc_drills for manufacturing the board, the BOM with all required components, and the pick_place file for automated assembly. Additional files are avaliable in the outputs folder, which contain several useful files and documents, such as: 3D models, bill of materials, schematics, layout prints, and draftsman.
The board has components that should not be soldered simultaneously. Refer to the documentation in the "Assembly" chapter.
The board requires external supply from the PC-104 connector or the JTAG programmer interface. The following diagram present a simplified diagram of the board power. Refer to the documentation in the "Instructions" chapter.
This image refers to the v0.5 release.
The debugging is performed through a serial UART port, using as default a baud rate of 115200 bps, 1 stop bit, and no parity bit. The interface uses a log system standard to improve readability. Refer to the documentation in the "Instructions" chapter.
Automated testing is not avaliable yet.
Refer to the releases page.
This repository containing hardware files is licensed under CERN Open Hardware License, version 2.
Project under development!