clk_wiz_ip.ppf

<?xml version="1.0" encoding="UTF-8" ?>
<!DOCTYPE pinplan>
<pinplan intended_family="Cyclone IV GX" variation_name="clk_wiz_ip" megafunction_name="ALTPLL" specifies="all_ports">
<global>
<pin name="inclk0" direction="input" scope="external" source="clock"  />
<pin name="c0" direction="output" scope="external" source="clock"  />

</global>
</pinplan>