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top.qsf
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2020 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition
# Date created = 17:57:24 June 13, 2021
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# top_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone IV GX"
set_global_assignment -name DEVICE EP4CGX75CF23I7
set_global_assignment -name TOP_LEVEL_ENTITY top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:57:24 JUNE 13, 2021"
set_global_assignment -name LAST_QUARTUS_VERSION "20.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH tb -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_NAME tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME tb -section_id tb
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING ON -section_id eda_simulation
set_global_assignment -name EDA_NATIVELINK_SIMULATION_SETUP_SCRIPT sim_config.do -section_id eda_simulation
set_global_assignment -name VERILOG_FILE top.v
set_global_assignment -name VERILOG_FILE clk_wiz.v
set_global_assignment -name COMMAND_MACRO_FILE sim_config.do
set_global_assignment -name SYSTEMVERILOG_FILE vga_sync.sv
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON
set_global_assignment -name NUM_PARALLEL_PROCESSORS 10
set_global_assignment -name VERILOG_FILE ant_logic.v
set_global_assignment -name VERILOG_FILE debounce.v
set_global_assignment -name SYSTEMVERILOG_FILE logic_fsm.sv
set_global_assignment -name VERILOG_FILE field.v
set_global_assignment -name QIP_FILE clk_wiz_ip.qip
set_global_assignment -name EDA_TEST_BENCH_FILE tb.vhd -section_id tb
set_global_assignment -name VERILOG_FILE mega_mux.v
set_global_assignment -name VERILOG_FILE grid.v
set_global_assignment -name VERILOG_FILE data_to_color.v
set_global_assignment -name VERILOG_FILE ant_body.v
set_global_assignment -name VERILOG_FILE cell_math.v
#-----------------------------------------
set_location_assignment PIN_J10 -to isys_clk
set_location_assignment PIN_F17 -to ovga_vs
set_location_assignment PIN_F16 -to ovga_hs
set_location_assignment PIN_D14 -to R[0]
set_location_assignment PIN_H12 -to R[1]
set_location_assignment PIN_C17 -to R[2]
set_location_assignment PIN_C14 -to R[3]
set_location_assignment PIN_H13 -to R[4]
set_location_assignment PIN_J13 -to R[5]
set_location_assignment PIN_C18 -to G[0]
set_location_assignment PIN_E17 -to G[1]
set_location_assignment PIN_A19 -to G[2]
set_location_assignment PIN_A18 -to G[3]
set_location_assignment PIN_G15 -to G[4]
set_location_assignment PIN_G12 -to G[5]
set_location_assignment PIN_G14 -to B[0]
set_location_assignment PIN_D15 -to B[1]
set_location_assignment PIN_C15 -to B[2]
set_location_assignment PIN_B16 -to B[3]
set_location_assignment PIN_C16 -to B[4]
set_location_assignment PIN_D17 -to B[5]
#-----------------------------------------
#KEY2
set_location_assignment PIN_AB12 -to key_start
#-----------------------------------------
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top