riscv-mini is a simple RISC-V 3-stage pipeline written in Chisel. It has been a crucial example in various project developments, including Chisel3, FIRRTL, Strober, simulation and verification methodologies. It implements RV32I of the User-level ISA Version 2.0 and the Machine-level ISA of the Privileged Architecture Version 1.7. Unlike other simple pipelines, it also contains simple instruction and data caches.
Note that a real-world processor is not the goal of riscv-mini. It is developed as an intermediate example before diving into rocket-chip.