Lib.rs

› Keywords #system-verilog #fpga #hardware #hdl #system-verilog-parser

#verilog

  1. veryl-parser

    A modern hardware description language

    v0.18.0 #verilog #system-verilog #verilog-parser

  2. veryl-analyzer

    A modern hardware description language

    v0.18.0 #system-verilog #verilog #parser

  3. sv-parser

    SystemVerilog parser library fully complient with IEEE 1800-2017

    v0.13.4 1.0K #system-verilog-parser #system-verilog #verilog

  4. sus_compiler

    Compiler for the SUS Hardware Design Language

    v0.3.8 #fpga #verilog #sus #vlsi #hdl

  5. veryl-path

    A modern hardware description language

    v0.18.0 #system-verilog #verilog #verilog-parser

  6. veryl-aligner

    A modern hardware description language

    v0.18.0 #system-verilog #verilog #system-verilog-parser

  7. arborium-verilog

    Verilog grammar for arborium (tree-sitter bindings)

    v2.12.4 180 #syntax-highlighting #tree-sitter #verilog

  8. veryl-metadata

    A modern hardware description language

    v0.18.0 #verilog #system-verilog #system-verilog-parser

  9. veryl-std

    A modern hardware description language

    v0.18.0 #system-verilog #verilog

  10. veryl

    A modern hardware description language

    v0.18.0 #system-verilog #verilog #system-verilog-parser

  11. svls

    SystemVerilog language server

    v0.2.14 100 #language-server #system-verilog #lsp #verilog

  12. spade-common

    Helper crate for https://spade-lang.org/

    v0.16.0 #spade-lang #helper #verilog #spade-language #hdl #llm #expressive #hardware-control #vhdl

  13. spade-ast

    Helper crate for https://spade-lang.org/

    v0.16.0 #spade-lang #documentation #low-level #helper #spade-language #verilog

  14. sv-parser-syntaxtree

    Helper crate of sv-parser

    v0.13.4 850 #system-verilog #system-verilog-parser #verilog

  15. marlin-verilator

    🦀 No nonsense hardware testing in Rust 🛠️

    v0.10.0 #verilog #hardware-testing #verilator #marlin #hardware-simulation #spade #veryl #system-verilog #no-nonsense

  16. sv-parser-parser

    Helper crate of sv-parser

    v0.13.4 1.0K #system-verilog-parser #system-verilog #verilog

  17. yarig

    A register interface generator

    v0.19.2 #register #rif #verilog

  18. spade-parser

    Helper crate for https://spade-lang.org/

    v0.16.0 #spade-lang #documentation #helper #verilog #spade-language #hdl

  19. mdbook-veryl

    A modern hardware description language

    v0.18.0 #system-verilog #verilog #parser

  20. topstitch

    Stitch together Verilog modules with Rust

    v0.93.0 60K #verilog #stitch #together #module #api #slang

  21. veryl-formatter

    A modern hardware description language

    v0.18.0 #system-verilog #verilog #parser

  22. veryl-emitter

    A modern hardware description language

    v0.18.0 #system-verilog #verilog #parser

  23. spade-mir

    Helper crate for https://spade-lang.org/

    v0.16.0 #verilog #spade-lang #helper #clash #level #spade-language

  24. ruverta

    Verilog: Very Simple Verilog Builder

    v0.2.0 #builder #stream #verilog #very-simple #name #state-machine #reg #dff #comb #system-verilog

  25. veryl-migrator

    A modern hardware description language

    v0.17.2 #system-verilog #verilog #parser

  26. hadou

    A TUI frontend for Icarus Verilog with Waveform viewing

    v0.2.5 #verilog #tui #hdl #terminal

  27. spade-types

    Helper crate for https://spade-lang.org/

    v0.16.0 #spade-lang #spade-language #helper #verilog #hdl

  28. sv-parser-pp

    Helper crate of sv-parser

    v0.13.4 750 #system-verilog-parser #system-verilog #verilog

  29. spade-typeinference

    Helper crate for https://spade-lang.org/

    v0.16.0 #spade-lang #spade-language #helper #verilog #level

  30. veryl-ls

    A modern hardware description language

    v0.18.0 #verilog #system-verilog #system-verilog-parser

  31. marlin

    🦀 No nonsense hardware testing in Rust 🛠️

    v0.10.0 #verilog #hardware-testing #hardware-simulation #verilator #spade #veryl #no-nonsense

  32. spade-lang

    The Spade compiler

    v0.16.0 #verilog #compiler #spade #spade-language

  33. veryl-sourcemap

    A modern hardware description language

    v0.18.0 #system-verilog #verilog

  34. sv-parser-error

    Helper crate of sv-parser

    v0.13.4 800 #system-verilog-parser #system-verilog #verilog

  35. svlint

    SystemVerilog linter

    v0.9.5 180 #system-verilog #lint #svls #verilog

  36. bendis

    A patch tool for Bender to work better in HERIS project

    v0.4.0 #bender #hardware #eda #verilog #dependencies

  37. oak-verilog

    Verilog language parser with support for modern Verilog syntax and features

    v0.0.4 #language-syntax #verilog-parser #verilog

  38. rust-hdl-ok-core

    Generic support code for OpalKelly based FPGA modules that use the FrontPanel HDL interface

    v0.46.0 100 #fpga #verilog #hardware

  39. marlin-verilog-macro-builder

    🦀 No nonsense hardware testing in Rust 🛠️

    v0.10.0 #verilog #hardware-testing #macro #marlin #verilator #system-verilog #spade #veryl #hardware-simulation

  40. vcd

    Read and write VCD (Value Change Dump) files

    v0.7.0 2.7K #verilog #eda

  41. cmtc

    compiler providing cmtir-based passes to generate backends including FIRRTL, SystemVerilog and simulators

    v0.1.2 #hdl-dsl #compiler #hdl #verilog #dsl #dsl-compiler

  42. cmtrs

    A rule-based embedded HDL in Rust

    v0.1.2 #hdl-dsl #compiler #hdl #dsl #hardware #verilog #dsl-compiler

  43. flexlint

    A flexible linter with rules defined by regular expression

    v0.2.7 #linter #regex #rules #flexible #defined #lint #forbidden #verilog

  44. pytv

    Python Templated Verilog

    v0.5.5 1.0K #python #verilog #template-generation

  45. rust_hdl_lib_widgets

    Write firmware for FPGAs in Rust - widget crate

    v0.44.0 #fpga #verilog #hardware

  46. cmtir

    The intermediate representation for Cement (cmt2) languages and compiler tools

    v0.1.2 #hdl-dsl #compiler #hdl #dsl #verilog #dsl-compiler

  47. spade-hir

    Helper crate for https://spade-lang.org/

    v0.16.0 #spade-lang #spade-language #documentation #helper #verilog

  48. rust_hdl_lib_sim

    Write firmware for FPGAs in Rust - Simulation crate

    v0.44.0 #fpga #verilog #hardware

  49. kaze

    An HDL embedded in Rust

    v0.1.19 #hdl #verilog

  50. spade-hir-lowering

    Helper crate for https://spade-lang.org/

    v0.16.0 #spade-lang #helper #verilog #level #hdl

  51. spade-ast-lowering

    Helper crate for https://spade-lang.org/

    v0.16.0 #spade-lang #helper #verilog #control #level #spade-language

  52. verugent

    Verilog: Hardware Discription DSL library

    v0.1.3 #verilog #rust-verilog

  53. rust-hdl

    Write firmware for FPGAs in Rust

    v0.46.0 #fpga #verilog #hardware

  54. veryl-simulator

    A modern hardware description language

    v0.18.0 #system-verilog #verilog #parser

  55. verilator

    Automated generation of Verilator test modules

    v0.1.6 #verilog #automated-tests

  56. tree-sitter-verilog

    Verilog grammar for tree-sitter

    v1.0.3 1.8K #tree-sitter #verilog #verilog-parser

  57. rust-hdl-widgets

    Write firmware for FPGAs in Rust - widget crate

    v0.46.0 #fpga #verilog #hardware

  58. rust-hdl-fpga-support

    Support crate for RustHDL - provides FPGA specific code

    v0.46.0 #fpga #verilog #hardware

  59. marlin-spade

    🦀 No nonsense hardware testing in Rust 🛠️

    v0.10.0 #verilog #hardware-testing #marlin #verilator #spade #hardware-simulation #veryl #no-nonsense

  60. marlin-veryl

    🦀 No nonsense hardware testing in Rust 🛠️

    v0.10.0 #verilog #hardware-testing #verilator #marlin #spade #veryl #system-verilog #hardware-simulation #no-nonsense

  61. marlin-verilog

    🦀 No nonsense hardware testing in Rust 🛠️

    v0.10.0 #verilog #hardware-testing #marlin #verilator #tokio-integration #spade #hardware-simulation #veryl #no-nonsense

  62. vast

    Verilog AST library

    v0.3.3 370 #ast #verilog

  63. rust_hdl_lib_fpga_support

    Support crate for RustHDL - provides FPGA specific code

    v0.44.0 #fpga #verilog #hardware

  64. rust_hdl_lib_hls

    Write firmware for FPGAs in Rust - High Level Synthesis crate

    v0.44.0 #fpga #verilog #hardware

  65. rust-hdl-bsp-ok-xem7010

    Support crate for RustHDL - provides Board Support Package for the OpalKelly XEM7010 module (Artix-7 based)

    v0.46.0 #fpga #verilog #hardware

  66. rust-hdl-bsp-ok-xem6010

    Support crate for RustHDL - provides Board Support Package for the OpalKelly XEM6010 FPGA module (Spartan-6 based)

    v0.46.0 #fpga #verilog #hardware

  67. rust_hdl_lib_ok_core

    Generic support code for OpalKelly based FPGA modules that use the FrontPanel HDL interface

    v0.44.0 #fpga #verilog #hardware

  68. rust-hdl-bsp-alchitry-cu

    Support crate for RustHDL - provides Board Support Package for the Alchitry Cu board

    v0.46.0 #fpga #verilog #hardware

  69. rust-hdl-sim

    Write firmware for FPGAs in Rust - Simulation crate

    v0.46.0 #fpga #verilog #hardware

  70. verilated

    Bindings to Verilated APIs for working with Verilator's generated verilog simulators

    v0.1.2 #simulation #verilog #api-bindings

  71. rust_hdl_lib_core

    Write firmware for FPGAs in Rust - core crate

    v0.44.1 #fpga #verilog #hardware

  72. rust-hdl-hls

    Write firmware for FPGAs in Rust - High Level Synthesis crate

    v0.46.0 #fpga #verilog #hardware

  73. svinst

    Determines the modules declared and instantiated in SystemVerilog files, producing a YAML file as output

    v0.1.6 120 #system-verilog #system-verilog-parser #verilog

  74. hoodlum

    HDL generation library for hardware synthesis

    v0.5.0 #verilog #hdl #compile #counter #hardware #hardware-description-language #udp

  75. veriloghex

    Parse Verilog .hex format

    v0.1.0 #verilog #verilog-parser #hex #record #format

  76. librstb

    Write HDL-Testbenches in Rust

    v0.1.1 #verilog #vhdl #eda

  77. rust_hdl_private_macros

    Macro support for RustHDL

    v0.44.0 #fpga #verilog #hardware

  78. virdant

    modern hardware description language

    v0.1.0-rc0 #hardware-description-language #modern #firrtl #chisel #human-readable #lesson #si-five #programming-language #aid #verilog

  79. rust_hls

    Support crate for rust_hls

    v0.2.0 #high-level-synthesis #fpga #verilog #bambu

  80. hdl-bsp-orange-crab

    Support crate for Rust HDL - provides Board Support Package for the Orange Crab board

    v0.1.0 #fpga #verilog #hardware

  81. libreda-structural-verilog

    Parser for structural verilog as it is created by Yosys

    v0.0.5 110 #verilog-parser #verilog #parser

  82. rust-hdl-ok-frontpanel-sys

    OpalKelly FrontPanel library wrapper for the RustHDL crate

    v0.46.0 120 #fpga #verilog #hardware

  83. vcd2df

    'vcd2df' function, which loads a IEEE 1364-1995/2001 VCD (.vcd) file, specified as a parameter of type string containing exactly a file path, and returns an Polars dataframe containing values over time…

    v0.1.2 #arrow #hardware-register #vcd #name #execution-trace #polars-dataframe #string-parameters #verilog #vhdl #distinct

  84. vcd-ng

    Read and write VCD (Value Change Dump) files, the next generation

    v0.2.0 140 #vcd #eda #verilog

  85. sv-filelist-parser

    parse a SystemVerilog Filelist and return a list of files, include directories and defines

    v0.1.3 260 #system-verilog #filelist #verilog

    86. Try searching with DuckDuckGo.

  86. verilog-arc

    proc macro based code generation backend for OpenVAF

    v0.4.2 #proc-macro #verilog #open-vaf #arc #proc-macro-generation #libary

  87. ivgtk

    iverilog and gtkwave chaining tool

    v0.1.0 #gtkwave #iverilog #verilog

  88. swim-marlin

    Parallel test runner for Marlin tests

    v0.1.0 #testing #marlin #swim #test-runner #parallel #hardware-testing #verilog

  89. extract_rust_hdl_interface

    Extracts the information needed for a rust-hdl module from a verilog module

    v0.2.0 #fpga #verilog #rust-hdl

  90. spade-macros

    Helper crate for https://spade-lang.org/

    v0.16.0 #spade-lang #helper #verilog #language #documentation #hdl #llm #spade-language #expressive #hardware-control

  91. rust-hdl-bsp-colorlight-i5

    Support crate for RustHDL - provides Board Support Package for the Colorlight i5 board (Lattice LFE5U-25F-6BG381C based)

    v0.45.1 #fpga #verilog #hardware

  92. sv-parser-macros

    Helper crate of sv-parser

    v0.13.4 2.2K #system-verilog #system-verilog-parser #verilog

  93. wrap_verilog_in_rust_hdl_macro

    A proc-macro to wrap Verilog code in a rust-hdl module

    v0.1.1 #verilog #fpga #wrap #rust-hdl #macro

  94. vpi_export

    Export Rust function to be used on a verilog module through VPI

    v0.1.9 650 #fpga #vpi #verilog #ffi #no-std

  95. rust-hdl-core

    Write firmware for FPGAs in Rust - core crate

    v0.46.0 100 #fpga #verilog #hardware

  96. verilog-filelist-parser

    parse a Verilog Filelist and return a list of files, include directories and defines

    v0.1.2 #system-verilog #filelist #verilog

  97. rust-hdl-bsp-tang-nano-4k

    Support crate for RustHDL - provides Board Support Package for the Tang Nano 4K board (Gowin GW1NSR-LV4C based)

    v0.45.1 #fpga #verilog #hardware

  98. rasta-verilog

    To-Verilog backend for rasta

    v0.1.0 #verilog #hsl #hdl #hardware

  99. marlin-verilog-macro

    🦀 No nonsense hardware testing in Rust 🛠️

    v0.10.0 #verilog #hardware-testing #macro #marlin #verilator #spade #system-verilog #veryl #hardware-simulation #no-nonsense

  100. rust_hdl_lib_ok_frontpanel_sys

    OpalKelly FrontPanel library wrapper for the RustHDL crate

    v0.44.0 #fpga #verilog #hardware

  101. svfmt

    SystemVerilog formatter

    v0.1.0 #system-verilog #svls #verilog #format

  102. marlin-spade-macro

    🦀 No nonsense hardware testing in Rust 🛠️

    v0.10.0 #verilog #hardware-testing #macro #marlin #spade #verilator #veryl #hardware-simulation #no-nonsense

  103. marlin-veryl-macro

    🦀 No nonsense hardware testing in Rust 🛠️

    v0.10.0 #verilog #hardware-testing #macro #marlin #veryl #verilator #spade #hardware-simulation #no-nonsense

  104. cmtrs_macros

    The macros for cmtrs

    v0.1.2 #hdl-dsl #verilog #compiler #hardware #hdl #dsl #dsl-compiler

  105. readmem

    Read support for Verilog $readmemb/$readmemh files

    v0.1.0 #verilog #readmemh #readmemb #content-type #read

  106. rust-hdl-macros

    Macro support for RustHDL

    v0.46.0 130 #fpga #verilog #hardware

  107. rust_hdl_lib_macros

    Macro support for RustHDL

    v0.44.1 #fpga #verilog #hardware

  108. parsv

    Retrieve any subcomponent from a Verilog module

    v0.1.0 #verilog #system-verilog-parser #sub-component #module #retrieve

  109. sv-bindings

    Raw FFI bindings for the (System)Verilog DPI, PLI, and VPI interfaces (IEEE 1800)

    v0.1.2 #system-verilog #vpi #dpi #verilog #system-bindings

  110. rstbrun

    Build and run Rstb tests with Icarus Verilog

    v0.1.1 #verilog #eda