Lib.rs

› Keywords #system-verilog #hdl #hardware #fpga #system-verilog-parser

#verilog

  1. sus_compiler

    Compiler for the SUS Hardware Design Language

    v0.3.10 #fpga #verilog #sus #vlsi #hdl

  2. veryl-parser

    A modern hardware description language

    v0.19.1 130 #verilog #system-verilog #verilog-parser

  3. sv-parser

    SystemVerilog parser library fully complient with IEEE 1800-2017

    v0.13.5 1.6K #system-verilog-parser #system-verilog #verilog

  4. veryl-analyzer

    A modern hardware description language

    v0.19.1 #system-verilog #verilog #parser

  5. veryl-metadata

    A modern hardware description language

    v0.19.1 #verilog #system-verilog #system-verilog-parser

  6. arborium-verilog

    Verilog grammar for arborium (tree-sitter bindings)

    v2.16.0 460 #syntax-highlighting #tree-sitter #verilog

  7. veryl-path

    A modern hardware description language

    v0.19.1 #system-verilog #verilog #verilog-parser

  8. veryl-aligner

    A modern hardware description language

    v0.19.1 #system-verilog #verilog #system-verilog-parser

  9. veryl-std

    A modern hardware description language

    v0.19.1 #system-verilog #verilog

  10. veryl

    A modern hardware description language

    v0.19.1 #system-verilog #verilog #system-verilog-parser

  11. marlin-verilog-macro-builder

    🦀 No nonsense hardware testing in Rust 🛠️

    v0.11.1 #verilog #hardware-testing #macro #marlin #verilator #system-verilog #spade #veryl #hardware-simulation #no-nonsense

  12. yarig

    A register interface generator

    v0.21.7 #register #rif #verilog

  13. svls

    SystemVerilog language server

    v0.2.14 #language-server #system-verilog #lsp #verilog

  14. veryl-simulator

    A modern hardware description language

    v0.19.1 #system-verilog #verilog #parser

  15. spade-ast

    Helper crate for https://spade-lang.org/

    v0.16.0 #spade-lang #documentation #low-level #helper #spade-language #verilog

  16. sv-parser-syntaxtree

    Helper crate of sv-parser

    v0.13.5 1.5K #system-verilog #system-verilog-parser #verilog

  17. marlin-verilator

    🦀 No nonsense hardware testing in Rust 🛠️

    v0.11.1 #verilog #hardware-testing #verilator #marlin #hardware-simulation #spade #veryl #system-verilog #no-nonsense

  18. topstitch

    Stitch together Verilog modules with Rust

    v0.95.1 39K #stitch #verilog #together #module #api #slang

  19. sv-parser-parser

    Helper crate of sv-parser

    v0.13.5 1.5K #system-verilog-parser #system-verilog #verilog

  20. veryl-migrator

    A modern hardware description language

    v0.19.1 #system-verilog #verilog #parser

  21. marlin

    🦀 No nonsense hardware testing in Rust 🛠️

    v0.11.1 #verilog #hardware-testing #hardware-simulation #verilator #spade #veryl #no-nonsense

  22. spade-parser

    Helper crate for https://spade-lang.org/

    v0.16.0 #spade-lang #documentation #helper #verilog #spade-language #hdl #llm

  23. veryl-emitter

    A modern hardware description language

    v0.19.1 #system-verilog #verilog #parser

  24. sv-parser-pp

    Helper crate of sv-parser

    v0.13.4 1.5K #system-verilog-parser #system-verilog #verilog

  25. veryl-formatter

    A modern hardware description language

    v0.19.1 #system-verilog #verilog #parser

  26. mdbook-veryl

    A modern hardware description language

    v0.19.1 #system-verilog #verilog #parser

  27. spade-mir

    Helper crate for https://spade-lang.org/

    v0.16.0 #verilog #spade-lang #helper #clash #level #spade-language

  28. spade-types

    Helper crate for https://spade-lang.org/

    v0.16.0 #spade-lang #spade-language #helper #verilog #hdl

  29. msu-256

    256-bit Ozturk Modular Squaring Unit on hdl-cat and comp-cat-rs

    v0.1.0 #hdl-cat #256-bit #montgomery #compute #modular #verilog #forms #testbench #emit #emission

  30. vcd

    Read and write VCD (Value Change Dump) files

    v0.7.0 9.7K #verilog #eda

  31. veryl-ls

    A modern hardware description language

    v0.19.1 #verilog #system-verilog #system-verilog-parser

  32. pytv

    Python Templated Verilog

    v0.5.6 #python #verilog #template-generation

  33. hadou

    A TUI frontend for Icarus Verilog with Waveform viewing

    v0.2.5 #verilog #tui #hdl #terminal

  34. sv-parser-error

    Helper crate of sv-parser

    v0.13.5 1.5K #system-verilog-parser #system-verilog #verilog

  35. spade-lang

    The Spade compiler

    v0.16.0 #verilog #compiler #spade #spade-language

  36. veryl-sourcemap

    A modern hardware description language

    v0.19.1 #system-verilog #verilog

  37. ruverta

    Verilog: Very Simple Verilog Builder

    v0.2.0 #builder #stream #verilog #very-simple #name #state-machine #reg #dff #comb #system-verilog

  38. svlint

    SystemVerilog linter

    v0.9.5 170 #system-verilog #lint #svls #verilog

  39. spi-i2c-hdl-cat

    SPI and I2C controllers using hdl-cat categorical hardware description

    v0.1.0 #controller #hardware-description #categorical #spi #hdl-cat #i2c #verilog #modes #fsm #monoidal

  40. oak-verilog

    Verilog language parser with support for modern Verilog syntax and features

    v0.0.11 #verilog-parser #verilog #parser

  41. spade-typeinference

    Helper crate for https://spade-lang.org/

    v0.16.0 #spade-lang #spade-language #helper #verilog #level

  42. bendis

    A patch tool for Bender to work better in HERIS project

    v0.4.0 #bender #hardware #verilog #eda #dependencies

  43. rust-hdl-ok-core

    Generic support code for OpalKelly based FPGA modules that use the FrontPanel HDL interface

    v0.46.0 100 #fpga #verilog #hardware

  44. veryl-cosim

    A modern hardware description language

    v0.19.1 #system-verilog #verilog #parser

  45. hdl-cat-kind

    Hardware-describable-type trait (Hw) and type descriptors for hdl-cat

    v0.2.0 #verilog #category-theory #simulation #hardware #hdl

  46. hdl-cat-error

    Shared Error enum for hdl-cat

    v0.2.0 #verilog #hardware #category-theory #simulation #hdl

  47. hdl-cat

    Umbrella crate re-exporting the hdl-cat workspace

    v0.5.0 #verilog #hardware #category-theory #simulation #hdl

  48. tree-sitter-verilog

    Verilog grammar for tree-sitter

    v1.0.3 3.9K #tree-sitter #verilog #verilog-parser

  49. cmtc

    compiler providing cmtir-based passes to generate backends including FIRRTL, SystemVerilog and simulators

    v0.1.2 #hdl-dsl #compiler #hdl #verilog #dsl #dsl-compiler

  50. rust_hdl_lib_widgets

    Write firmware for FPGAs in Rust - widget crate

    v0.44.0 #fpga #verilog #hardware

  51. cmtrs

    A rule-based embedded HDL in Rust

    v0.1.2 #hdl-dsl #compiler #hdl #dsl #hardware #verilog #dsl-compiler

  52. flexlint

    A flexible linter with rules defined by regular expression

    v0.2.7 #linter #regex #rules #flexible #defined #lint #forbidden #verilog

  53. spade-hir

    Helper crate for https://spade-lang.org/

    v0.16.0 #spade-lang #spade-language #documentation #helper #verilog

  54. kaze

    An HDL embedded in Rust

    v0.1.19 #hdl #verilog

  55. spade-hir-lowering

    Helper crate for https://spade-lang.org/

    v0.16.0 #spade-lang #helper #verilog #level #hdl

  56. marlin-spade

    🦀 No nonsense hardware testing in Rust 🛠️

    v0.11.1 #verilog #hardware-testing #marlin #verilator #spade #hardware-simulation #veryl #no-nonsense

  57. spade-ast-lowering

    Helper crate for https://spade-lang.org/

    v0.16.0 #spade-lang #helper #verilog #control #level #spade-language

  58. rust_hdl_lib_sim

    Write firmware for FPGAs in Rust - Simulation crate

    v0.44.0 #fpga #verilog #hardware

  59. marlin-veryl

    🦀 No nonsense hardware testing in Rust 🛠️

    v0.11.1 #verilog #hardware-testing #verilator #marlin #spade #veryl #system-verilog #hardware-simulation #no-nonsense

  60. verugent

    Verilog: Hardware Discription DSL library

    v0.1.3 #verilog #rust-verilog

  61. rust-hdl

    Write firmware for FPGAs in Rust

    v0.46.0 #fpga #verilog #hardware

  62. cmtir

    The intermediate representation for Cement (cmt2) languages and compiler tools

    v0.1.2 #hdl-dsl #compiler #hdl #dsl #verilog #dsl-compiler

  63. rust-hdl-widgets

    Write firmware for FPGAs in Rust - widget crate

    v0.46.0 110 #fpga #verilog #hardware

  64. marlin-verilog

    🦀 No nonsense hardware testing in Rust 🛠️

    v0.11.1 #verilog #hardware-testing #marlin #verilator #tokio-integration #spade #hardware-simulation #veryl #no-nonsense

  65. hdl-cat-verilog

    Verilog AST + emitter for hdl-cat IR graphs

    v0.6.0 #verilog #category-theory #hardware #hdl #simulation

  66. verilator

    Automated generation of Verilator test modules

    v0.1.6 #verilog #automated-tests

  67. hdl-cat-circuit

    Circuit as symmetric monoidal category built on comp-cat-rs and hdl-cat-ir

    v0.2.0 #verilog #hardware #category-theory #hdl #simulation

  68. vast

    Verilog AST library

    v0.3.3 320 #ast #verilog

  69. hdl-cat-sim

    Stream-based simulator for hdl-cat Sync machines

    v0.2.0 #verilog #simulation #category-theory #hardware #hdl

  70. rust_hdl_lib_fpga_support

    Support crate for RustHDL - provides FPGA specific code

    v0.44.0 #fpga #verilog #hardware

  71. rust-hdl-bsp-ok-xem7010

    Support crate for RustHDL - provides Board Support Package for the OpalKelly XEM7010 module (Artix-7 based)

    v0.46.0 #fpga #verilog #hardware

  72. rust-hdl-bsp-ok-xem6010

    Support crate for RustHDL - provides Board Support Package for the OpalKelly XEM6010 FPGA module (Spartan-6 based)

    v0.46.0 #fpga #verilog #hardware

  73. rust_hdl_lib_ok_core

    Generic support code for OpalKelly based FPGA modules that use the FrontPanel HDL interface

    v0.44.0 #fpga #verilog #hardware

  74. rust-hdl-bsp-alchitry-cu

    Support crate for RustHDL - provides Board Support Package for the Alchitry Cu board

    v0.46.0 #fpga #verilog #hardware

  75. hdl-cat-ir

    Hardware IR: typed wires, gate instructions, free-category embedding

    v0.2.0 #verilog #hardware #category-theory #simulation #hdl

  76. hdl-cat-bits

    Bit-precise unsigned and signed integer newtypes for hdl-cat

    v0.2.0 #verilog #hardware #category-theory #hdl #simulation

  77. hdl-cat-sync

    Mealy/Moore machines as IR arrows with initial state

    v0.2.0 #verilog #category-theory #hardware #hdl #simulation

  78. rust-hdl-sim

    Write firmware for FPGAs in Rust - Simulation crate

    v0.46.0 #fpga #verilog #hardware

  79. hdl-cat-signal

    Clock-domain-indexed signal type over comp-cat-rs Stream

    v0.2.0 #verilog #hardware #category-theory #simulation #hdl

  80. hdl-cat-std

    Standard component library for hdl-cat

    v0.2.0 #verilog #category-theory #hardware #hdl #simulation

  81. verilated

    Bindings to Verilated APIs for working with Verilator's generated verilog simulators

    v0.1.2 #simulation #verilog #api-bindings

  82. rust-hdl-hls

    Write firmware for FPGAs in Rust - High Level Synthesis crate

    v0.46.0 #fpga #verilog #hardware

  83. rust_hdl_lib_core

    Write firmware for FPGAs in Rust - core crate

    v0.44.1 #fpga #verilog #hardware

  84. hoodlum

    HDL generation library for hardware synthesis

    v0.5.0 #verilog #hdl #compile #hardware #counter #hardware-description-language #udp

  85. rust-hdl-fpga-support

    Support crate for RustHDL - provides FPGA specific code

    v0.46.0 #fpga #verilog #hardware

  86. svinst

    Determines the modules declared and instantiated in SystemVerilog files, producing a YAML file as output

    v0.1.6 #system-verilog #system-verilog-parser #verilog

  87. librstb

    Write HDL-Testbenches in Rust

    v0.1.1 #verilog #vhdl #eda

  88. rust_hls

    Support crate for rust_hls

    v0.2.0 #high-level-synthesis #fpga #verilog #bambu

  89. rust_hdl_private_macros

    Macro support for RustHDL

    v0.44.0 #fpga #verilog #hardware

  90. virdant

    modern hardware description language

    v0.1.0-rc0 #hardware-description-language #modern #firrtl #chisel #human-readable #lesson #si-five #programming-language #aid #verilog

  91. hdl-bsp-orange-crab

    Support crate for Rust HDL - provides Board Support Package for the Orange Crab board

    v0.1.0 #fpga #verilog #hardware

  92. libreda-structural-verilog

    Parser for structural verilog as it is created by Yosys

    v0.0.5 110 #verilog-parser #verilog #parser

  93. rust-hdl-ok-frontpanel-sys

    OpalKelly FrontPanel library wrapper for the RustHDL crate

    v0.46.0 120 #fpga #verilog #hardware

  94. veriloghex

    Parse Verilog .hex format

    v0.1.0 #verilog #verilog-parser #iterator #hex #record

  95. vcd-ng

    Read and write VCD (Value Change Dump) files, the next generation

    v0.2.0 140 #vcd #eda #verilog

    96. Try searching with DuckDuckGo.

  96. sv-filelist-parser

    parse a SystemVerilog Filelist and return a list of files, include directories and defines

    v0.1.3 350 #system-verilog #filelist #verilog

  97. marlin-verilog-macro

    🦀 No nonsense hardware testing in Rust 🛠️

    v0.11.1 #verilog #hardware-testing #macro #verilator #marlin #spade #system-verilog #veryl #hardware-simulation #no-nonsense

  98. verilog-arc

    proc macro based code generation backend for OpenVAF

    v0.4.2 #proc-macro #verilog #open-vaf #arc #proc-macro-generation #libary

  99. vcd2df

    'vcd2df' function, which loads a IEEE 1364-1995/2001 VCD (.vcd) file, specified as a parameter of type string containing exactly a file path, and returns an Polars dataframe containing values over time…

    v0.1.2 #arrow #hardware-register #vcd #name #execution-trace #polars-dataframe #string-parameters #verilog #vhdl #distinct

  100. ivgtk

    iverilog and gtkwave chaining tool

    v0.1.0 #gtkwave #iverilog #verilog

  101. swim-marlin

    Parallel test runner for Marlin tests

    v0.1.0 #testing #marlin #swim #test-runner #parallel #hardware-testing #verilog

  102. extract_rust_hdl_interface

    Extracts the information needed for a rust-hdl module from a verilog module

    v0.2.0 #fpga #verilog #rust-hdl

  103. spade-macros

    Helper crate for https://spade-lang.org/

    v0.16.0 #spade-lang #helper #verilog #language #documentation #hdl #llm #spade-language #expressive #hardware-control

  104. sv-parser-macros

    Helper crate of sv-parser

    v0.13.5 1.5K #system-verilog #system-verilog-parser #verilog

  105. rust-hdl-bsp-colorlight-i5

    Support crate for RustHDL - provides Board Support Package for the Colorlight i5 board (Lattice LFE5U-25F-6BG381C based)

    v0.45.1 #fpga #verilog #hardware

  106. wrap_verilog_in_rust_hdl_macro

    A proc-macro to wrap Verilog code in a rust-hdl module

    v0.1.1 #verilog #fpga #wrap #rust-hdl #macro

  107. rust_hdl_lib_hls

    Write firmware for FPGAs in Rust - High Level Synthesis crate

    v0.44.0 #fpga #verilog #hardware

  108. vpi_export

    Export Rust function to be used on a verilog module through VPI

    v0.1.9 650 #fpga #vpi #verilog #ffi #no-std

  109. rust-hdl-core

    Write firmware for FPGAs in Rust - core crate

    v0.46.0 130 #fpga #verilog #hardware

  110. verilog-filelist-parser

    parse a Verilog Filelist and return a list of files, include directories and defines

    v0.1.2 #system-verilog #filelist #verilog

  111. rust-hdl-bsp-tang-nano-4k

    Support crate for RustHDL - provides Board Support Package for the Tang Nano 4K board (Gowin GW1NSR-LV4C based)

    v0.45.1 #fpga #verilog #hardware

  112. minroot-hdl

    hdl-cat hardware blocks for MinRoot VDF

    v0.1.1 #verilog #minroot #hardware #vdf #block #hdl-cat #field-element #combinational

  113. marlin-spade-macro

    🦀 No nonsense hardware testing in Rust 🛠️

    v0.11.1 #verilog #hardware-testing #macro #marlin #spade #verilator #veryl #hardware-simulation #no-nonsense

  114. rasta-verilog

    To-Verilog backend for rasta

    v0.1.0 #verilog #hsl #hdl #hardware

  115. rust_hdl_lib_ok_frontpanel_sys

    OpalKelly FrontPanel library wrapper for the RustHDL crate

    v0.44.0 #fpga #verilog #hardware

  116. svfmt

    SystemVerilog formatter

    v0.1.0 #system-verilog #svls #verilog #format

  117. marlin-veryl-macro

    🦀 No nonsense hardware testing in Rust 🛠️

    v0.11.1 #verilog #hardware-testing #macro #marlin #veryl #verilator #spade #hardware-simulation #no-nonsense

  118. readmem

    Read support for Verilog $readmemb/$readmemh files

    v0.1.0 #verilog #readmemh #readmemb #content-type #read

  119. rust-hdl-macros

    Macro support for RustHDL

    v0.46.0 130 #fpga #verilog #hardware

  120. cmtrs_macros

    The macros for cmtrs

    v0.1.2 #hdl-dsl #verilog #compiler #hardware #hdl #dsl #dsl-compiler

  121. rust_hdl_lib_macros

    Macro support for RustHDL

    v0.44.1 #fpga #verilog #hardware

  122. parsv

    Retrieve any subcomponent from a Verilog module

    v0.1.0 #verilog #system-verilog-parser #sub-component #module #retrieve