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XiangShan is an open-source, high-performance RISC-V processor project that implements out-of-order superscalar cores using Chisel for hardware construction. The design targets modern performance goals—deep pipelines, speculative execution, multi-issue decode/execute, and sophisticated branch prediction—while remaining synthesizable for ASIC flows and portable to FPGAs for research. A modular microarchitecture separates frontend, backend, and memory subsystems with coherent caches and scalable interconnects, enabling multi-core configurations. The project invests heavily in verification: differential testing against reference models, extensive random instruction tests, and full software stacks (bootloaders, Linux) to validate correctness under realistic workloads. Tooling around the core (build scripts, simulators, waveform/debug support) lowers the barrier for academics and industry contributors to experiment and extend.
Features
- Supports RV64GCBVH RISC-V ISA (general + compressed + bit/byte vector + hypervisor etc)
- Modular design of pipeline, vector units, co-processor / accelerator support etc
- Agile development methodology with tools for functional verification, debugging, performance validation
- Extensive documentation, user guide, design documents, with translation/localization support (English / Chinese etc)
- Capability to integrate or target actual silicon or tape-out flows, and use real synthesis toolchains etc
- Benchmarks and performance oriented work: pushing for high frequency, efficient vector processing etc to match or exceed performance of ARM Cortex-A76 etc.
Project Samples
