EXP NO: 01 VERIFICATION OF LOGIC GATES AIM: To develop the VHDL code for logic gates by using Active

HDL 6.3 LOGIC DIAGRAM: AND GATE: LOGIC DIAGRAM: OR GATE: LOGICDIAGRAM

TRUTH TABLE: A 0 0 1 1 B 0 1 0 1 Y=AB 0 0 0 1

TRUTH TABLE:

A NOT GATE: NAND GATE: LOGICDIAGRAM A 0 0 1 1 XOR GATE: LOGICDIAGRAM 0 0 1 1

B 0 1 0 1 B 0 1 0 1

Y=A+B 0 1 1 1 Y=(AB) 1 1 1 0

LOGIC DIAGRAM: TRUTH TABLE

TRUTH TABLE: A 0 1 Y=A 1 0

NOR GATE: LOGIC DIAGRAM:

TRUTH TABLE: A 0 0 1 1 B 0 1 0 1 Y=(A+B) 1 0 0 0

TRUTH TABLE A 0 0 1 1 B 0 1 0 1 0 1 1 0

XNOR GATE: LOGIC DIAGRAM: A 0 0 1 1 VHDL SOUCE CODE: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity logicgates is Port ( a : in std_logic; b : in std_logic; c : out std_logic_vector(6 downto 0)); end logicgates; architecture dataflow of logicgates is begin c(0)<= a and b; c(1)<= a or b;

TRUTH TABLE: B 0 1 0 1 1 0 0 1

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c(2)<= a nand b; c(3)<= a nor b; c(4)<= a xor b; c(5)<= a xnor b; c(6)<= not a; end dataflow; Wave Form: RESULT: Thus the outputs of Basic Logic Gates are verified by simulating the VHDL code.

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EXP NO: 02 ADDERS AND SUBTRACTORS AIM: To develop the VHDL code for adders and subtractors by using Active HDL 6.3. BASIC ADDERS & SUBTRACTORS: HALF ADDER: LOGIC DIAGRAM: TRUTH TABLE:

A 0 0 1 1 VHDL SOURCE CODE: Dataflow Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity hadd is Port ( a : in std_logic; b : in std_logic; sum : out std_logic; carry : out std_logic); end hadd; architecture dataflow of hadd is begin sum <= a xor b; carry <= a and b; end dataflow; Behavioral Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity haddbehavioral is Port ( a : in std_logic; b : in std_logic; sum : out std_logic; carry : out std_logic); end haddbehavioral; architecture Behavioral of haddbehavioral is begin p1:process (a,b) begin sum<= a xor b; carry<= a and b; end process p1; end Behavioral;

B 0 1 0 1

SUM 0 1 1 0

CARRY 0 0 0 1

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Structural Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity haddstructural is Port ( a : in std_logic; b : in std_logic; sum : out std_logic; carry : out std_logic); end haddstructural; architecture structural of haddstructural is component xor2 port(a,b:in std_logic; z:out std_logic); end component; component and2 port(a,b:in std_logic; z:out std_logic); end component; begin x1: xor2 port map (a,b,sum); a1: and2 port map (a,b,carry); end structural; and2 component source code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity and2 is Port ( a : in std_logic; b : in std_logic; z : out std_logic); end and2; architecture dataflow of and2 is begin z<= a and b; end dataflow; xor2 component source code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity xor2 is Port ( a : in std_logic; b : in std_logic; z : out std_logic); end xor2; architecture dataflow of xor2 is begin z<= a xor b; end dataflow; FULL ADDER:

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LOGIC DIAGRAM: A 0 0 0 0 1 1 1 1 VHDL SOURCE CODE: Dataflow Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity fadd_dataflow is Port ( a : in std_logic; b : in std_logic; c : in std_logic; sum : out std_logic; carry : out std_logic); end fadd_dataflow; architecture dataflow of fadd_dataflow is signal p,q,r,s:std_logic; begin p<= a xor b; q<= a and b; r<= b and c; s<= c and a; sum<= p xor c; carry<= q or r or s; end dataflow; Behavioral Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity fadd_behv is Port ( a : in std_logic; b : in std_logic; c : in std_logic; sum : out std_logic; carry : out std_logic); end fadd_behv; architecture Behavioral of fadd_behv is begin p1:process(a,b,c)

TRUTH TABLE: B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 SUM 0 1 1 0 1 0 0 1 CARRY 0 0 0 1 0 1 1 1

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variable r,s,t:std_logic; begin r:= a and b; s:= b and c; t:= c and a; sum<= a xor b xor c; carry<= r or s or t; end process p1; end Behavioral; Structural Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity fadd_structural is Port ( a : in std_logic; b : in std_logic; c : in std_logic; sum : out std_logic; carry : out std_logic); end fadd_structural; architecture structural of fadd_structural is component xor2 port(a,b:in std_logic; z:out std_logic); end component; component and2 port(a,b:in std_logic; z:out std_logic); end component; component or3 port(a,b,c:in std_logic; z:out std_logic); end component; signal p,q,r,s:std_logic; begin x1: xor2 port map (a,b,p); x2: xor2 port map (p,c,sum); a1: and2 port map (a,b,q); a2: and2 port map (b,c,r); a3: and2 port map (c,a,s); o1: or3 port map (q,r,s,carry); end structural; and2 component source code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity and2 is Port ( a : in std_logic; b : in std_logic; z : out std_logic); end and2;

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architecture dataflow of and2 is begin z<= a and b; end dataflow; or3 component source code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity or3 is Port ( a : in std_logic; b : in std_logic; c : in std_logic; z : out std_logic); end or3; architecture dataflow of or3 is begin z<= a or b or c; end dataflow; xor2 component source code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity xor2 is Port ( a : in std_logic; b : in std_logic; z : out std_logic); end xor2; architecture dataflow of xor2 is begin z<= a xor b; end dataflow; FULL SUBSTRACTOR: LOGIC DIAGRAM: 0 0 0 0 1 1 1 1 VHDL SOURCE CODE Dataflow Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 TRUTH TABLE: A B C DIFFERENCE 0 1 1 0 1 0 0 1 BORROW 0 1 1 1 0 0 0 1

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use IEEE.STD_LOGIC_UNSIGNED.ALL; entity fsub_dataflow is Port ( a : in std_logic; b : in std_logic; c : in std_logic; diff : out std_logic; borrow : out std_logic); end fsub_dataflow; architecture dataflow of fsub_dataflow is signal abar:std_logic; begin abar<=not a; diff<=a xor b xor c; borrow<=(abar and b) or (b and c) or (c and abar); end dataflow; Behavioral Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity fsub_behv is Port ( a : in std_logic; b : in std_logic; c : in std_logic; diff : out std_logic; borrow : out std_logic); end fsub_behv; architecture Behavioral of fsub_behv is begin p1:process(a,b,c) variable abar,r,s,t:std_logic; begin abar:=not a; r:=abar and b; s:=b and c; t:=c and abar; diff<=a xor b xor c; borrow<=r or s or t; end process p1; end Behavioral; Structural Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity fsub_structural is Port ( a : in std_logic; b : in std_logic; c : in std_logic; diff : out std_logic; borrow : out std_logic); end fsub_structural; architecture structural of fsub_structural is component xor2 port(a,b:in std_logic; z:out std_logic);

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end component; component and2 port(a,b:in std_logic; z:out std_logic); end component; component not1 port(a:in std_logic; z:out std_logic); end component; component or3 port(a,b,c:in std_logic; z:out std_logic); end component; signal p,q,r,s,abar:std_logic; begin x1:xor2 port map (a,b,p); x2:xor2 port map (p,c,diff); n1:not1 port map (a,abar); a1:and2 port map (abar,b,q); a2:and2 port map (b,c,r); a3:and2 port map (c,abar,s); o1:or3 port map (q,r,s,borrow); end structural; FULL ADDER USING TWO HALF ADDERS: LOGIC DIAGRAM: A 0 0 0 0 1 1 1 1 VHDL SOURCE CODE: Structural Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity fadd2 is Port ( a : in std_logic; b : in std_logic; c : in std_logic; sum : out std_logic; carry : out std_logic); end fadd2; architecture structural of fadd2 is component hadd port(a,b:in std_logic; sum,carry:out std_logic); end component; component or2 port(a,b:in std_logic; B 0 0 1 1 0 0 1 1 TRUTH TABLE: C 0 1 0 1 0 1 0 1 SUM 0 1 1 0 1 0 0 1 CARRY 0 0 0 1 0 1 1 1

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z:out std_logic); end component; signal p,q,r:std_logic; begin h1:hadd port map (a,b,p,q); h2:hadd port map (p,c,sum,r); o1:or2 port map (r,q,carry); end structural; hadd component source code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity hadd is Port ( a : in std_logic; b : in std_logic; sum : out std_logic; carry : out std_logic); end hadd; architecture dataflow of hadd is begin sum <= a xor b; carry <= a and b; end dataflow; or2 component source code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity or2 is Port ( a : in std_logic; b : in std_logic; z : out std_logic); end or2; architecture dataflow of or2 is begin z<= a or b; end dataflow; FULL SUBTRACTOR USING TWO HALF SUBTRACTORS: LOGIC DIAGRAM: A 0 0 0 0 1 1 1 1 TRUTH TABLE: B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 DIFFERENCE 0 1 1 0 1 0 0 1 BORROW 0 1 1 1 0 0 0 1

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VHDL SOURCE CODE: Structural Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity fsub2 is Port ( a : in std_logic; b : in std_logic; c : in std_logic; diff : out std_logic; borrow : out std_logic); end fsub2; architecture structural of fsub2 is component hsub_dataflow port(a,b:in std_logic; diff,borrow:out std_logic); end component; component or2 port(a,b:in std_logic; z:out std_logic); end component; signal p,q,r:std_logic; begin h1:hsub_dataflow port map (a,b,p,q); h2:hsub_dataflow port map (p,c,diff,r); o1:or2 port map (r,q,borrow); end structural; hsub component source code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity hsub_dataflow is Port ( a : in std_logic; b : in std_logic; diff : out std_logic; borrow : out std_logic); end hsub_dataflow; architecture dataflow of hsub_dataflow is begin diff <= a xor b; borrow <= not a and b; end dataflow;

RIPPLE CARRY ADDER (Binary adder):

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LOGIC DIAGRAM:

A(0) B(0)

A(1) B(1) A(2) B(2) A(3) B(3)

Cin

S(0)

S(1)

S(2)

S(3)

VHDL SOURCE CODE Structural Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity rca is Port ( a : in std_logic_vector(3 downto 0); b : in std_logic_vector(3 downto 0); c : in std_logic; s : out std_logic_vector(3 downto 0); cout : out std_logic); end rca; architecture structural of rca is component fadd_behv port(a,b,c:in std_logic; sum,carry:out std_logic); end component; signal c0,c1,c2:std_logic; begin f1:fadd_behv port map (a(0),b(0),c,s(0),c0); f2:fadd_behv port map (a(1),b(1),c0,s(1),c1); f3:fadd_behv port map (a(2),b(2),c1,s(2),c2); f4:fadd_behv port map (a(3),b(3),c2,s(3),cout); end structural; fadd_behv component source code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity fadd_behv is Port ( a : in std_logic; b : in std_logic; c : in std_logic; sum : out std_logic;

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carry : out std_logic); end fadd_behv; architecture Behavioral of fadd_behv is begin p1:process(a,b,c) variable r,s,t:std_logic; begin r:= a and b; s:= b and c; t:= c and a; sum<= a xor b xor c; carry<= r or s or t; end process p1; end Behavioral; FAST ADDERS: CARRY SELECT ADDER: LOGIC DIAGRAM:

VHDL SOURCE CODE: Structural Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity csa is Port ( a : in std_logic_vector(7 downto 0); b : in std_logic_vector(7 downto 0); c : in std_logic; su : inout std_logic_vector(3 downto 0); sd : inout std_logic_vector(3 downto 0); s : out std_logic_vector(7 downto 0); cout : out std_logic); end csa; architecture structural of csa is component rca port(a,b:in std_logic_vector(3 downto 0); c:in std_logic; s:out std_logic_vector(3 downto 0);

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cout:out std_logic); end component; component mux2 port(a,b,s:in std_logic; z:out std_logic); end component; signal c1,c2,c3:std_logic; begin r1:rca port map (a(3 downto 0),b(3 downto 0),c,s(3 downto 0),c1); r2:rca port map (a(7 downto 4),b(3 downto 0),'0',su(3 downto 0),c2); r3:rca port map (a(7 downto 4),b(3 downto 0),'1',sd(3 downto 0),c3); m1:mux2 port map (su(0),sd(0),c1,s(4)); m2:mux2 port map (su(1),sd(1),c1,s(5)); m3:mux2 port map (su(2),sd(2),c1,s(6)); m4:mux2 port map (su(3),sd(3),c1,s(7)); m5:mux2 port map (c2,c3,c1,cout); end structural; rca component source code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity rca is Port ( a : in std_logic_vector(3 downto 0); b : in std_logic_vector(3 downto 0); c : in std_logic; s : out std_logic_vector(3 downto 0); cout : out std_logic); end rca; architecture structural of rca is component fadd_behv port(a,b,c:in std_logic; sum,carry:out std_logic); end component; signal c0,c1,c2:std_logic; begin f1:fadd_behv port map (a(0),b(0),c,s(0),c0); f2:fadd_behv port map (a(1),b(1),c0,s(1),c1); f3:fadd_behv port map (a(2),b(2),c1,s(2),c2); f4:fadd_behv port map (a(3),b(3),c2,s(3),cout); end structural; mux2 component source code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity mux2 is Port ( a : in std_logic; b : in std_logic; s : in std_logic; z : out std_logic); end mux2; architecture behv of mux2 is begin

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process(a,b,s) begin if (s='0') then z<=a; else z<=b; end if; end process; end behv;

CARRY SKIP ADDER: LOGIC DIAGRAM:

VHDL SOURCE CODE: Structural Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity cskadd is Port ( a : in std_logic_vector(7 downto 0); b : in std_logic_vector(7 downto 0); c : in std_logic; s : out std_logic_vector(7 downto 0); cout : out std_logic); end cskadd; architecture structural of cskadd is component rca port(a,b:in std_logic_vector(3 downto 0); c:in std_logic; s:out std_logic_vector(3 downto 0); cout:out std_logic); end component; component skip port(a,b:in std_logic_vector(3 downto 0); c:in std_logic; z:out std_logic); end component; component or2

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port(a,b:in std_logic; z:out std_logic); end component; signal c1,c2,c3,x1,x2:std_logic; begin r1:rca port map (a(3 downto 0),b(3 downto 0),c,s(3 downto 0),c1); r2:rca port map (a(7 downto 4),b(7 downto 4),c2,s(7 downto 4),c3); s1:skip port map (a(3 downto 0),b(3 downto 0),c,x1); s2:skip port map (a(7 downto 4),b(7 downto 4),c2,x2); o1:or2 port map (c1,x1,c2); o2:or2 port map (c3,x2,cout); end structural; rca component source code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity rca is Port ( a : in std_logic_vector(3 downto 0); b : in std_logic_vector(3 downto 0); c : in std_logic; s : out std_logic_vector(3 downto 0); cout : out std_logic); end rca; architecture structural of rca is component fadd_behv port(a,b,c:in std_logic; sum,carry:out std_logic); end component; signal c0,c1,c2:std_logic; begin f1:fadd_behv port map (a(0),b(0),c,s(0),c0); f2:fadd_behv port map (a(1),b(1),c0,s(1),c1); f3:fadd_behv port map (a(2),b(2),c1,s(2),c2); f4:fadd_behv port map (a(3),b(3),c2,s(3),cout); end structural; or2 component source code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity or2 is Port ( a : in std_logic; b : in std_logic; z : out std_logic); end or2; architecture dataflow of or2 is begin z<= a or b; end dataflow;

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skip component source code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity skip is Port ( a : in std_logic_vector(3 downto 0); b : in std_logic_vector(3 downto 0); c : in std_logic; z : out std_logic); end skip; architecture dataflow of skip is begin z<=(a(0) xor b(0)) and (a(1) xor b(1)) and (a(2) xor b(2)) and (a(3) xor b(3)) and c; end dataflow;

CARRY LOOK AHEAD ADDER: LOGIC DIAGRAM:

VHDL SOURCE CODE: Structural Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity calkadd is Port ( a : in std_logic_vector(7 downto 0); b : in std_logic_vector(7 downto 0); c : in std_logic; s : out std_logic_vector(7 downto 0); cout : out std_logic); end calkadd; architecture structural of calkadd is component fulladd port(a,b,c:in std_logic; s,ca:out std_logic); end component; signal c0,c1,c2,c3,c4,c5,c6:std_logic; begin

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f1:fulladd port map (a(0),b(0),c,s(0),c0); f2:fulladd port map (a(1),b(1),c0,s(1),c1); f3:fulladd port map (a(2),b(2),c1,s(2),c2); f4:fulladd port map (a(3),b(3),c2,s(3),c3); f5:fulladd port map (a(4),b(4),c3,s(4),c4); f6:fulladd port map (a(5),b(5),c4,s(5),c5); f7:fulladd port map (a(6),b(6),c5,s(6),c6); f8:fulladd port map (a(7),b(7),c6,s(7),cout); end structural; fulladd component source code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity fulladd is Port ( a : in std_logic; b : in std_logic; c : in std_logic; s : out std_logic; ca : out std_logic); end fulladd; architecture dataflow of fulladd is signal l,m,g,p:std_logic; begin l<=a xor b; m<=p and c; g<=a and b; p<=a or b; s<=c xor l; ca<=g or m; end dataflow; VERILOG SOURCE CODE: Structural Modeling: module clkadd(x, y, cin, sum, cout); input [7:0] x; input [7:0] y; input cin; output [7:0] sum; output cout; wire a1,a2,a3,a4,a5,a6,a7; fulladddataflow f1(x[0],y[0],cin,sum[0],a1), f2(x[1],y[1],a1,sum[1],a2), f3(x[2],y[2],a2,sum[2],a3), f4(x[3],y[3],a3,sum[3],a4), f5(x[4],y[4],a4,sum[4],a5), f6(x[5],y[5],a5,sum[5],a6), f7(x[6],y[6],a6,sum[6],a7), f8(x[7],y[7],a7,sum[7],cout); endmodule fulladd component source code: module fulladddataflow(a, b, cin, sum, carry); input a; input b; input cin; output sum;

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output carry; assign sum=a^b^cin; assign carry=(a & b) | (b & cin) | (cin & a); endmodule TEST BENCH(VHDL): LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY test_vhd IS END test_vhd; ARCHITECTURE behavior OF test_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT calkadd PORT( a : IN std_logic_vector(7 downto 0); b : IN std_logic_vector(7 downto 0); c : IN std_logic; s : OUT std_logic_vector(7 downto 0); cout : OUT std_logic ); END COMPONENT; --Inputs SIGNAL c : std_logic := '0'; SIGNAL a : std_logic_vector(7 downto 0) := (others=>'0'); SIGNAL b : std_logic_vector(7 downto 0) := (others=>'0'); --Outputs SIGNAL s : std_logic_vector(7 downto 0); SIGNAL cout : std_logic; BEGIN -- Instantiate the Unit Under Test (UUT) uut: calkadd PORT MAP( a => a, b => b, c => c, s => s, cout => cout ); tb : PROCESS BEGIN a<="11111010";b<="10101011";c<='1'; wait for 200ps; a<="11001011";b<="11100011";c<='0'; wait for 200ps; END PROCESS; END; Simulation output: RESULT: Thus the OUTPUTs of Adders,Subtractors and Fast Adders are verified by synthesizing and simulating the VHDL and VERILOG code.

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EXP NO: 03 ENCODERS AND DECODERS AIM

DATE:

To develop the source code for encoders and decoders by using VHDL/VERILOG and obtain the simulation, synthesis, place and route and implement into FPGA. ENCODER LOGIC DIAGRAM TRUTH TABLE D 0 1 0 0 0 0 0 0 0 : D1 0 1 0 0 0 0 0 0 D2 0 0 1 0 0 0 0 0 D3 0 0 0 1 0 0 0 0 D4 0 0 0 0 1 0 0 0 D5 0 0 0 0 0 1 0 0 D6 0 0 0 0 0 0 1 0 D7 0 0 0 0 0 0 0 1 X Y Z 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1

VHDL SOURCE CODE Dataflow Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity encoder_dataflow is Port ( d : in std_logic_vector(7 downto 0); z : out std_logic_vector(2 downto 0)); end encoder_dataflow; architecture dataflow of encoder_dataflow is begin z(2)<= d(4) or d(5) or d(6) or d(7); z(1)<= d(2) or d(3) or d(6) or d(7); z(0)<= d(1) or d(3) or d(5) or d(7); end dataflow; Behavioral Modeling:

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library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity encoder_behv is Port ( d : in std_logic_vector(7 downto 0); e : in std_logic; z : out std_logic_vector(2 downto 0)); end encoder_behv; architecture Behavioral of encoder_behv is begin p1:process(d,e) begin if (e='1') then case d is when "10000000"=>z<="000"; when "01000000"=>z<="001"; when "00100000"=>z<="010"; when "00010000"=>z<="011"; when "00001000"=>z<="100"; when "00000100"=>z<="101"; when "00000010"=>z<="110"; when "00000001"=>z<="111"; when others=>z<="ZZZ"; end case; else z<="XXX"; end if; end process p1; end Behavioral; Structural Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity encoder_struct is Port ( d : in std_logic_vector(7 downto 0); z : out std_logic_vector(2 downto 0)); end encoder_struct; architecture structural of encoder_struct is component or4 port(a,b,c,d:in std_logic; z:out std_logic); end component; begin o1:or4 port map (d(4),d(5),d(6),d(7),z(0)); o2:or4 port map (d(2),d(3),d(6),d(7),z(1)); o3:or4 port map (d(1),d(3),d(5),d(7),z(2)); end structural; or4 component source code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

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entity or4 is Port ( a : in std_logic; b : in std_logic; c : in std_logic; d : in std_logic; z : out std_logic); end or4; architecture dataflow of or4 is begin z<=a or b or c or d; end dataflow; DECODERS: LOGIC DIAGRAM: A 0 0 1 1 B 0 1 0 1 TRUTH TABLE: C 1 1 1 1 Z(0) 0 1 1 1 Z(1) 1 0 1 1 Z(2) 1 1 0 1 Z(3) 1 1 1 0

VHDL SOURCE CODE: Dataflow Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity decoder_dataflow is Port ( a : in std_logic; b : in std_logic; e : in std_logic; z : out std_logic_vector(3 downto 0)); end decoder_dataflow; architecture dataflow of decoder_dataflow is signal abar,bbar:std_logic; begin abar<= not a; bbar<= not b; z(0)<= not (abar and bbar and e); z(1)<= not (abar and b and e); z(2)<= not (a and bbar and e); z(3)<= not (a and b and e); end dataflow; Behavioral Modeling: library IEEE;

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use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity decoder_behv is Port ( a : in std_logic; b : in std_logic; e : in std_logic; z : out std_logic_vector(3 downto 0)); end decoder_behv; architecture Behavioral of decoder_behv is begin p1:process(a,b) begin if (e='1') then z(0)<= not a and not b ; z(1)<= not a and b; z(2)<= a and not b; z(3)<= a and b; else z<="1111"; end if; end process p1; end Behavioral; Structural Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity decoder_struct is Port ( a : in std_logic; b : in std_logic; e : in std_logic; z : out std_logic_vector(3 downto 0)); end decoder_struct; architecture structural of decoder_struct is component nand3 port(a,b,c:in std_logic; z:out std_logic); end component; component not1 port(a:in std_logic; z:out std_logic); end component; signal abar,bbar:std_logic; begin n1:not1 port map (a,abar); n2:not1 port map (b,bbar); a1:nand3 port map (abar,bbar,e,z(0)); a2:nand3 port map (abar,b,e,z(1)); a3:nand3 port map (a,bbar,e,z(2)); a4:nand3 port map (a,b,e,z(3)); end structural; nand3 component source code: library IEEE;

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use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity nand3 is Port ( a : in std_logic; b : in std_logic; c : in std_logic; z : out std_logic); end nand3; architecture dataflow of nand3 is begin z<= not (a and b and c); end dataflow; not1 component source code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity not1 is Port ( a : in std_logic; z : out std_logic); end not1; architecture dataflow of not1 is begin z<= not a; end dataflow;

RESULT: Thus the OUTPUTs of Encoder and Decoder are verified by synthesizing and simulating the VHDL and VERILOG code.

EXP NO: 04 MULTIPLEXER AND DEMULTIPLEXER AIM

DATE:

To develop the source code for multiplexer and demultiplexer by using VHDL/VERILOG and obtain the simulation, synthesis, place and route and implement into FPGA. MULTIPLEXER:

Page 24

LOGIC DIAGRAM: TRUTH TABLE:

D 1

9 2 3 4 5 9 1

D 2

1 2 8

D 3

1 2 8

SELECT INPUT S1 S0 0 0 0 1 1 0 1 1

OUTPUT Y D0 D1 D2 D3

S 1

S 0

VHDL SOURCE CODE: Dataflow Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity mux_dataflow is Port ( d : in std_logic_vector(3 downto 0); s : in std_logic_vector(1 downto 0); y : out std_logic); end mux_dataflow; architecture dataflow of mux_dataflow is signal s0bar,s1bar,p,q,r,st:std_logic; begin p<= d(0) and s0bar and s1bar; q<= d(1) and s0bar and s(1); r<= d(2) and s(0) and s1bar; st<= d(3) and s(0) and s(1); s0bar<= not s(0); s1bar<= not s(1); y<= p or q or r or st; end dataflow; Behavioral Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity mux_behv is Port ( d : in std_logic_vector(3 downto 0); s : in std_logic_vector(1 downto 0); y : out std_logic); end mux_behv; architecture Behavioral of mux_behv is begin p1:process(d,s) begin if (s(0)<='0' and s(1)<='0') then y<=d(0); elsif (s(0)<='0' and s(1)<='1') then y<=d(1); elsif (s(0)<='1' and s(1)<='0') then y<=d(2);

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else y<=d(3); end if; end process p1; end Behavioral; Structural Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity mux_struct is Port ( d : in std_logic_vector(3 downto 0); s : in std_logic_vector(1 downto 0); y : out std_logic); end mux_struct; architecture structural of mux_struct is component not1 port(a:in std_logic; z:out std_logic); end component; component and3 port(a,b,c:in std_logic; z:out std_logic); end component; component or4 port(a,b,c,d:in std_logic; z:out std_logic); end component; signal s0bar,s1bar,p,q,r,st:std_logic; begin n1:not1 port map (s(0),s0bar); n2:not1 port map (s(1),s1bar); a1:and3 port map (d(0),s0bar,s1bar,p); a2:and3 port map (d(1),s0bar,s(1),q); a3:and3 port map (d(2),s(0),s1bar,r); a4:and3 port map (d(3),s(0),s(1),st); o1:or4 port map (p,q,r,st,y); end structural;

and3 component source code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity and3 is Port ( a : in std_logic; b : in std_logic; c : in std_logic; z : out std_logic); end and3; architecture dataflow of and3 is begin z<=a and b and c; end dataflow;

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not1 component source code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity not1 is Port ( a : in std_logic; z : out std_logic); end not1; architecture dataflow of not1 is begin z<= not a; end dataflow; or4 component source code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity or4 is Port ( a : in std_logic; b : in std_logic; c : in std_logic; d : in std_logic; z : out std_logic); end or4; architecture dataflow of or4 is begin z<=a or b or c or d; end dataflow; DEMULTIPLEXER: LOGIC DIAGRAM:
S 1 S 0

` TRUTH TABLE: INPUT S0 0 0 1 1 OUTPUT Y1 Y2 0 0 1 0 0 1 0 0

D i n

2 3 4 5 2 3 4 5 2 3 4 5 2 3 4 5 1 1

D 1 1 1 1
Y 0

S1 0 1 0 1

Y0 1 0 0 0

Y3 0 0 0 1

Y 1

Y 2

Y 3

E n a b l e

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VHDL SOURCE CODE: Dataflow Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity demux_dataflow is Port ( d : in std_logic; s : in std_logic_vector(1 downto 0); z : out std_logic_vector(3 downto 0)); end demux_dataflow; architecture dataflow of demux_dataflow is signal s0bar,s1bar:std_logic; begin s0bar<= not s(0); s1bar<= not s(1); z(0)<=d and s0bar and s1bar; z(1)<=d and s0bar and s(1); z(2)<=d and s(0) and s1bar; z(3)<=d and s(0) and s(1); end dataflow; Behavioral Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity demux_behv is Port ( d : in std_logic; s : in std_logic_vector(1 downto 0); z : out std_logic_vector(3 downto 0)); end demux_behv; architecture Behavioral of demux_behv is begin p1:process(d,s) begin if (s(0)<='0' and s(1)<='0') then z(0)<=d; z(1)<='Z'; z(2)<='Z'; z(3)<='Z'; elsif (s(0)<='0' and s(1)<='1') then z(0)<='Z'; z(1)<=d; z(2)<='Z'; z(3)<='Z'; elsif (s(0)<='1' and s(1)<='0') then z(0)<='Z'; z(1)<='Z'; z(2)<=d; z(3)<='Z'; else z(0)<='Z';

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z(1)<='Z'; z(2)<='Z'; z(3)<=d; end if; end process p1; end Behavioral; Structural Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity demux_struct is Port ( d : in std_logic; s : in std_logic_vector(1 downto 0); z : out std_logic_vector(3 downto 0)); end demux_struct; architecture structural of demux_struct is component not1 port(a:in std_logic; z:out std_logic); end component; component and3 port(a,b,c:in std_logic; z:out std_logic); end component; signal s0bar,s1bar:std_logic; begin n1:not1 port map (s(0),s0bar); n2:not1 port map (s(1),s1bar); a1:and3 port map (d,s0bar,s1bar,z(0)); a2:and3 port map (d,s0bar,s(1),z(1)); a3:and3 port map (d,s(0),s1bar,z(2)); a4:and3 port map (d,s(0),s(1),z(3)); end structural; and3 component source code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity and3 is Port ( a : in std_logic; b : in std_logic; c : in std_logic; z : out std_logic); end and3; architecture dataflow of and3 is begin z<=a and b and c; end dataflow; not1 component source code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

Page 29

entity not1 is Port ( a : in std_logic; z : out std_logic); end not1; architecture dataflow of not1 is begin z<= not a; end dataflow;

RESULT: Thus the OUTPUTs of Multiplexers and Demultiplexers are verified by synthesizing and simulating the VHDL and VERILOG code.

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EXP NO: 05 CODE CONVERTERS AND COMPARATOR AIM:

DATE:

To develop the source code for code converters and comparator by using VHDL/VERILOG and obtained the simulation, synthesis, place and route and implement into FPGA. CODE CONVERTER (BCD TO GRAY): LOGIC DIAGRAM:

BCD 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 TRUTH TABLE:

GRAY 0000 0001 0011 0010 0110 0111 0101 0100 1100 1101

VHDL SOURCE CODE: Dataflow Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity b2g_dataflow is Port ( b : in std_logic_vector(3 downto 0); g : out std_logic_vector(3 downto 0)); end b2g_dataflow; architecture dataflow of b2g_dataflow is begin g(0)<=b(0) xor b(1); g(1)<=b(1) xor b(2); g(2)<=b(2) xor b(3); g(3)<=b(3); end dataflow; Behavioral Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity b2g_behv is Port ( b : in std_logic_vector(3 downto 0); g : out std_logic_vector(3 downto 0)); end b2g_behv;

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architecture Behavioral of b2g_behv is begin p1:process(b) begin g(3)<=b(3); g(2)<=b(3) xor b(2); g(1)<=b(2) xor b(1); g(0)<=b(1) xor b(0); end process p1; end Behavioral; Structural Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity b2g_struct is Port ( b : in std_logic_vector(3 downto 0); g : out std_logic_vector(3 downto 0)); end b2g_struct; architecture structural of b2g_struct is component xor2 port(a,b:in std_logic; z:out std_logic); end component; component not1 port(a:in std_logic; z:out std_logic); end component; signal p:std_logic; begin x1:xor2 port map (b(0),b(1),g(0)); x2:xor2 port map (b(1),b(2),g(1)); x3:xor2 port map (b(2),b(3),g(2)); n1:not1 port map (b(3),p); n2:not1 port map (p,g(3)); end structural; not1 component source code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity not1 is Port ( a : in std_logic; z : out std_logic); end not1; architecture dataflow of not1 is begin z<= not a; end dataflow; xor2 component source code: library IEEE;

Page 32

use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity xor2 is Port ( a : in std_logic; b : in std_logic; z : out std_logic); end xor2; architecture dataflow of xor2 is begin z<= a xor b; end dataflow;

CODE CONVERTER (BCD TO EXCESS 3): LOGIC DIAGRAM:

BCD 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001

EXCESS 3 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100

TRUTH TABLE: BCD EXCESS 3

VHDL SOURCE CODE: Dataflow Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity bcd2excess_data is Port ( b : in std_logic_vector(3 downto 0); e : out std_logic_vector(3 downto 0)); end bcd2excess_data; architecture dataflow of bcd2excess_data is signal b0bar,b1bar,b2bar,b3bar,p,q,r,s,t : std_logic; begin b0bar<=not b(0); b1bar<=not b(1); b2bar<=not b(2); b3bar<=not b(3); e(0)<= b0bar ; e(1)<= b(0) xnor b(1); p<=b1bar and b0bar; q<=p and b(2); r<= b(0) or b(1); s<= r and b2bar; e(2)<= q or s; t<= r and b(2); e(3)<= t or b(3);

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end dataflow; Behavioral Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity bcd2excess_behv is Port ( b : in std_logic_vector(3 downto 0); e : out std_logic_vector(3 downto 0)); end bcd2excess_behv; architecture Behavioral of bcd2excess_behv is begin process(b) begin e<=b+"0011"; end process; end Behavioral; Structural Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity bcd2excess_struct is Port ( b : in std_logic_vector(3 downto 0); e : out std_logic_vector(3 downto 0)); end bcd2excess_struct; architecture structural of bcd2excess_struct is component not1 is port(a:in std_logic;z:out std_logic); end component; component and2 is port(a,b:in std_logic;z:out std_logic); end component; component or2 is port(a,b:in std_logic;z:out std_logic); end component; component xnor2 is port(a,b:in std_logic;z:out std_logic); end component; signal b0bar,b1bar,b2bar,b3bar,p,q,r,s,t:std_logic; begin n1:not1 port map(b(0),b0bar); n2:not1 port map(b(1),b1bar); n3:not1 port map(b(2),b2bar); n4:not1 port map(b(3),b3bar); e(0)<=b0bar; x1:xnor2 port map (b(0),b(1),e(1)); a1:and2 port map (b0bar,b1bar,p); a2:and2 port map (b(2),p,q); o1:or2 port map(b(0),b(1),r); a3:and2 port map(r,b2bar,s); o2:or2 port map (q,s,e(2)); a4:and2 port map (r,b(2),t); o3:or2 port map(b(3),t,e(3)); end structural;

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4 BIT COMPARATOR: LOGIC DIAGRAM:

VHDL SOURCE CODE: --Design --Description --Author --Reg no --Version : 4-BIT COMPARATOR : To implement 4-BIT COMPARATOR : V.RAJAN : 2882629 : Xilinx- 7.1i

Behavioral Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity comparator_behv is Port ( a : in std_logic_vector(3 downto 0); b : in std_logic_vector(3 downto 0); x : out std_logic; y : out std_logic; z : out std_logic); end comparator_behv; architecture Behavioral of comparator_behv is begin p1:process(a,b) begin if (a<b) then x<='1'; y<='0'; z<='0'; elsif (a=b) then x<='0'; y<='1'; z<='0'; else x<='0'; y<='0'; z<='1'; end if; end process p1; end Behavioral; RESULT: Thus the OUTPUTs of Code converters and comparator are verified by synthesizing and simulating the VHDL and VERILOG code.

Page 35

EXP NO: 06 FLIP FLOPS AIM:

DATE:

To develop the source code for flip flops by using VHDL/VERILOG and Obtained the simulation, synthesis, place and route and implement into FPGA. SR FLIPFLOP: LOGIC DIAGRAM: TRUTH TABLE:

1 2

Q(t)
3 1 2 3

S 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1

Q(t+1) 0 0 1 X 1 0 1 X

C P
1 1 3 2 3

0 0 0 0 1 1 1 1

VHDL SOURCE CODE: Behavioral Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity srff is Port ( s : in std_logic; r : in std_logic; clk : in std_logic; rst : in std_logic; q : inout std_logic; qbar : inout std_logic); end srff; architecture Behavioral of srff is begin process(s,r,clk,rst,q,qbar) begin if (rst='1') then q<='0'; qbar<='1'; elsif (clk='1' and clk'event) then if (s='0' and r='0') then q<=q; qbar<=qbar; elsif (s='0' and r='1') then q<='0'; qbar<='1'; elsif (s='1' and r='0') then q<='1'; qbar<='0'; else q<='X'; qbar<='X'; end if;

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end if; end process; end Behavioral; JK FLIPFLOP: LOGIC DIAGRAM:

TRUTH TABLE: Q(t) J 0 0 1 1 0 0 1 1 K 0 1 0 1 0 1 0 1 Q(t+1) 0 0 1 1 1 0 1 0

1 2

C P
1 1 2 8 3

0 0 0 0 1 1 1 1

VHDL SOURCE CODE: Behavioral Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity jkff is Port ( j : in std_logic; k : in std_logic; clk : in std_logic; rst : in std_logic; q : inout std_logic; qbar : inout std_logic); end jkff; architecture Behavioral of jkff is begin process(j,k,clk,rst,q,qbar) begin if (rst='1') then q<='0'; qbar<='1'; elsif (clk='1' and clk'event) then if (j='0' and k='0') then q<=q; qbar<=qbar; elsif (j='0' and k='1') then q<='0'; qbar<='1'; elsif (j='1' and k='0') then q<='1'; qbar<='0'; else q<=not q; qbar<=not qbar; end if; end if; end process; end Behavioral;

Page 37

D FLIPFLOP: LOGIC DIAGRAM:

TRUTH TABLE:
Q

Q(t) 0 0 1 1

D 0 1 0 1

Q(t+1) 0 1 0 1

C P
1 1 3 2 3 2 3

VHDL SOURCE CODE: --Design --Description --Author --Reg no --Version : D-FLIP FLOP : To implement D-FLIP FLOP : V.RAJAN : 2882629 : Xilinx- 7.1i

Behavioral Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity dff is Port ( d : in std_logic; clk : in std_logic; rst : in std_logic; q : inout std_logic; qbar : inout std_logic); end dff; architecture Behavioral of dff is begin process(d,clk,rst,q,qbar) begin if (rst='1') then q<='0'; qbar<='1'; elsif (clk='1' and clk'event) then if (d='0') then q<='0'; qbar<='1'; else q<='1'; qbar<='0'; end if; end if; end process; end Behavioral;

T FLIPFLOP:

Page 38

LOGIC DIAGRAM:
1 2 8

TRUTH TABLE: Q(t) T 0 1 0 1 Q(t+1) 0 1 1 0

1 2

C P
1 2 8 1 9 2 3

VHDL SOURCE CODE: --

0 0 1 1

Behavioral Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity tff is Port ( t : in std_logic; clk : in std_logic; rst : in std_logic; q : inout std_logic; qbar : inout std_logic); end tff; architecture Behavioral of tff is begin process(t,clk,rst,q,qbar) begin if (rst='1') then q<='0'; qbar<='1'; elsif (clk='1' and clk'event) then if (t='0') then q<=q; qbar<=qbar; else q<=not q; qbar<=not qbar; end if; end if; end process; end Behavioral;

MASTER-SLAVE SR FLIP-FLOP: LOGIC DIAGRAM:

Page 39

VHDL SOURCE CODE: Structural Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity sr_ms is Port ( s : in std_logic; r : in std_logic; clk : in std_logic; rst : in std_logic; q : inout std_logic; qbar : inout std_logic); end sr_ms; architecture structural of sr_ms is component srff Port ( s : in std_logic; r : in std_logic; clk : in std_logic; rst : in std_logic; q : inout std_logic; qbar : inout std_logic); end component; component not1 port(a:in std_logic; z:out std_logic); end component; signal clkbar,s1,r1:std_logic; begin n1:not1 port map (clk,clkbar); sr1:srff port map (s,r,clk,rst,s1,r1); sr2:srff port map (s1,r1,clkbar,rst,q,qbar); end structural; srff component source code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity srff is

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Port ( s : in std_logic; r : in std_logic; clk : in std_logic; rst : in std_logic; q : inout std_logic; qbar : inout std_logic); end srff; architecture Behavioral of srff is begin process(s,r,clk,rst,q,qbar) begin if (rst='1') then q<='0'; qbar<='1'; elsif (clk='1' and clk'event) then if (s='0' and r='0') then q<=q; qbar<=qbar; elsif (s='0' and r='1') then q<='0'; qbar<='1'; elsif (s='1' and r='0') then q<='1'; qbar<='0'; else q<='X'; qbar<='X'; end if; end if; end process; end Behavioral;

RESULT: Thus the OUTPUTs of Flip Flops are verified by synthesizing and simulating the VHDL and VERILOG code.

EXP NO: 07 REGISTER USING LATCHES AND FLIP FLOPS

DATE:

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AIM: To develop the source code for register and latches using flip-flops by using VHDL/VERILOG and Obtained the simulation, synthesis, place and route and implement into FPGA. REGISTER USING FLIP FLOPS: LOGIC DIAGRAM:

VHDL SOURCE CODE: Behavioral Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity reguff is Port ( d : in std_logic_vector(7 downto 0); clk : in std_logic; rst : in std_logic; q : inout std_logic_vector(7 downto 0); qbar : inout std_logic_vector(7 downto 0)); end reguff; architecture Behavioral of reguff is begin process(d,clk,rst) begin if (clk='1' and clk'event) then if (rst='1') then q<="00000000"; qbar<="11111111"; else q<=d; qbar<=not d; end if; end if; end process; end Behavioral; REGISTER USING LATCHES: LOGIC DIAGRAM:

VHDL SOURCE CODE: Behavioral Modeling:

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library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity regulat is Port ( d : in std_logic_vector(7 downto 0); rst : in std_logic; en : in std_logic; q : inout std_logic_vector(7 downto 0); qbar : inout std_logic_vector(7 downto 0)); end regulat; architecture Behavioral of regulat is begin process(d,rst,en) begin if (rst='1') then q<="00000000"; qbar<="11111111"; elsif (en='1') then q<=d; qbar<=not d; end if; end process; end Behavioral; RESULT: Thus the OUTPUTs of 8-bit register using flip flops and latches are verified by synthesizing and simulating the VHDL and VERILOG code.

EXP NO: 08 SHIFT REGISTERS

DATE:

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AIM: To develop the source code for shifters unit by using VHDL/VERILOG and obtain the simulation, synthesis, place and route and implement into FPGA. SERIAL-IN SERIAL-OUT SHIFT REGISTER: LOGIC DIAGRAM :

VHDL SOURCE CODE: Behavioral Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity siso is Port ( d : in std_logic; clk : in std_logic; rst : in std_logic; q : out std_logic); end siso; architecture Behavioral of siso is signal x:std_logic_vector(7 downto 0); begin process(d,clk,rst) begin if (rst='1') then q<='X'; elsif (clk='1' and clk'event) then x(0)<=d; x(1)<=x(0); x(2)<=x(1); x(3)<=x(2); x(4)<=x(3); x(5)<=x(4); x(6)<=x(5); x(7)<=x(6); q<=x(7); end if; end process; end Behavioral;

SERIAL IN PARALLEL OUT SHIFT REGISTER: LOGIC DIAGRAM :

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VHDL SOURCE CODE: Behavioral Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity sipo is Port ( d : in std_logic; clk : in std_logic; rst : in std_logic; q : inout std_logic_vector(7 downto 0)); end sipo; architecture Behavioral of sipo is begin process(d,clk,rst) begin if (rst='1') then q<="ZZZZZZZZ"; elsif (clk='1' and clk'event) then q(0)<=d; q(1)<=q(0); q(2)<=q(1); q(3)<=q(2); q(4)<=q(3); q(5)<=q(4); q(6)<=q(5); q(7)<=q(6); end if; end process; end Behavioral;

PARALLEL-IN PARELLEL-OUT SHIFT REGISTER: LOGIC DIAGRAM :

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VHDL SOURCE CODE: Behavioral Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity pipo is Port ( d : in std_logic_vector(7 downto 0); clk : in std_logic; rst : in std_logic; q : out std_logic_vector(7 downto 0)); end pipo; architecture Behavioral of pipo is begin process(d,clk,rst) begin if (rst='1') then q<="ZZZZZZZZ"; elsif (clk='1' and clk'event) then q(0)<=d(0); q(1)<=d(1); q(2)<=d(2); q(3)<=d(3); q(4)<=d(4); q(5)<=d(5); q(6)<=d(6); q(7)<=d(7); end if; end process; end Behavioral; PARALLEL-IN SERIAL-OUT SHIFT REGISTER: LOGIC DIAGRAM :

VHDL SOURCE CODE: Behavioral Modeling:

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library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity piso is Port ( d : in std_logic_vector(7 downto 0); clk : in std_logic; rst : in std_logic; load : in std_logic; q : out std_logic); end piso; architecture Behavioral of piso is begin process(d,clk,rst,load) variable x:std_logic_vector(7 downto 0); begin if (clk='1' and clk'event) then if (rst='1') then q<='Z'; else if (load='0') then x:=d; else q<=x(0); x(0):=x(1); x(1):=x(2); x(2):=x(3); x(3):=x(4); x(4):=x(5); x(5):=x(6); x(6):=x(7); x(7):='Z'; end if; end if; end if; end process; end Behavioral; RESULT: Thus the OUTPUTs of 8-bit shift register are verified by synthesizing and simulating the VHDL and VERILOG code.

EXP NO: 09 SYNCHRONOUS AND ASYNCHRONOUS COUNTER

DATE:

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AIM: To develop the source code for synchronous and asynchronous counter by using VHDL/VERILOG and obtain the simulation, synthesis, place and route and implement into FPGA. SYNCHRONOUS COUNTER: LOGIC DIAGRAM:

VHDL SOURCE CODE: Structural Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity syncounter is Port ( clk : in std_logic; rst : in std_logic; q : inout std_logic_vector(3 downto 0)); end syncounter; architecture structural of syncounter is component tff port(t,clk,rst:in std_logic; q,qbar:inout std_logic); end component; component and2 port(a,b:in std_logic; z:out std_logic); end component; signal x1,x2:std_logic; signal x3,x4,x5,x6:std_logic:='Z'; begin t1:tff port map ('1',clk,rst,q(0),x3); t2:tff port map (q(0),clk,rst,q(1),x4); t3:tff port map (x1,clk,rst,q(2),x5); t4:tff port map (x2,clk,rst,q(3),x6); a1:and2 port map (q(0),q(1),x1); a2:and2 port map (x1,q(2),x2); end structural; tff component source code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity tff is Port ( t : in std_logic;

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clk : in std_logic; rst : in std_logic; q : inout std_logic; qbar : inout std_logic); end tff; architecture Behavioral of tff is begin process(t,clk,rst,q,qbar) begin if (rst='1') then q<='0'; qbar<='1'; elsif (clk='1' and clk'event) then if (t='0') then q<=q; qbar<=qbar; else q<=not q; qbar<=not qbar; end if; end if; end process; end Behavioral; and2 component source code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity and2 is Port ( a : in std_logic; b : in std_logic; z : out std_logic); end and2; architecture dataflow of and2 is begin z<=a and b; end dataflow; ASYNCHRONOUS COUNTER: LOGIC DIAGRAM:

VHDL SOURCE CODE: Structural Modeling:

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library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity asyncounter is Port ( clk : in std_logic; rst : in std_logic; q : inout std_logic_vector(3 downto 0)); end asyncounter; architecture structural of asyncounter is component tff port(t,clk,rst:in std_logic; q,qbar:inout std_logic); end component; signal x1,x2,x3:std_logic; signal x4:std_logic:='Z'; begin t1:tff port map ('1',clk,rst,q(0),x1); t2:tff port map ('1',x1,rst,q(1),x2); t3:tff port map ('1',x2,rst,q(2),x3); t4:tff port map ('1',x3,rst,q(3),x4); end structural; tff component source code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity tff is Port ( t : in std_logic; clk : in std_logic; rst : in std_logic; q : inout std_logic; qbar : inout std_logic); end tff; architecture Behavioral of tff is begin process(t,clk,rst,q,qbar) begin if (rst='1') then q<='0'; qbar<='1'; elsif (clk='1' and clk'event) then if (t='0') then q<=q; qbar<=qbar; else q<=not q; qbar<=not qbar; end if; end if; end process; end Behavioral; RESULT: Thus the OUTPUTs of Synchronous and Asynchronous counter are verified by synthesizing and simulating the VHDL and VERILOG code. EXP NO: 10 DATE: ARITHMETIC AND LOGIC UNIT

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AIM: To develop the source code for arithmetic and logic unit by using VHDL/VERILOG and obtain the simulation, synthesis, place and route and implement into FPGA. LOGIC DIAGRAM:

TRUTH TABLE:

VHDL SOUCE CODE --Design : ALU --Description : To implement ALU --Author : V.RAJAN --Roll no : 2882629 --Version : Xilinx- 7.1i Structural Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity alu is Port ( a : in std_logic_vector(7 downto 0); b : in std_logic_vector(7 downto 0); c : in std_logic; s : in std_logic_vector(3 downto 0);

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y : out std_logic_vector(7 downto 0)); end alu; architecture structural of alu is component arith port(a,b:in std_logic_vector(7 downto 0); c:in std_logic; s:in std_logic_vector(2 downto 0); x:out std_logic_vector(7 downto 0)); end component; component logic port(a,b:in std_logic_vector(7 downto 0); s:in std_logic_vector(2 downto 0); x:out std_logic_vector(7 downto 0)); end component; component mux1 port(a,b:in std_logic_vector(7 downto 0); s:in std_logic; x:out std_logic_vector(7 downto 0)); end component; signal x1,x2:std_logic_vector(7 downto 0); begin a1:arith port map (a(7 downto 0),b(7 downto 0),c,s(2 downto 0),x1(7 downto 0)); l1:logic port map (a(7 downto 0),b(7 downto 0),s(2 downto 0),x2(7 downto 0)); m1:mux1 port map (x1(7 downto 0),x2(7 downto 0),s(3),y(7 downto 0)); end structural; arith component source code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity arith is Port ( a : in std_logic_vector(7 downto 0); b : in std_logic_vector(7 downto 0); c : in std_logic; s : in std_logic_vector(2 downto 0); x : out std_logic_vector(7 downto 0)); end arith; architecture Behavioral of arith is begin process(a,b,c,s) begin case s is when "000" => x <= a; when "001" => x <= a+1; when "010" => x <= a-1; when "011" => x <= b; when "100" => x <= b+1; when "101" => x <= b-1; when "110" => x <= a+b; when others => x <= a+b+c; end case; end process; end Behavioral; logic component source code: library IEEE;

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use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity logic is Port ( a : in std_logic_vector(7 downto 0); b : in std_logic_vector(7 downto 0); s : in std_logic_vector(2 downto 0); x : out std_logic_vector(7 downto 0)); end logic; architecture Behavioral of logic is begin process(a,b,s) begin case s is when "000" => x <= not a; when "001" => x <= not b; when "010" => x <= a and b; when "011" => x <= a nand b; when "100" => x <= a or b; when "101" => x <= a nor b; when "110" => x <= a xor b; when others => x <= a xnor b; end case; end process; end Behavioral; mux1 component source code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity mux1 is Port ( a : in std_logic_vector(7 downto 0); b : in std_logic_vector(7 downto 0); s : in std_logic; x : out std_logic_vector(7 downto 0)); end mux1; architecture Behavioral of mux1 is begin process(a,b,s) begin if (s='0') then x<=a; else x<=b; end if; end process; end Behavioral; RESULT: Thus the OUTPUTs of Arithmetic Logic Unit are verified by synthesizing and simulating the VHDL and VERILOG code.

EXP NO: 12 BARREL SHIFTER

DATE:

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AIM: To develop the source code for barrel shifter by using VHDL/VERILOG and obtain the simulation, synthesis, place and route and implement into FPGA. LOGICAL DIAGRAM:

VHDL SOUCE CODE Behavioral Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity bar_shftr is generic ( n : positive := 7 ); Port ( data : in std_logic_vector(n-1 downto 0); sel : in integer range 0 to n-1; bar_out : out std_logic_vector(n-1 downto 0)); end bar_shftr; architecture Behavioral of bar_shftr is begin process(sel,data) variable var_buf : std_logic_vector(n-1 downto 0); begin var_buf:=data; for k in 1 to sel loop var_buf:=var_buf(n-2 downto 0) & var_buf(n-1); end loop; bar_out<=var_buf; end process; end Behavioral; RESULT: Thus the OUTPUTs of Barrel Shifter are verified by synthesizing and simulating the VHDL and VERILOG code.

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