ASIC Verification
Course Overview
Fall 2011 Meeta Yadav
2011, Meeta Yadav
Course Overview
This course covers the verification process used in validating the functional correctness in today's complex Application Specific Integrated Circuits (ASICs). Topics include fundamentals of simulation based functional verification, stimulus generation, results checking, coverage, debug, and assertions. Provides the students with real world verification problems to allow them to apply what they learn.
Instructor
Dr. Meeta Yadav
Email: myadav@[Link] Office hours: 4:00 to 5:00 Fridays, 3:00 to 4:00 Thursday (DE)
TAS
TBD
Prerequisite
ECE 520 ASIC Design or equivalent. A good working knowledge of Verilog or VHDL is essential. This is not suitable as a first course in a hardware description language.
2011, Meeta Yadav
What is ASIC Verification?
2011, Meeta Yadav
Design Complexity Increasing
Communication
Entertainment
Broadcasting
Computing
Telematics
Image Processing
Location-Based Services
Designs are becoming more complex as more functionality is added to them
2011, Meeta Yadav
Increase in Transistors Per Die
Increased functionality increases the number of transistors in the design thus increasing the possibility of error in the design
2011, Meeta Yadav
Increase in Design Bugs
50% of ASICs require more than one respin
75% of them have logical or functional bugs
[Collet 2005]
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Solution is:
ASIC Verification
Functional Verification Formal Verification
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ASIC Verification is:
1. Making sure there are no bugs in the design
2. All design functionality has been implemented
2011, Meeta Yadav
What will you learn in this class?
To develop a Verification Plan
What to Verify? How to Verify it?
OOP
Develop a reusable testbench
VMM Methodology
Write Assertions
Think Get close to the bug
When am I done?
Perform Coverage
Close the gap
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Testbench Development
Testbench functionality
Generate stimulus Apply stimulus to the Design Under Test (DUT)
Stimulus Generation
Stimulus Application
Design Under Test
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Testbench Development
Testbench functionality
Generate stimulus Apply stimulus to the Design Under Test (DUT) Capture the response Check for correctnessA
Stimulus Generation
Stimulus Application
Design Under Test
Response Capture
Correctness Check
Golden Model
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Testbench Development
Testbench functionality
Generate stimulus Apply stimulus to the Design Under Test (DUT) Capture the response Check for correctness Measure the progress against the overall verification goals
Progress Check and Control of Verification Process
Stimulus Generation
Stimulus Application
Design Under Test
Response Capture
Correctness Check
Golden Model
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Testbench Development
Testbench functionality
Generate stimulus Apply stimulus to the Design Under Test (DUT) Capture the response Check for correctness Measure the progress against the overall verification goals
Progress Check and Control of Verification Process
Stimulus Generation
Assertions Stimulus Application Design Under Test Response Capture
Correctness Check
Golden Model
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Language and Tools
SystemVerilog
QuestaSim
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Course Overview
Topics
1. 2. 3. 4. 5. 5. 6. 7. Introduction to Verification Test Bench Environments Interfaces Stimulus Generation Object Oriented Programming Functional Coverage Assertions SystemVerilog Language Constructs
[Link]
Text
C. Spear, System Verilog for Verification, Springer 2006 or most recent
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Course Overview
Evaluation
Labs Midterm 15% 15% There will be 5 labs The exam will be open book and open notes
Project
50%
Verification of an LC3 microprocessor by developing a reusable test environment using SystemVerilog, and gathering functional coverage metrics. Students will be required to find embedded bugs and validate them against a list provided and report functional coverage numbers.
The exam will be comprehensive and open books and open notes.
Final
20%
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Project
Perform Functional Verification on pipelined LC3 microprocessor using a reusable testbench Validate the bug list Perform coverage Demo: Detect bug in the design in 1 hour, analyze the bug
Progress Check and Control of Verification Process
Stimulus Generation
Golden Model Assertions Correctness Check
Stimulus Application
Design Under Test
Response Capture
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References
Comprehensive functional verification the complete industry cycle by Bruce Wile, John C. Goss, Wolfgang Roesner. Elsevier/Morgan Kaufmann, c2005 SystemVerilog for Verification: A Guide to Learning the Testbench Language Features by Chris Spear. Springer, 2006 or most recent
SystemVerilog for Design: A Guide to Using SystemVerilog for Hardware Design and Modeling by Stuart Sutherland, Simon Davidman, Peter Flake and P. Moorby. Springer, 2006
Verification Methodology Manual for SystemVerilog by Janick Bergeron, Eduard Cerny, Alan Hunter, Andy Nightingale. Springer, 2005 SystemVerilog Assertions Handbook by Ben Cohen, S Venkataramananm, A Kumari. VhdlCohen Publishing, 2005. SystemVerilog 3.1a , Language Reference Manual Accelleras Extensions to Verilog
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Chances of you doing Verification in the industry if you stay in this field?
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Designers are doing Verification
Source: 2004/2002 IC/ASIC Functional Verification Study, Collett International Research, Used with Permission
Very High
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Thank You
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