ROMs Using Block RAM Resources
XST can use block RAM resources to implement ROMs with synchronous outputs or address
inputs. These ROMs are implement as single-port block RAMs. The use of block RAM
resources to implement ROMs is controlled by the ROM_STYLE constraint. Please see
"Design Constraints" chapter for details about the ROM_SYTLE attribute. Please see "FPGA
Optimization" chapter for details on ROM implementation.
Here is a list of VHDL/Verilog templates described below.
ROM with registered output
ROM with registered address
The following table shows pin descriptions for a registered ROM.
IO Pins Description
clk
Positive-Edge Clock
en
Synchronous Enable (active High)
addr
Read Address
data
Data Output
VHDL Code
Following is the recommended VHDL code for a ROM with registered output.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity rominfr is
port (
clk : in std_logic;
en
: in std_logic;
addr : in std_logic_vector(4 downto 0);
data : out std_logic_vector(3 downto 0));
end rominfr;
architecture syn of rominfr is
type rom_type is array (31 downto 0) of std_logic_vector (3 downto 0);
constant ROM : rom_type :=(
"0001","0010","0011","0100","0101","0110","0111","1000","1001",
"1010","1011","1100","1101","1110","1111","0001","0010","0011",
"0100","0101","0110","0111","1000","1001","1010","1011","1100",
"1101","1110","1111");
begin
process (clk)
begin
if (clk'event and clk = '1') then
if (en = '1') then
data <= ROM(conv_integer(addr);
end if;
end if;
end process;
end syn;
Following is alternate VHDL code for a ROM with registered output.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity rominfr is
port (
clk : in std_logic;
en
: in std_logic;
addr : in std_logic_vector(4 downto 0);
data : out std_logic_vector(3 downto 0));
end rominfr;
architecture syn of rominfr is
type rom_type is array (31 downto 0) of std_logic_vector (3 downto 0);
constant ROM : rom_type :=(
"0001","0010","0011","0100","0101","0110","0111","1000","1001",
"1010","1011","1100","1101","1110","1111","0001","0010","0011",
"0100","0101","0110","0111","1000","1001","1010","1011","1100",
"1101","1110","1111");
signal rdata : std_logic_vector(3 downto 0);
begin
rdata <= ROM(conv_integer(addr));
process (clk)
begin
if (clk'event and clk = '1') then
if (en = '1') then
data <= rdata;
end if;
end if;
end process;
end syn;
Following is VHDL code for a ROM with registered address.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity rominfr is
port (
clk : in std_logic;
en
: in std_logic;
addr : in std_logic_vector(4 downto 0);
data : out std_logic_vector(3 downto 0));
end rominfr;
architecture syn of rominfr is
type rom_type is array (31 downto 0) of std_logic_vector (3 downto 0);
constant ROM : rom_type :=
("0001","0010","0011","0100","0101","0110","0111","1000","1001","1010" ,"10
11","1100","1101","1110","1111","0001","0010","0011","0100","0101" ,"0110",
"0111","1000","1001","1010","1011","1100","1101","1110","1111"
);
signal raddr : std_logic_vector(4 downto 0);
begin
process (clk)
begin
if (clk'event and clk = '1') then
if (en = '1') then
raddr <= addr;
end if;
end if;
end process;
data <= ROM(conv_integer(raddr));
end syn;
