Prepared by:
Manish Arutla CEA304
Babu C. Laxmanan CEA306
Akhil Reghunathan CEA301
Nilesh Jamdade CEA319
CPU Performs
• Computer’s data processing functions
• Jump, Skip
• Stores and Retrieves Insructions
• Stores and Retrieves Data
CPU Architecture
• 1 ALU
“arith. logic unit”
Circuits perform arith. & logic
• 2 Control Unit
Fetches from memory decodes
instructions tells system
execute instructions
• 3 Address Registers
Store addresses
PC: Program Counter to hold address of
next instruction to be fetched
MBR: Memory Buffer Register for
value to be read/written from/to
memory
IR: Instruction Register to contain
opcode of the last Instruction
CPU Architecture
• 4 Accumulator
Register(s)
Accumulates bits swapped
in and out of the ALU.
• 5 Shifter
Stores, carries and rotates
results
CPU Architecture
• 6 Program Counter
Register
Contains the address of the next
instruction to be fetched and executed.
The program counter is then
incremented and the next processing
cycle begins.
• 7 Stack Pointer
Register
Keeps track of the STACK.
• Control Path
• responsible for instruction fetch and
execution sequencing
• responsible for operand fetch
• responsible for saving results
CPU Architecture
• 8 STACK • The Processing Cycle
Register(s) (simplified)
• The Stack is not part of the CPU it
is part of memory. • Fetch the next instruction
• The pull operation results in a
transfer of the word at the top of • Decode instruction
the stack into the accumulator.
• The push operation puts a word on
• Execute instruction
the stack. The final accumulator
contents are deposited on top of the
• Increment counter
stack.
• The Stack Pointer keeps track of
what’s next on the stack. First word
at the bottom.
Instruction Cycle
•The processing required for single operation is called
instruction cycle
• Once started, a computer continuously performs the following:
1. Fetch next instruction from memory
2. Decode the instruction
3. Execute the instruction
• Special purpose registers used
1. PC: Program Counter to hold address of next instruction
to be fetched
2. MBR: Memory Buffer Register for value to be read/written
from/to memory
3. IR: Instruction Register to contain opcode of the last Instruction
Basic Instruction Cycle
Memory
Fetching
Execution
CPU
Fetch Cycle
Address Line
Data Line
PC
PC++ Memory
IR MBR
Memory Buffer Register
Execute Cycle
Execute a simple instruction: Load A, 1234H
Address Line
Data Line
IR Memory
A MBR
Basic Instruction Cycle (contd.)
Begin
Begin
Fetch Cycle
Fetch
FetchNext
Next
Instruction
Instruction
Decode Cycle Decode
Decode
Instruction
Instruction
Execute
Execute
Instruction
Instruction
Execute Cycle
Layout of bits in an instruction
Includes opcode
Includes (implicit or explicit) operand(s)
Usually more than one instruction
format in an instruction set
•In selecting the instruction format(s) the
following factors should be considered.
1.The number of instructions to be represented.
2. The addressability and addressing modes.
3. The ease of decoding.
4. Type of instruction field (fixed or variable)
5. The cost of hardware required to decode
and execute instructions.
•The main instruction is function of an:
1.Specify an operation to be performed on data.
2.Specify the operand / data to be used.
The operands specify input data, memory location
etc.
•The operation & operands are include in an
instruction by specific field in instruction word.
•These specific fields are divided into two parts:
1)Opcode
2)Operand
Opcode
•The opcode field is used to specify
the operation to be performed.
Operand
•The operand field is used to
specify the add. of the operands in
main memory or in processor.
Basic Instruction Format
Opcode Register 1 Index Register Memory Address
0 89 12 14 17 18 35
Instruction Addressing
The way in which ‘Data’ or ‘Address’ of data
specified in the instruction is called “Instruction
Addressing”.
The various addressing modes are:
1. Immediate Addressing
2. Register Addressing
3. Direct Addressing
4. Register Indirect Addressing
5. Register Relative Addressing
6. Implicit Addressing
Immediate Addressing
Operand(Data) is part of instruction
In this addressing data required for instruction
computation is immediately available within the
instruction itself.
e.g. ADD 5
◦ Add 5 to contents of accumulator
◦ 5 is operand
No memory reference to fetch data
Fast
Limited range
Instruction
Data
Register Addressing
Operand(Data) is held in register named in address
field
In this addressing data required for instruction
computation is in the register which is specified in
instruction. i.e register addresses data.
Limited number of registers
Very small address field needed
◦ Shorter instructions
◦ Faster instruction fetch
Instruction Register
Register Data
Direct Addressing
Address field contains address of operand(Data)
In this addressing data required for instruction
computation is in the memory location whose effective
address(EA) is directly specified in the instruction.
e.g. ADD A
◦ Add contents of cell A to accumulator
◦ Look in memory at address A for operand
Single memory reference to access data
Limited address space
Instruction Memory
Address Data
Register Indirect Addressing
In this addressing data required for instruction is in
memory location whose EA is in register pair which is
specified in the instruction.
i.e. Register pair indirectly points to the data in the
memory.
Large address space (2n)
One fewer memory access than indirect addressing
Instruction Register Pair Memory
Register Pair Address Data
Register Relative Addressing
In this addressing data required for instruction
computation is in the memory location whose
EA is calculated by adding base address from
the register pair specified in the instruction
with relative displacement.
locality of reference & cache usage
Register Pair Relative
Displacement
+ Data
Base Address
Implicit Addressing
Implicit addressing also called as implied
addressing or inherent addressing.
In this Addressing ,Processor implies that
content of accumulator should be operated by an
instruction
Accumulator
Data
