Scribd
Upload
87 views6 pages

2-Bit Up-Down Counter Design Guide

This document describes a 2-bit up-down counter and its truth table. It then discusses Mealy and Moore machines, including their differences in how outputs are determined. Finally, it provides an example of designing a finite state machine for a coin-operated vending machine.

Uploaded by

amarsdd7238
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
87 views6 pages

2-Bit Up-Down Counter Design Guide

This document describes a 2-bit up-down counter and its truth table. It then discusses Mealy and Moore machines, including their differences in how outputs are determined. Finally, it provides an example of designing a finite state machine for a coin-operated vending machine.

Uploaded by

amarsdd7238
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

CSE 561 Sequential Circuits

1
2-bit up-down counter (2 inputs)
direction: D = 0 for up, D = 1 for down
count: C = 0 for hold, C = 1 for count



S1 S0 C D N1 N0
0 0 0 0 0 0
0 0 0 1 0 0
0 0 1 0 0 1
0 0 1 1 1 1
0 1 0 0 0 1
0 1 0 1 0 1
0 1 1 0 1 0
0 1 1 1 0 0
1 0 0 0 1 0
1 0 0 1 1 0
1 0 1 0 1 1
1 0 1 1 0 1
1 1 0 0 1 1
1 1 0 1 1 1
1 1 1 0 0 0
1 1 1 1 1 0

0
1
0
0
1
1
1
0
C=0
D=X
C=0
D=X
C=0
D=X
C=0
D=X
C=1
D=0
C=1
D=0
C=1
D=0
C=1
D=0
C=1
D=1
N1 = CS1
+ CDS0S1 + CDS0S1
+ CDS0S1 + CDS0S1
= CS1
+ C(D(S1 S0) + D(S1 S0))
N0 = CS0 + CS0
0 1 1 0
0 1 1 0
1 0 0 1
1 0 0 1
D
S1
S0
C
0 1 1 0
0 1 1 0
1 0 0 1
1 0 0 1
D
S1
S0
C
0 1 1 0
0 1 1 0
1 0 0 1
1 0 0 1
D
S1
S0
C
0 0 1 1
0 0 1 1
1 0 1 0
0 1 0 1
D
S1
S0
C
0 0 1 1
0 0 1 1
1 0 1 0
0 1 0 1
D
S1
S0
C
0 0 1 1
0 0 1 1
1 0 1 0
0 1 0 1
D
S1
S0
C

CSE 561 Sequential Circuits
2
Mealy machines tend to have less states
different outputs on arcs (n2) rather than states (n)
Moore machines are safer to use
outputs change at clock edge (always one cycle later)
in Mealy machines, input change can cause output change as soon as logic is done
a big problem when two machines are interconnected asynchronous feedback may
occur if one isnt careful
Mealy machines react faster to inputs
react in same cycle don't need to wait for clock
in Moore machines, more logic may be necessary to decode state into outputs
more gate delays after clock edge





state feedback
inputs
outputs reg
combinational
logic for
next state logic for
outputs
inputs outputs
state feedback
reg
combinational
logic for
next state
logic for
outputs
inputs outputs
state feedback
reg
combinational
logic for
next state
logic for
outputs
CSE 561 Sequential Circuits
3
Example: vending machine
Release item after 15 cents are deposited
Single coin slot for dimes, nickels
No change
Suitable abstract representation
tabulate typical input sequences:
3 nickels; nickel, dime; dime, nickel; two dimes
draw state diagram:
inputs: N, D, reset; output: open chute
assumptions:
assume N and D asserted for one cycle
each state has a self loop for N = D = 0 (no coin)

Vending
Machine
FSM
N
D
Reset
Clock
Open
Coin
Sensor
Release
Mechanism
Vending
Machine
FSM
N
D
Reset
Clock
Open
Coin
Sensor
Release
Mechanism


PS IN NS OUT
D N open
0 0 0 0 0
0 1 5 0
1 0 10 0
1 1
5 0 0 5 0
0 1 10 0
1 0 15 0
1 1
10 0 0 10 0
0 1 15 0
1 0 15 0
1 1
15 15 1
0
Reset
5
N
N
N + D
10
D
15
[open]
D
0
Reset
0
Reset
5
N
5
N
NN
N + D N + D
10
D
10
D
15
[open]
D
15
[open]
DD

0 0 1 1
0 1 1 1
X X 1 X
1 1 1 1
Q1
D1
Q0
N
D
0 1 1 0
1 0 1 1
X X 1 X
0 1 1 1
Q1
D0
Q0
N
D
0 0 1 0
0 0 1 0
X X 1 X
0 0 1 0
Q1
Open
Q0
N
D
0 0 1 1
0 1 1 1
X X 1 X
1 1 1 1
Q1
D1
Q0
N
D
0 0 1 1
0 1 1 1
X X 1 X
1 1 1 1
Q1
D1
Q0
N
D
0 1 1 0
1 0 1 1
X X 1 X
0 1 1 1
Q1
D0
Q0
N
D
0 1 1 0
1 0 1 1
X X 1 X
0 1 1 1
Q1
D0
Q0
N
D
0 0 1 0
0 0 1 0
X X 1 X
0 0 1 0
Q1
Open
Q0
N
D
0 0 1 0
0 0 1 0
X X 1 X
0 0 1 0
Q1
Open
Q0
N
D

0 0 1 1
0 1 1 1
X X 1 X
1 1 1 1
Q1
D1
Q0
N
D
0 1 1 0
1 0 1 1
X X 1 X
0 1 1 1
Q1
D0
Q0
N
D
0 0 1 0
0 0 1 0
X X 1 X
0 0 1 0
Q1
Open
Q0
N
D
0 0 1 1
0 1 1 1
X X 1 X
1 1 1 1
Q1
D1
Q0
N
D
0 0 1 1
0 1 1 1
X X 1 X
1 1 1 1
Q1
D1
Q0
N
D
0 1 1 0
1 0 1 1
X X 1 X
0 1 1 1
Q1
D0
Q0
N
D
0 1 1 0
1 0 1 1
X X 1 X
0 1 1 1
Q1
D0
Q0
N
D
0 0 1 0
0 0 1 0
X X 1 X
0 0 1 0
Q1
Open
Q0
N
D
0 0 1 0
0 0 1 0
X X 1 X
0 0 1 0
Q1
Open
Q0
N
D


S0
Reset
S2
D
S6
[open]
D
S4
[open]
D
S1
N
S3
N
S5
[open]
N
S8
[open]
D
S7
[open]
N
S0
Reset
S0
Reset
S2
D
S2
D
S6
[open]
D
S6
[open]
D
S4
[open]
D
S4
[open]
D
S1
N
S1
N
S3
N
S3
N
S5
[open]
N
S5
[open]
N
S8
[open]
D
S8
[open]
D
S7
[open]
N
S7
[open]
N

D1 = Q1 + D + Q0 N
D0 = Q0 N + Q0 N + Q1 N + Q1 D
OPEN = Q1 Q0
CSE 561 Sequential Circuits
4


0
10
5
15
Reset/0
D/0
D/1
N/0
N+D/1
N/0
N D/0
Reset/1
N D/0
N D/0
Reset/0
0
10
5
15
Reset/0
D/0
D/1
N/0
N+D/1
N/0
N D/0
Reset/1
N D/0
N D/0
Reset/0





OPEN is 0 when reset (by adding AND gate)
PS IN NS OUT
Q1 Q0 D N D1 D0 open
0 0 0 0 0 0 0
0 1 0 1 0
1 0 1 0 0
1 1
0 1 0 0 0 1 0
0 1 1 0 0
1 0 1 1 1
1 1
1 0 0 0 1 0 0
0 1 1 1 1
1 0 1 1 1
1 1
1 1 1 1 1
D0 = Q0N + Q0N + Q1N + Q1D
D1 = Q1 + D + Q0N
OPEN = Q1Q0 + Q1N + Q1D + Q0D
0 0 1 0
0 0 1 1
X X 1 X
0 1 1 1
Q1
Open
Q0
N
D
0 0 1 0
0 0 1 1
X X 1 X
0 1 1 1
Q1
Open
Q0
N
D
0 0 1 0
0 0 1 1
X X 1 X
0 1 1 1
Q1
Open
Q0
N
D

CSE 561 Sequential Circuits
5
Recognize A, B = 0, 1


Recognize A, B = 1, 0 then 0, 1



D Q
Q
B
A
clock
out
D Q
Q
D Q
Q
clock
out
A
B
B
A
out
D Q
Q
D Q
Q
D Q
Q
D Q
Q
A
B
clock
out
D Q
Q
D Q
Q
A
B
clock
out
CSE 561 Sequential Circuits
6
Remove one 1 from every string of 1s on the input

1
0
0
0
1
1
zero
[0]
one1
[0]
two1s
[1]
1
0
0
0
1
1
zero
[0]
one1
[0]
two1s
[1]
1/0
0/0
0/0
1/1
zero
[0]
one1
[0]
1/0
0/0
0/0
1/1
zero
[0]
one1
[0]

You might also like