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ReducingCongestionWithICCompiler

ReducingCongestionWithICCompiler
DocId:020963Product:ICCompilerLastModified:08/05/2008

ReducingCongestionWithICCompiler
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yourdesignsarecongestedatdifferentlocationswithdifferentseverity.
Thisdocumentdescribeshowtosolvecongestionissues.
DivideandConquerApproach
Thedivideandconquerapproachresolvescongestionstepbystepanddoesnot
[Link]
bemoretimeconsuming,[Link]
solveafewproblemsatthesametime,forexample,ahighutilizationissue,
adatapathstructureissue,[Link]
interdependentorinfluential,sosolvingthoseproblemsmightimprove
[Link]
aftereachsuccessfulexperimentalstage.
Youshouldneitheroptimize(usingplace_optorpsynopt)norexplorecongestion
[Link],itmightbeuseful
tosegmentouttheproblematichierarchy(byusinggroupingcommandsinDesign
Compiler/DesignCompilertopographicalmode)andgeneratetheexpectedfloorplan
(byusingminimumphysicalconstraintoptions);thenworkstandaloneuntilyou
getthebestresults.
AvoidVeryHighUtilization
ThefirststepofdesignoptimizationinICCompilerisdonewithathinnetlist.
Thismeansthatthenetlistdoesnotcontainelementstobeaddedlaterin
theflowsuchasclocktreebuffers,holdfixingcells(buffers),[Link]
[Link]
dependsoneachdesign,[Link]
[Link]
cases,[Link],itisrecommendedthatyouavoid
[Link],takethe
followingactionstoeliminatepotentialproblemsresultedbyroutingcongestion
and/orinsufficientplacementarea:
[Link](bothtiminganddesignrulechecking).An
optimizeddesignthatcontainsmanylargecellsandbufferscouldindicatebad
[Link]:
check_timing
report_timing_requirementsignored
[Link].
DesignCompiler:compilearea_efforthigh[inc]
ICCompiler:psynoptarea_recoveryarea_efforthigh[only_area_recovery]
ICCompiler:place_optarea_recovery
Settingphysopt_ultra_high_area_efforttotrueadverselyimpactsthedesign
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areawhenusedwithplace_optarea_recoveryeffortmediumorplace_opt
area_recoveryefforthigh.
Reducingthenumberofcellsinthedesignorevenspecifyingafewsubblocks
toreducethenumberofcells,[Link]
repeatingthisstepforeachstageintheflow(itmightcauselongerruntime),the
[Link]
becomesyourstartingpoint.
CongestionHotSpotsandBlockTiming
[Link]
canhaveverytighttiminganddesignrulechecking(DRC)constraints,especiallya
[Link],the
tighttimingiscausedbytimingandDRCconstraintpropagationfromthetoplevel.
[Link]
constraints,applyadifferentDRCortimingconstrainttotheblock.
Youcanalsotryothertechniquessuchasusingcaseanalysis,settingfalse
pathormulticyclepathconstraints,addinginputdelaytotheassociatedclock,
orconstrainingtheports.
AutomaticCongestionHandling
IfyouwantICCompilertoresolvecongestionautomatically,followthebelow
steps.
SettheCongestionOptions
Forbestresults,youshouldproviderealisticnumbersfortherouting
[Link],metal1ismostlyusedforcell
buildingandpowerandoftenhaslimitedavailabilityforrouting.
Tospecifytheroutingavailabilityforalayer,usethefollowingcommand:
set_congestion_optionslayer<layer>availability<percentage>\
coordinate[get_placement_area]
Thesesettingsaffectcongestionoptimizationandreporting.
ChecktheResults
Somelocationsinthedesignareexpectedtobecongestediftheyarenotwell
[Link]
inthe"FloorplanDrivenProblems"sectionthatfollows.
ViewtheASCIIcongestionreportgeneratedbythereport_congestioncommand.
YoucanalsoviewcongestioninformationintheGUI.
UsethecongestionOption
[Link]
defaultbehaviorthattheplacerminimizeswirelength(thedefault)oroptimizes
pathlocationtomeettiming,thegoalofthealgorithmsistoreducecongestion.
Thealgorithmsareinvokedbyusingthecongestion*optionwiththepsynopt,
place_opt,create_placement,orrefine_placementcommandduringplacementstage.
Twoprimaryconcernswhenusingthecongestionremovalalgorithmsare:
[Link],socongestionremovalalgorithmsshouldbeinvoked
onlywhenneeded.
[Link].
Whenusingthecreate_placementandrefine_placementcommands,youcancontrol
thecongestioneffort.Thecongestion_effortoptiondetermineshowmucheffort
[Link]
[Link],settingthe
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congestionefforttohighcausesalongerruntime.
Therecommendedwayofusingcongestionoptionsisasfollows:
MediumThemaximumroutingcongestionmightbegreaterthan100percent,
[Link]
largecomparedwiththeoverallfloorplansizeanddonotformlarge
masses.
HighThemaximumcongestionismuchhigherthan100percentandthe
[Link].
timing_drivencongestionTotradeoffbetweencongestionandtiming,
invokethetiming_drivenandcongestionoptions.Thetooltriesto
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congestioncostfunctionsarefullyrecognizedatallpointscangreatlybenefit
designswithbothtimingandcongestionproblems.
UseGlobalRouteBasedCongestion
Indifficultcases,youmightwanttouseamoreaccuratecongestioncalculation
basedonglobalroute.Thedefaultreport_congestioncommandisbasedonatradeoff
[Link]
mightnotdiffermuch,[Link]:
route_globalcongestion_map_only
UsetheHighEffortCongestionAlgorithm
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algorithm,settheplacer_enable_high_effort_congestionvariabletotruebefore
yourunplace_optcongestionorpsynoptcongestion.Whenyouenablethe
higheffortcongestionalgorithm,ICCompilerdoesaverydetailed
congestiondrivenplacementandgeneratesalogasfollows:
100%done.
69%...75%...81%...88%...94%...69%...75%...81%...88%...94%...100%done.
[begininitializingdataforlegalitychecker]
Performingthepsynoptcongestionoptimizationwithoutthehigheffortcongestion
algorithmgivesyouthefollowinglog:
100%done.
69%...75%...81%...88%...94%...100%done.
FloorplanDrivenProblems
Thissectiondiscussesfloorplandrivenproblemssuchaschannels,macros,
powergrids,andportlocationchanges.
Channels(Slivers,Tunnels)CausingCongestionProblems
Achannelisdefinedastherouting(placement)areabetweenmacrosorthe
[Link]
[Link],congestioncanappear
attheinternaledgeoftheblockage,[Link]
worstcasescenariohappenswhenthepinsofonemacroareplacedinthesame
[Link]
isthatportsarelocatedattheendofthechannel.
Inadenselypackeddesign,alargenumberofcompleteblockagesmightcause
insufficientplacementareatoplacethedesign.

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ChannelPlanning
Createchannelswideenoughtoaccommodateallrouting,powerrings(ifany),
andthebusexpansionareaoutsidethemacrospinssothatnetscangoacross
[Link],useonlynecessary
widthforchannelroutingtosavearea.
MacroTreatment
Macroplacement(ororientation)shouldminimizetheinterconnectbetween
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iftheyareconnectedtothesamebus,thepinsshouldalignrespectivelyeven
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busesandmorethantworoutinglayersareavailable,pinalignmentisstill
recommended.
PowerGrid(Mesh)
Apowergridsuppliespowertoallchipcomponents(transistors).IRdrop
(voltagedrop)alongthepowersupplylinecancausethebasiccomponentsof
thedesign,thetransistors,[Link]
ringcontainingallthepadsincludingpowerpadsthatarelocatedatthechip
boundaries,someareas(especiallyinthecenterornearareasthataremasked
frompowerrouting)mightnotgetthevoltagelevelneededtofunctionproperly.
Toavoidthisproblem,youcandesignaveryrobustgridtoencompassthechip.
WhenyoucannotmeetthegoalsofIRdropusingasinglelayerperdirectionor
thetopmetalwiththesmallestresistance,youcandesignagridwithtwoor
[Link],anextensiveuseofroutingresourcesor
placingmetalinanondefaultpowergridmetaldirectionmightcreateadesign
thatisnotroutable.
AnalyzingthePowerPlan
Powerplanningisderivedfromchiplevelfloorplanning,soyourinitial
[Link]
[Link]
suchasJupiterXTpowernetworkanalysisandAstroRailshouldbeusedto
verifythatagridisrobustenoughbutdoesnotwasteroutingresources.
UseJupiterXTpowernetworksynthesisandpowerpadsynthesistohelpyou
createamoreefficientpowerplan.
NonoptimizedTrackUse
Inmanycases,apowergridisspreadevenlyacrossthewholechipregardless
[Link]
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losingroutingresources,adjustboththepowerstrapwidthanddistancebetween
strapsalongthegrid.
DifferentWidthsInsideaSpecificBlock
Becauseapowerstrapwidthisspecifiedforthepowersupplyoftheentire
chipregardlessofthedistancefromapowerpad,thepowerstraphasthesame
[Link],considerthinningorremovingafew
powerstraps(afterconsultingwithyourpowerplandesigner)andanalyzethe
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theblocklooksfine,addingapowerringaroundthisblockmighthelp.
NondefaultViaRules
Thedefaultbehaviorofapowergridroutingisspecifiedbyputtingavia
[Link]
[Link]
[Link],ifmetal#3and
metal#5arededicatedtoverticaldirection,andmetal#4andmetal#6are
dedicatedtohorizontaldirection,astackviabetweenmetal#3andmetal#5uses
metal#[Link],[Link]
beachievedbyputtingmoreeffortinthestripesdesignstep;thatis,keepthe
verticallayerlowerthanthehorizontaltoavoidunconnectedpowerstraps.
UseseparatestepsforviasbyselectingtheaxgCreatePrerouteContactsmenuand
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theaxgPrerouteStandardCellsmenuAdvanceViaRulesdialogbox.
PortLocationChanges
Thissectiondescribessomecongestionproblemsdrivenfromportlocations.
Forthepurposesofthisdocument,itisassumedthatyoudon'thavefullcontrol
overportlocationsandsidesattheblocklevel.
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[Link](including
wirelengthandtiming)placebothinputcellsandportisolationcellsand
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[Link]
[Link],ifthere
arestrongcellsinthelibrarythatcansupportDRCandoutputdelaysversus
clockrates,outputportscanbewithinacertaindistancefromtheports.
Manyportsthatarecondensedwithinasmallportionofthedesignareamight
conflictwithreasonablecellplacement,especiallythosecellswithdirect
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portsasmuchaspossible.
RoutingBottlenecks
Anotherissueistheroutingbottleneckwhereyouhavemanyroutingsegments
withalimitedamountoflayersandyoutrytofollowbackenddesignrulesto
[Link]
[Link]
[Link]
[Link],usea
progressiveblockageapproach.
LimitedChannels
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(boththeareabetweenafewmacrosandthedistancebetweenmacrosanddesign
borders)istoosmall,eventotheamountofroutingthatshouldpassthrough
it,[Link]
therearealimitednumberoflayers,especiallyintechnologieswherethere
[Link],noblockagecanbeused,
[Link]
planningstage.
BlockLevelFloorplanAdjustments
Youcanusethefollowingblocklevelfloorplanadjustmentstoimprovecongestion.
LocalUtilization
OnemethodyoucanusewithICCompilertoimprovecongestionislocalutilization.
[Link]
locatingabottleneck,youcancontroltheamountofcellsbydefininglocal
utilizationbypercentage.
Usethefollowingcommandtoimplementlocalutilization:
set_congestion_optionscoordinate{}max_util0.X
Thissolutioncanbeusedinseveralplacesinablock,andyoucanspecify
[Link]
themax_utilvalueshouldbelessthan1.[Link],
[Link],
usinglocalutilizationtoimprovecongestioncanleadtofurtheradjustments.
NondefaultDirectionRouting
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[Link]
macromanufacturersallowyoutoroutewithmetalsthatarehigherthanmetal#5
[Link]
[Link],thismetalroutingdirectionisopposite
[Link],youcansolvesomeofthe
congestionproblemsusingcreate_route_guideorchooseFlourplan>Create
RouteGuideintheGUI.
create_route_guideswitch_preferred_direction
BoundingorGroupingSubblocksWithoutCongestionOptions
Sometimesyoumightwanttoputspecificsubdesignsorsubblockseither
togetherorwithinaspecificplaceinadesignprimarilytosolvetiming
[Link],whichcanbeusedtosolve
[Link]
approachisasfollows.(Usedifferentnumbersforeachsubblock.)

create_boundsnamebound1coordinate{}efforthigh|ultratype\
hard[get_cellscell_list1]
create_boundsnamebound2coordinate{}efforthigh|ultratype\
hard[get_cellscell_list2]

Thesolutionhasonerestrictionthattoomanyboundscanslowdownthe
[Link]
areaistoolarge,movingothercellsintothespacesinsidetheboundcauses
[Link],thisapproachwon'tbehonored.
Afterinspection,[Link],
resultscanbecomemuchworse.
CombiningBoundingSubblocksWithLocalUtilization(WithCongestionOptions)
Whenyouinspectlocalutilizationusage,determineiftheplacercanputa
[Link]
agroupofcellshasalocalutilizationrestrictionandtheplacerputsthe
groupsomewhereelse,theeffortisnotsuccessfulbecausecongestion
remainsandtimingisadverselyimpacted.
Youcanforcecellstogroupinaspecificlocationandtoutilizelocally
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toimplementthisapproachareasfollows:

create_boundsnamebound1coordinate{X1Y1X2Y2}efforthigh\
typehard[get_cellscell_list1]
set_congestion_optionscoordinate{X1Y1X2Y2}max_util0.X
create_placementtiming(orrefine_placement)
Therestrictionforthissolutionisthattoomanyboundscanslowdownthe
[Link]
[Link],othercellscanjumpintothespaces
[Link],the
utilizationwon'[Link],determineifthegroupingis
timingbased.Cellsthatgetstuckinthecornerorsideviolatethemax_util
valuewhilesomeoftheboundingarearemainsempty.
StrategicKeepouts

Thissolutionputsplacementblockagesinareaswithveryhighcongestion.
Afterallocatingthebottleneck,youcancontroltheamountofcellsbydefining
[Link],ICCompilerhassomekeepoutareasaround
[Link]
[Link]
onthethresholdyoudefineandgeneratesblockagesoverthehighlycongested
[Link],iftheutilizationislimited,theoptimizationmight
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latertrytoputthecellsinotherplacessothatthecongestioncanmove
toalessrestrictedarea.
AnExampleofUsingScripttoGenerateStrategicKeepouts
#CustomerControl#
setrun_num1
setcongestion_threshold1.3
setcon_placement_typehard
#ScriptBody
redirectvarcongested_area{get_congested_regionsthreshold\
$congestion_threshold}
setcongestion_vector[split[lindex$congested_area[expr[llength\
$congested_area]2]]","]
foreachi$congestion_vector{\
setsbn"[stringtrim[lindex[split$i""]0]\{][lindex\
[split$i""]1]";\
create_placement_blockagetype$con_placement_typecoordinat\
[list[stringtrim[lindex[split$i""]0]\{]\
[lindex[split$i""]1][lindex[split$i""]2]\
[stringtrim[lindex[split$i""]3]\}]]\
nameconblckg$run_num$sbn
}
ForMoreInformation:
SeealsotheSNUGIsrael2006userpaper(C4):"TheCongestionDragonCan
[Link]."

2015Synopsys,[Link].

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