Memory Organization

Computer Organization and Assembly Language

Computer Science Department

National University of Computer and Emerging Sciences

Islamabad

Memory Organization Computer Organization and Assembly Language – NUCES Hina Anwar – slide 1
 Memory Hierarchy
2
‰Main Memory
¾Only programs and data currently needed by the
processor
‰Auxiliary Memory
¾Devices that provide backup storage
¾System programs, large data files etc
¾E.g. magnetic disks and tapes
‰Cache
¾Increases the speed of processing
¾Rapid rate and small size
¾Compensates speed difference between main
memory and processor
¾Segments of programs and data currently in use
Memory Organization Computer Organization and Assembly Language – NUCES Hina Anwar – slide 2
 Memory Hierarchy
3

‰Total memory capacity can be visualized as hierarchy of

components
‰Slow to fast
‰High capacity to smaller capacity

Memory Organization Computer Organization and Assembly Language – NUCES Hina Anwar – slide 3
 Memory Hierarchy 
4

Magnetic tapes Main Memory

I/O processor

Magnetic disks

Cache Memory
CPU

Memory Organization Computer Organization and Assembly Language – NUCES Hina Anwar – slide 4
 Hierarchy List
5

‰Registers
‰L1 Cache
‰L2 Cache
‰Main memory
‰Disk cache
‰Disk
‰Optical
‰Tape

Memory Organization Computer Organization and Assembly Language – NUCES Hina Anwar – slide 5
 Main Memory
6
‰Central storage unit
‰Large and fast memory to store programs and data during
the computer operation
‰RAM
¾Random access memory
¾Volatile
¾Stores programs and data that are subject to
change
¾Read/write memory
‰ROM
¾Read only memory
¾Non-volatile
¾Stores tables of constant data that do not change
Memory Organization Computer Organization and Assembly Language – NUCES Hina Anwar – slide 6
 Main Memory
7

‰Bootstrap loader
¾Startup program
¾Stored in ROM
¾Its function is to load the operating system
‰ROM and RAM chips are available in variety of sizes
¾e.g. 128x8

Memory Organization Computer Organization and Assembly Language – NUCES Hina Anwar – slide 7
 RAM chip
8

‰7 bit address bus

‰8 bit data bus
‰Two chip selects Chip Select 1
‰Read control signal Chip Select 2

‰Write control signal Read

128x8 RAM
Write 8-bit data bus

7-bit Address

Memory Organization Computer Organization and Assembly Language – NUCES Hina Anwar – slide 8
 Memory Connection to CPU
9

‰Memory Capacity : 512 bytes of RAM and 512 bytes of

ROM
‰Chips Available : 128x8 RAM
512x8 ROM
‰4 RAMS and 1 ROM
‰Each RAM receives 7 lower bits
‰Particular RAM chip selected is determined by lines 8 and 9
‰Selection between ROM and Ram is done by line 10

Memory Organization Computer Organization and Assembly Language – NUCES Hina Anwar – slide 9
 Memory Connection to CPU
10

‰ CPU

Decoder 128x8
3 2 1 0 RAM 1

128x8
RAM 2

128x8
RAM 3

128x8
RAM 4

512x8
Memory Organization Computer Organization and Assembly Language – NUCES
ROM Hina Anwar – slide 10
 Auxiliary Memory
11

‰Characteristics
¾Access mode
¾Access time
¾Transfer rate
¾Capacity
¾Cost

Memory Organization Computer Organization and Assembly Language – NUCES Hina Anwar – slide 11
 Access Mode
12

‰Sequential
¾Start at the beginning and read through in order
¾Access time depends on location of data and
previous location
¾e.g. tape
‰Direct
¾Individual blocks have unique address
¾Access is by jumping to vicinity plus sequential
search
¾Access time depends on location and previous
location
Memory Organization Computer Organization and Assembly Language – NUCES Hina Anwar – slide 12
¾e.g. disk
 Access Mode
13

‰Random
¾Individual addresses identify locations exactly
¾Access time is independent of location or previous
access
¾e.g. RAM
‰Associative
¾Data is located by a comparison with contents of a
portion of the store
¾Access time is independent of location or previous
access
¾e.g. cache
Memory Organization Computer Organization and Assembly Language – NUCES Hina Anwar – slide 13
 Access Time
14

‰The average time to reach a storage location in memory

and obtain its content
‰Access Time = seek time + transfer time
‰Seek Time
¾Time required to position the read/write head to a
location
‰Transfer Time
¾Time required to transfer data to or from the device

Memory Organization Computer Organization and Assembly Language – NUCES Hina Anwar – slide 14
 Transfer Rate
15

‰Word or bytes transferred at one time

‰For internal memory it is usually governed by data bus
width

Memory Organization Computer Organization and Assembly Language – NUCES Hina Anwar – slide 15
 Locality of Reference
16

‰The references to memory at any given interval of time tend

to be confined with in a few localized areas in memory
‰If the active portions of the program and data are placed in
a fast small memory, the efficiency can be increased
‰Such small fast memory is referred to as cache memory

Memory Organization Computer Organization and Assembly Language – NUCES Hina Anwar – slide 16
 Cache
17

‰Small amount of fast memory

‰Sits between normal main memory and CPU
‰May be located on CPU chip or module
‰Faster than main memory by a factor of 5 to 10

Memory Organization Computer Organization and Assembly Language – NUCES Hina Anwar – slide 17
 Cache operation ‐ overview
18

‰CPU requests contents of memory location

‰Check cache for this data
‰If present, get from cache (fast)
‰If not present, read required block from main memory to
cache
‰Then deliver from cache to CPU
‰Cache includes tags to identify which block of main memory
is in each cache slot

Memory Organization Computer Organization and Assembly Language – NUCES Hina Anwar – slide 18
 Cache Performance
19

‰Hit ratio
¾When CPU refers to memory and finds the word in
cache, it is said to produce a hit
¾If not found, it is called a miss
¾Hit Ratio = Number of hits / Total CPU references
to memory

Memory Organization Computer Organization and Assembly Language – NUCES Hina Anwar – slide 19
 References
20

‰Computer System Architecture by Morris Mano – Chapter

12
‰Computer Organization and Architecture
by William Stallings – Chapter 3

Memory Organization Computer Organization and Assembly Language – NUCES Hina Anwar – slide 20