Lecture 2

Introduction to VHDL
for Synthesis

ECE 545 – Introduction to VHDL George Mason University

 Resources
• Volnei A. Pedroni, Circuit Design with VHDL
Chapter 1, Introduction
Chapter 2, Code Structure
Chapter 3.1, Pre-Defined Data Types

• Sundar Rajan, Essential VHDL: RTL Synthesis

Done Right
Chapter 1, VHDL Fundamentals
Chapter 2, Getting Your First Design Done
(see errata at [Link]
ECE 545 Introduction to VHDL 2
 Brief History of VHDL

ECE 545 Introduction to VHDL 3

VHDL

• VHDL is a language for describing digital

hardware used by industry worldwide

• VHDL is an acronym for VHSIC (Very High

Speed Integrated Circuit) Hardware
Description Language

ECE 545 Introduction to VHDL 4

Genesis of VHDL
State of art circa 1980
• Multiple design entry methods and
hardware description languages in use
• No or limited portability of designs
between CAD tools from different vendors
• Objective: shortening the time from a
design concept to implementation from
18 months to 6 months

ECE 545 Introduction to VHDL 5

A Brief History of VHDL
• June 1981: Woods Hole Workshop
• July 1983: contract awarded to develop VHDL
• Intermetrics
• IBM
• Texas Instruments
• August 1985: VHDL Version 7.2 released
• December 1987:
VHDL became IEEE Standard 1076-1987 and in 1988
an ANSI standard

ECE 545 Introduction to VHDL 6

 Three versions of VHDL

• VHDL-87

• VHDL-93

• VHDL-01

ECE 545 Introduction to VHDL 7

 Examples
• VHDL Example:
process (clk, rstn)
begin
if (rstn = '0') then
q <= '0';
elseif (clk'event and clk =
'1') then
q <= a + b;
end if;
end process;

ECE 545 Introduction to VHDL 8

 VHDL for Synthesis

ECE 545 Introduction to VHDL 9

 VHDL for Specification

VHDL for Simulation

VHDL for Synthesis

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 Levels of design description

Algorithmic level
Level of description
Register Transfer Level
most suitable for synthesis
Logic (gate) level

Circuit (transistor) level

Physical (layout) level

ECE 545 Introduction to VHDL 11

Register Transfer Logic (RTL) Design Description

Combinational
Logic
Combinational
Logic
…

Registers

ECE 545 Introduction to VHDL 12

 VHDL Fundamentals

ECE 545 Introduction to VHDL 13

 Naming and Labeling (1)

• VHDL is not case sensitive

Example:
Names or labels
databus
Databus
DataBus
DATABUS
are all equivalent

ECE 545 Introduction to VHDL 14

 Naming and Labeling (2)
General rules of thumb (according to VHDL-87)

1. All names should start with an alphabet character (a-z

or A-Z)
2. Use only alphabet characters (a-z or A-Z) digits (0-9)
and underscore (_)
3. Do not use any punctuation or reserved characters
within a name (!, ?, ., &, +, -, etc.)
4. Do not use two or more consecutive underscore
characters (__) within a name (e.g., Sel__A is invalid)
5. All names and labels in a given entity and architecture
must be unique

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 Free Format
• VHDL is a “free format” language
No formatting conventions, such as spacing or
indentation imposed by VHDL compilers. Space
and carriage return treated the same way.
Example:
if (a=b) then
or
if (a=b) then
or
if (a =
b) then
are all equivalent

ECE 545 Introduction to VHDL 16

 Readability standards

ESA VHDL Modelling Guidelines

published by
European Space Research and Technology Center
in September 1994

available at the course web page

ECE 545 Introduction to VHDL 17

 Readability standards
Selected issues covered by ESA Guidelines:

• Consistent Writing Style

• Consistent Naming Conventions
• Consistent Indentation
• Consistent Commenting Style
• Recommended File Headers
• File naming and contents
• Number of statements/declarations per line
• Ordering of port and signal declarations
• Constructs to avoid

ECE 545 Introduction to VHDL 18

 Comments
• Comments in VHDL are indicated with
a “double dash”, i.e., “--”
 Comment indicator can be placed anywhere in the
line
 Any text that follows in the same line is treated as
a comment
 Carriage return terminates a comment
 No method for commenting a block extending over
a couple of lines
Examples:
-- main subcircuit
Data_in <= Data_bus; -- reading data from the input FIFO

ECE 545 Introduction to VHDL 19

 Comments

• Explain Function of Module to Other

Designers
• Explanatory, Not Just Restatement of Code
• Locate Close to Code Described
• Put near executable code, not just in a header

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 Design Entity

ECE 545 Introduction to VHDL 21

Design Entity
design entity

entity declaration Design Entity - most basic

building block of a design.

architecture 1
One entity can have
architecture 2 many different architectures.

architecture 3

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Entity Declaration
• Entity Declaration describes the interface of the
component, i.e. input and output ports.

Entity name Port type

Port names
Semicolon

ENTITY nand_gate IS
PORT(
a : IN STD_LOGIC;
b : IN STD_LOGIC;
No Semicolon
z : OUT STD_LOGIC
);
END nand_gate;

Reserved words Port modes (data flow directions)

ECE 545 Introduction to VHDL 23

Entity declaration – simplified syntax

ENTITY entity_name IS
PORT (
port_name : signal_mode signal_type;
port_name : signal_mode signal_type;
………….
port_name : signal_mode signal_type);
END entity_name;

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Architecture

• Describes an implementation of a design

entity.
• Architecture example:

ARCHITECTURE model OF nand_gate IS

BEGIN
z <= a NAND b;
END model;

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Architecture – simplified syntax

ARCHITECTURE architecture_name OF entity_name IS

[ declarations ]
BEGIN
code
END architecture_name;

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Entity Declaration & Architecture
nand_gate.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY nand_gate IS
PORT(
a : IN STD_LOGIC;
b : IN STD_LOGIC;
z : OUT STD_LOGIC);
END nand_gate;

ARCHITECTURE model OF nand_gate IS

BEGIN
z <= a NAND b;
END model;

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Mode In

Port signal Entity

Driver resides
outside the entity

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Mode out

Entity

Port signal

Can’t read out

c within an entity

Driver resides
inside the entity c <= z

ECE 545 Introduction to VHDL 29

Mode out with signal

Entity

Port signal

x z

c Signal X can be
read inside the entity

Driver resides z <= x

inside the entity
c <= x

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Mode inout

Port signal Entity

Signal can be
read inside the entity

Driver may reside

both inside and outside
of the entity

ECE 545 Introduction to VHDL 31

Mode buffer

Entity

Port signal

c
Port signal Z can be
read inside the entity

Driver resides
c <= z
inside the entity

ECE 545 Introduction to VHDL 32

Port Modes
The Port Mode of the interface describes the direction in which data travels with
respect to the component

• In: Data comes in this port and can only be read within the entity. It can
appear only on the right side of a signal or variable assignment.

• Out: The value of an output port can only be updated within the entity. It
cannot be read. It can only appear on the left side of a signal
assignment.

• Inout: The value of a bi-directional port can be read and updated within
the entity model. It can appear on both sides of a signal assignment.

• Buffer: Used for a signal that is an output from an entity. The value of the
signal can be used inside the entity, which means that in an assignment
statement the signal can appear on the left and right sides of the <=
operator

ECE 545 Introduction to VHDL 33

 Libraries

ECE 545 Introduction to VHDL 34

Library declarations
Library declaration

Use all definitions from the package

LIBRARY ieee; std_logic_1164
USE ieee.std_logic_1164.all;

ENTITY nand_gate IS
PORT(
a : IN STD_LOGIC;
b : IN STD_LOGIC;
z : OUT STD_LOGIC);
END nand_gate;

ARCHITECTURE model OF nand_gate IS

BEGIN
z <= a NAND b;
END model;

ECE 545 Introduction to VHDL 35

Library declarations - syntax

LIBRARY library_name;
USE library_name.package_name.package_parts;

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 Fundamental parts of a library

LIBRARY

PACKAGE 1 PACKAGE 2

TYPES TYPES
CONSTANTS CONSTANTS
FUNCTIONS FUNCTIONS
PROCEDURES PROCEDURES
COMPONENTS COMPONENTS

ECE 545 Introduction to VHDL 37

 Libraries
• ieee Need to be explicitly
Specifies multi-level logic system,
including STD_LOGIC, and declared
STD_LOGIC_VECTOR data types

• std
Specifies pre-defined data types
(BIT, BOOLEAN, INTEGER, REAL,
SIGNED, UNSIGNED, etc.), arithmetic
operations, basic type conversion Visible by default
functions, basic text i/o functions, etc.

• work
Current designs after compilation
ECE 545 Introduction to VHDL 38
 STD_LOGIC Demystified

ECE 545 Introduction to VHDL 39

STD_LOGIC

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY nand_gate IS
PORT(
a : IN STD_LOGIC;
b : IN STD_LOGIC;
z : OUT STD_LOGIC);
END nand_gate;

ARCHITECTURE model OF nand_gate IS

BEGIN
z <= a NAND b;
END model;

What is STD_LOGIC you ask?

ECE 545 Introduction to VHDL 40

STD_LOGIC type demystified
Value Meaning

‘X’ Forcing (Strong driven) Unknown

‘0’ Forcing (Strong driven) 0

‘1’ Forcing (Strong driven) 1

‘Z’ High Impedance

‘W’ Weak (Weakly driven) Unknown

Weak (Weakly driven) 0.

‘L’
Models a pull down.
Weak (Weakly driven) 1.
‘H’
Models a pull up.

‘-’ Don't Care

ECE 545 Introduction to VHDL 41

 Signals
SIGNAL a : STD_LOGIC;

a
1
wire

SIGNAL b : STD_LOGIC_VECTOR(7 DOWNTO 0);

b
8 bus

ECE 545 Introduction to VHDL 42

Standard Logic Vectors
SIGNAL a: STD_LOGIC;
SIGNAL b: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL c: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL d: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL e: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL f: STD_LOGIC_VECTOR(8 DOWNTO 0);
……….
a <= ‘1’;
b <= ”0000”; -- Binary base assumed by default
c <= B”0000”; -- Binary base explicitly specified
d <= ”0110_0111”; -- You can use ‘_’ to increase readability
e <= X”AF67”; -- Hexadecimal base
f <= O”723”; -- Octal base
ECE 545 Introduction to VHDL 43
Vectors and Concatenation

SIGNAL a: STD_LOGIC_VECTOR(3 DOWNTO 0);

SIGNAL b: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL c, d, e: STD_LOGIC_VECTOR(7 DOWNTO 0);

a <= ”0000”;
b <= ”1111”;
c <= a & b; -- c = ”00001111”

d <= ‘0’ & ”0001111”; -- d <= ”00001111”

e <= ‘0’ & ‘0’ & ‘0’ & ‘0’ & ‘1’ & ‘1’ &
‘1’ & ‘1’;
-- e <= ”00001111”

ECE 545 Introduction to VHDL 44

 VHDL Design Styles

ECE 545 Introduction to VHDL 45

VHDL Design Styles

VHDL Design
Styles

dataflow structural behavioral

Concurrent Components and Sequential statements

statements interconnects • Registers
• State machines
• Test benches

Subset most suitable for synthesis

ECE 545 Introduction to VHDL 46

xor3 Example

ECE 545 Introduction to VHDL 47

 Entity xor3

ENTITY xor3 IS
PORT(
A : IN STD_LOGIC;
B : IN STD_LOGIC;
C : IN STD_LOGIC;
Result : OUT STD_LOGIC
);
end xor3;

ECE 545 Introduction to VHDL 48

 Dataflow Architecture (xor3 gate)
ARCHITECTURE dataflow OF xor3 IS
SIGNAL U1_out: STD_LOGIC;
BEGIN
U1_out <=A XOR B;
Result <=U1_out XOR C;
END dataflow;

U1_out

ECE 545 Introduction to VHDL 49

Dataflow Description
• Describes how data moves through the system
and the various processing steps.
• Data Flow uses series of concurrent statements
to realize logic. Concurrent statements are
evaluated at the same time; thus, order of these
statements doesn’t matter.
• Data Flow is most useful style when series of
Boolean equations can represent a logic.

ECE 545 Introduction to VHDL 50

 Structural Architecture (xor3 gate)
ARCHITECTURE structural OF xor3 IS I1
SIGNAL U1_OUT: STD_LOGIC; Y
I2
COMPONENT xor2 IS
PORT( XOR2
I1 : IN STD_LOGIC;
I2 : IN STD_LOGIC;
Y : OUT STD_LOGIC A
); B XOR3 Result
END COMPONENT; C

BEGIN
U1: xor2 PORT MAP (I1 => A,
I2 => B,
U1_OUT
Y => U1_OUT);
A
U2: xor2 PORT MAP (I1 => U1_OUT, B RESULT
I2 => C, C
Y => Result);
END structural;
XOR3

ECE 545 Introduction to VHDL 51

Component and Instantiation (1)

• Named association connectivity

(recommended)
COMPONENT xor2 IS
PORT(
I1 : IN STD_LOGIC;
I2 : IN STD_LOGIC;
Y : OUT STD_LOGIC
);
END COMPONENT;

U1: xor2 PORT MAP (I1 => A,

I2 => B,
Y => U1_OUT);

ECE 545 Introduction to VHDL 52

Component and Instantiation (2)

• Positional association connectivity

(not recommended)

COMPONENT xor2 IS
PORT(
I1 : IN STD_LOGIC;
I2 : IN STD_LOGIC;
Y : OUT STD_LOGIC
);
END COMPONENT;

U1: xor2 PORT MAP (A, B, U1_OUT);

ECE 545 Introduction to VHDL 53

 Structural Description
• Structural design is the simplest to understand.
This style is the closest to schematic capture and
utilizes simple building blocks to compose logic
functions.
• Components are interconnected in a hierarchical
manner.
• Structural descriptions may connect simple gates
or complex, abstract components.
• Structural style is useful when expressing a
design that is naturally composed of sub-blocks.

ECE 545 Introduction to VHDL 54

 Behavioral Architecture (xor3 gate)
ARCHITECTURE behavioral OF xor3 IS
BEGIN
xor3_behave: PROCESS (A,B,C)
BEGIN
IF ((A XOR B XOR C) = '1') THEN
Result <= '1';
ELSE
Result <= '0';
END IF;
END PROCESS xor3_behave;
END behavioral;

ECE 545 Introduction to VHDL 55

Behavioral Description
• It accurately models what happens on the inputs
and outputs of the black box (no matter what is
inside and how it works).
• This style uses PROCESS statements in VHDL.

ECE 545 Introduction to VHDL 56

What is a PROCESS?
• A process is a sequence of instructions referred to as sequential
statements.
The keyword PROCESS

• A process can be given a unique name

Testing: PROCESS
using an optional LABEL
BEGIN
• This is followed by the keyword test_vector<=“00”;
PROCESS WAIT FOR 10 ns;
test_vector<=“01”;
• The keyword BEGIN is used to indicate WAIT FOR 10 ns;
the start of the process test_vector<=“10”;
WAIT FOR 10 ns;
• All statements within the process are test_vector<=“11”;
executed SEQUENTIALLY. Hence, WAIT FOR 10 ns;
order of statements is important. END PROCESS;

• A process must end with the keywords

END PROCESS.

ECE 545 Introduction to VHDL 57

 Execution of statements in a PROCESS
Testing: PROCESS
BEGIN
test_vector<=“00”;
• The execution of statements WAIT FOR 10 ns;
continues sequentially till the
test_vector<=“01”;

Order of execution
last statement in the process.
• After execution of the last WAIT FOR 10 ns;
statement, the control is again test_vector<=“10”;
passed to the beginning of the WAIT FOR 10 ns;
process. test_vector<=“11”;
WAIT FOR 10 ns;
END PROCESS;
Program control is passed to the
first statement after BEGIN

ECE 545 Introduction to VHDL 58

 PROCESS with a WAIT Statement
• The last statement in the Testing: PROCESS
PROCESS is a WAIT instead of BEGIN
WAIT FOR 10 ns. test_vector<=“00”;
• This will cause the PROCESS
WAIT FOR 10 ns;
to suspend indefinitely when
test_vector<=“01”;

Order of execution
the WAIT statement is
executed. WAIT FOR 10 ns;
• This form of WAIT can be used test_vector<=“10”;
in a process included in a WAIT FOR 10 ns;
testbench when all possible test_vector<=“11”;
combinations of inputs have
been tested or a non-periodical WAIT;
signal has to be generated. END PROCESS;

Program execution stops here

ECE 545 Introduction to VHDL 59

 WAIT FOR vs. WAIT
WAIT FOR: waveform will keep repeating
itself forever

0 1 2 3 0 1 2 3 …

WAIT : waveform will keep its state after

the last wait instruction.

…
ECE 545 Introduction to VHDL 60
 Loop Statement

• Loop Statement
FOR i IN range LOOP
statements
END LOOP;

• Repeats a Section of VHDL Code

• Example: process every element in an array in
the same way

ECE 545 Introduction to VHDL 61

 Loop Statement – Example (1)

Testing: PROCESS
BEGIN
test_vector<="000";
FOR i IN 0 TO 7 LOOP
WAIT FOR 10 ns;
test_vector<=test_vector+”001";
END LOOP;
END PROCESS;

ECE 545 Introduction to VHDL 62

 Loop Statement – Example (2)

Testing: PROCESS
BEGIN
test_ab<="00";
test_sel<="00";
FOR i IN 0 TO 3 LOOP
FOR j IN 0 TO 3 LOOP
WAIT FOR 10 ns;
test_ab<=test_ab+"01";
END LOOP;
test_sel<=test_sel+"01";
END LOOP;
END PROCESS;

ECE 545 Introduction to VHDL 63

 ?

ECE 545 Introduction to VHDL 64