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Data Structure and Encoding Analysis

The document outlines the course units for a class on VLSI. Unit 5 covers high density memory elements, shifters, adders, ALUs, multipliers, parity generators, and zero/one detectors. Unit 6 discusses gate array ASICs and implementing a 4x4 multiplier using PLA. It also covers the architecture of PAL and FPGA. Unit 7 defines terms related to synthesis processes and discusses ASIC design flow stages. It explains synthesis, design capture tools, and design verification tools. Unit 8 covers CMOS testing needs and principles, chip and system-level test techniques, and layout design for improved testability.

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98 views1 page

Data Structure and Encoding Analysis

The document outlines the course units for a class on VLSI. Unit 5 covers high density memory elements, shifters, adders, ALUs, multipliers, parity generators, and zero/one detectors. Unit 6 discusses gate array ASICs and implementing a 4x4 multiplier using PLA. It also covers the architecture of PAL and FPGA. Unit 7 defines terms related to synthesis processes and discusses ASIC design flow stages. It explains synthesis, design capture tools, and design verification tools. Unit 8 covers CMOS testing needs and principles, chip and system-level test techniques, and layout design for improved testability.

Uploaded by

ravipati9
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd

NRI INSTITUTE OF TECHNOLOGY DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING CLASS:III ECE SUBJECT:VLSI

UNIT-5 1. Explain about High Density Memory Elements. 2. a)Explain about Shifters? b)Explain about Adders 3. a)Explain about ALUs b)Explain about Multipliers 4. a)Explain about Parity generators b) Explain about Zero/One Detectors UNIT-6 1. Explain about the following gate array based ASICS (a) Channel gate arrays (b) Channel less gate arrays (c) Structured gate arrays 2. Using PLA Implement 4*4 Multiplier circuit. 3. With neat sketches explain the architecture of PAL. 4. With neat sketches explain the architecture of FPGA.

[10M] [5+5=10M] [5+5=10M]

[5+5=10M]

[10M] [10M] [10M] [10M]

Unit-7 1. With respect to synthesis process explain the following terms. (a) Flattening (b) Factoring. (c) Mapping. 2. Explain the following processes in the ASIC design flow. (a) Post - layout timing simulation. (b) Post synthesis simulation. 3. What is synthesis? Explain about it? 4. Explain about Design capture tools and Design Verification Tools

[3M+3M+4M]

[5M+5M] [10M] [10M]

UNIT-8 1. a) Explain about CMOS Testing b) Need for testing [5M+5M] 2. Explain about Test Principles b) Design Strategies for test [5M+5M] 3. Explain about Chip level Test Techniques [10M] 4. Explain about System-level Test Techniques, Layout Design for improved Testability. [10M]

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