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RISC vs CISC in 8051 Microcontrollers

RISC processors have a reduced number of instructions that each take a single cycle to execute, while CISC processors have a large number of variable instructions that may take multiple cycles. Harvard architectures separate program and data memory so they can be accessed simultaneously, allowing faster execution. Von Neumann architectures have a single memory for both program and data, requiring serial access that is slower. Examples of Harvard architecture microcontrollers include the PIC and AVR families, while Von Neumann examples include the Intel x86 and Motorola 68000 families.

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87 views2 pages

RISC vs CISC in 8051 Microcontrollers

RISC processors have a reduced number of instructions that each take a single cycle to execute, while CISC processors have a large number of variable instructions that may take multiple cycles. Harvard architectures separate program and data memory so they can be accessed simultaneously, allowing faster execution. Von Neumann architectures have a single memory for both program and data, requiring serial access that is slower. Examples of Harvard architecture microcontrollers include the PIC and AVR families, while Von Neumann examples include the Intel x86 and Motorola 68000 families.

Uploaded by

Katrina Lynch
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd

Microcontroller

Explain the differences between the following:


a) RISC and CISC processors
b) Harvard and Von-Neumann architectures
Ans:
RISC:[Reduced Instruction Set Computer]

CISC:[Complex Instruction Set Computer]

1. Number of instructions is less.

1. Large number of instructions.

2. Instructions take only one instruction


instruction
cycle to Execute.

2. Many instructions take multiple


cycle to execute.

3. Fixed format instructions.

3. Variable format instructions.

4. In RISC only few addressing modes are there

4.Many addressing modes.

and most instructions have register to register


addressing mode.
5.Due to orthogonality or symmetry of the procon status
-essor (ability to write to all registers as if they

5.Conditonal jumps are usually based

register bits.

were same), conditional jumps can be based on


a bit in any memory.
6.Eg: PIC 16F877

CHANDRASHEKHARA B M.
[Type text]

6.Motorola 68000

5th EC

C SEC 1MS12EC404
Page 1

Microcontroller

Harvard Architecture

Von-Neumann Architecture

1. Separate blocks of Data memory & Program


memory.

Data
Data
memor
Memory
y

1. Single memory block for Data & Program memory.

Program
Program
memory
Memory

CPU
CPU

CPU
CPU

Program&
Program
DataData
and
Memory
memory

2. Execution in one cycle. Hence easier timing of


loops and delays.

2. Execution in multiple cycles.

3. Here we can fetch data and program in parallel so


that we can save the time.

3.Serial fetch instructions and data because program &


And data memories are in same block.

4. Here instruction & data are always separate.

4. Here problem is that data / program can get mixed.

5.Different code(instruction) and data path width are


Possible.
Ex: 14-bit instructions, 8-bit data in PIC 16F84.

5.Data and Instructions (multiples of) are of same size

6. It consists of more complex hardware.

6. It consists of Simple chip design.

7.MOV ACC,REG
Cycle1) a)Execute the previous instruction
b)Read MOV Acc, Reg
Cycle2) Execute MOV Acc, Reg
i.e. current instruction was fetched during the
previous instructions execution. This makes faster
execution.

7. MOV ACC,REG
Cycle1) Read instruction
Cycle2) Execute MOV Acc, Reg
In the first cycle of instruction execution, the instruction
is read from the memory space. In the next cycle, the
data to be put in the accumulator is read from the
memory space.

8. 8051 as Harvard:8051 has two separate signals


a) ~RD (P3.7) It is activated when byte is to be read
from external data memory.
b) ~PSENIt is for external program memory.

8.8051 as Von-Neumann: Here the two signals ~RD and


~PSEN are combined with a logical AND operation.
~RD
EN
~PSEN

9.Ex:Microchip PIC families, Atmel AVR

CHANDRASHEKHARA B M.
[Type text]

5th EC

9. PCs (Intel 80X86/Pentium, Motorola 68000),


Motorola
68XX C families.

C SEC 1MS12EC404
Page 2

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