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Computer Architecture Solutions

The document provides sample code in x86, C, and MIPS assembly for a loop that iterates from 0 to 99 and sums the iterations. It also describes a VLIW architecture problem where a tool takes MIPS code and groups instructions into VLIW instructions. For 18 MIPS instructions that are provided, the minimum VLIW machine width would be 3 to produce 9 VLIW instructions. The MIPS instructions grouped into each of the 9 VLIW instructions are listed.

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0% found this document useful (0 votes)
148 views4 pages

Computer Architecture Solutions

The document provides sample code in x86, C, and MIPS assembly for a loop that iterates from 0 to 99 and sums the iterations. It also describes a VLIW architecture problem where a tool takes MIPS code and groups instructions into VLIW instructions. For 18 MIPS instructions that are provided, the minimum VLIW machine width would be 3 to produce 9 VLIW instructions. The MIPS instructions grouped into each of the 9 VLIW instructions are listed.

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islandemiaj
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We take content rights seriously. If you suspect this is your content, claim it here.
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Assignment 4 Solutions

Other ISAs continued


Due: May 2, 2014
1. x86:

The following is x86 assembly. Write equivalent code in C and MIPS assembly. (It will
probably be easier for you to write the C code first, and then the MIPS assembly
equivalent.) In your write-up, include a mapping between the C variables / MIPS
registers you use and the x86 registers.
.text
.globl main
main:
movl $0x0, %ebx
movl $0x0, %ecx
jmp check
loop:
mov %ecx, %eax
add %eax, %ebx
addl $0x1, %ecx
check:
cmpl $0x63, %ecx
jle loop
ret
Ans:
C Code:
void main(void) {
int counter; // %ecx
int base = 0; // %ebx
int acc; // %eax
for (counter = 0; counter < 100; counter++) {

acc = counter;
base += acc;
}
}
It is admittedly ambiguous whether %eax returns or not. If so, the code would be
return acc;
Multiple answers were accepted.
MIPS code:
.text
.globl __start
__start:
ori $t0, $0, 0
ori $t1, $0, 0
ori $t2, $0, 0
ori $t3, $0, 100
loop:
beq $t1, $t3, done
sll $0, $0, 0
add $t2, $t0, $t1
add $t0, $t0, $t2
j loop
addi $t1, $t1, 1
done:
addiu $v0, $0, 10
syscall

// t0 is base (%ebx)
// t1 is counter (%ecx)
// t2 is acc (%eax)
// t3 is constant 100
// bge is a pseudo instruction
// nop in branch delay slot
// acc = counter
// base += acc
// acc++ in branch delay slot
// Prepare to exit (system call 10)

Common mistakes:
- 0x63 is a hex value and equal to 99 in decimal.
- Using <= 100 instead of < 100
- Using < 99 instead of <= 99
- Order of the comparison in cmpl $0x63, %ecx

[Link]:
In this problem, you are given a tool to transform machine code that is written for the MIPS ISA
to code in a VLIW ISA.
The VLIW ISA is identical to MIPS except that multiple instructions can be grouped together into
one VLIW instruction. Up to N MIPS instructions can be grouped together (N is the machine
width, which depends on the particular machine). The transformation tool cannot reorder MIPS
instructions to fill VLIW instructions. You are given the following MIPS program (we have
numbered the instructions for reference below):
(01) lw $t0, 0($a0)
(02) lw $t2, 8($a0)
(03) lw $t1, 4($a0)
(04) add $t6, $t0, $t1
(05) lw $t3, 12($a0)
(06) sub $t7, $t1, $t2
(07) lw $t4, 16($a0)
(08) lw $t5, 20($a0)
(09) srlv $s2, $t6, $t7
(10) sub $s1, $t4, $t5
(11) add $s0, $t3, $t4
(12) sllv $s4, $t7, $s1
(13) srlv $s3, $t6, $s0
(14) sllv $s5, $s0, $s1
(15) add $s6, $s3, $s4
(16) add $s7, $s4, $s6
(17) srlv $t0, $s6, $s7
(18) srlv $t1, $t0, $s7

1. When you run the tool with its settings targeted for a particular VLIW machine, you find that
the resulting VLIW code has 9 VLIW instructions. What minimun value of N must the target
VLIW machine have?
Ans:
N = 3 (see VLIW program below). If N = 2, then the VLIW program must have at least 11 MIPS
instructions, and the number of VLIW instructions either stays the same or decreases as width
is increased by one MIPS instruction.
2. Write the MIPS instruction numbers (from the code above) corresponding to each VLIW
instruction, for this value of N.
MIPS. Inst. No.

MIPS. Inst. No.

MIPS. Inst. No.

VLIW Instruction 1:

01

02

03

VLIW Instruction 2:

04

05

06

VLIW Instruction 3:

07

08

09

VLIW Instruction 4:

10

11

VLIW Instruction 5:

12

13

VLIW Instruction 6:

15

VLIW Instruction 7:

16

VLIW Instruction 8:

17

VLIW Instruction 9:

18

Multiple answers are accepted.

14

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