Appendices
Appendix A
ISCAS Circuits
ISCAS circuits
In this appendix we describe in more detail the ISCAS85 benchmark circuits used throughout this
thesis.
The following tables present for each such circuit, its intended function together with general
statistics on its lines and gates.
Circuit
c432
c499
c880
c1355
c1908
c2670
c3540
c5315
c6288
c7552
PI
36
41
60
41
33
233
50
178
32
207
Circuit
c432
c499
c880
c1355
c1908
c2670
c3540
c5315
c6288
c7552
PO
7
32
26
32
25
140
22
123
32
108
gates
160
202
383
546
880
1193
1669
2307
2416
3512
Function
Priority decoder
ECAT
ALU and control
ECAT
ECAT
ALU and control
ALU and control
ALU and selector
16-bit multiplier
ALU and control
level
17
11
24
24
40
32
47
49
124
43
buffer
26
32
162
196
223
313
534
avg
fanin
2.10
2.02
1.90
1.95
1.70
1.74
1.76
1.90
1.99
1.75
not
40
40
63
40
277
321
490
581
32
876
max
fanin
9
5
4
5
8
5
8
9
2
5
and
4
56
117
56
63
333
498
718
256
776
fanout
stems
89
59
125
259
385
454
579
806
1456
1300
nand
79
fanout
lines
236
256
437
768
995
1244
1821
2830
3840
3833
or
2
29
2
87
416
377
254
298
454
77
92
214
1028
244
nor
19
61
1
12
68
27
2128
54
avg
fanout
1.75
1.81
1.70
1.87
1.67
1.55
1.72
1.81
1.97
1.68
xor
18
104
max
fanout
9
12
8
12
16
11
16
15
16
15
Total
160
202
383
546
880
1193
1669
2307
2416
3512
Below we present high-level schematics of each circuit, with brief descriptions of their functions. The
information is taken directly from [Link] where a more recent
publication on such reverse engineering is referred [M. Hansen, H. Yalcin, and J. P. Hayes, Unveiling
the ISCAS-85 Benchmarks: A Case Study in Reverse Engineering, IEEE Design and Test, vol. 16, no.
3, pp. 72-80, July-Sept. 1999].
In the web page, the following introductory comment is then found:
The high-level ISCAS-85 benchmarks discussed in this paper are available below, and we invite
other researchers to use them. The models, of which we have constructed both structural and
behavioral versions, partition the original gate-level netlists into standard RTL blocks and identify the
functions of these blocks. Together, the gate-level and high-level models form a set of hierarchical
benchmark circuits that have proven to be useful research tools in several areas of digital design,
including test generation, timing analysis, and technology mapping. The web documentation for each
model consists of annotated circuit schematic diagrams, and executable (simulatable) descriptions
written in structural Verilog. The structural models are intended to express the specific high-level
structure implicit in the original gate-level designs. In most cases, we also provide behavioral Verilog
models, which define high-level blocks in the form of logical equations that can readily be synthesized
into gates.
Hence, this web page can be consulted for a more comprehensive analysis of such circuit benchmarks,
including their complete gate-level description.
185
C432
27-channel interrupt controller
Statistics: 36 inputs; 7 outputs; 160 gates
Function: c432 is a 27-channel interrupt controller. The input channels are grouped into three 9-bit
buses (we call them A, B and C), where the bit position within each bus determines the interrupt
request priority. A fourth 9-bit input bus (called E) enables and disables interrupt requests within the
respective bit positions. The figure above concisely represents the circuit. Modules labelled M1, M2,
M3, M4 contain the underlying logic.
The seven outputs PA, PB, PC and Chan[3:0] specify which channels have acknowledged
interrupt requests.
Module M1
186
C432
Module M2
Module M3
Module M4
Module M5
Module M5 is a 9-line-to-4-line priority encoder. An inverter was added to output 421gat to form
Chan[3] for a correct truth table.
187
C432
Bus Functions
I/O Bus
A[8:0]
B[8:0]
C[8:0]
E[8:0]
PA,PB,PC
Chan[3:0]
188
Function
Highest priority input bus
Middle priority input bus
Lowest priority input bus
Channel enable input bus
Requesting bus output
Requesting channel output
C499 / C1355
32-Bit Single-Error-Correcting Circuit
Statistics: 41 inputs; 32 outputs; 202/546 gates
Function: c499 was found to be a single-error-correcting circuit as shown above. The 41 inputs are
combined to form an 8-bit internal bus S, which then combines with 32 primary inputs to form the 32
primary outputs. The Boolean expressions defining S form the H matrix for a (40,32) Hamming code
[See C. L. Chen and M. Y. Hsiao. Error-Correcting Codes for Semiconductor Memory Applications:
A State-of-the-Art Review. IBM Journal of Research & Development, vol. 28, pp. 124-134, March
1984]. An example S bit is given by S0 = (ID00 ID04 ID08 ID12) (ID16 ID17 ID18 ID19)
(ID20 ID21 ID22 ID23) R IC0. Hence, it is in module M1 that most XOR gates lay.
Module M2 contains the necessary correcting logic, so c499 can correct single-bit errors;
however, no error-detection logic is present. The S lines are formulated to generate a unique syndrome
for each input line in error. The syndromes are the column vectors of H. If syndrome i is seen, output
ODi is inverted. This is specified by the 32 output equations realized by M2. As an example, OD00 =
S 0 S 1S 2 S 3 S 4 S 5 S 6 S 7 ID00.
The c1355 circuit has the same overall function as c499; it differs in that all XOR primitives of
c499 are expanded to their four-NAND-gate equivalents.
Bus Functions
I/O buses
ID[0:31]
IC[0:7]
R
OD[0:31]
Function
Input data
Input code
Read line
Corrected output data
189
C880
8-Bit ALU
Statistics: 60 inputs; 26 outputs; 383 gates
Function: c880 is an 8-bit ALU with the high-level model shown in above. Given the presence of a
CLA module in the 74181 ALU, it is not surprising to find a similar module in c880. The core of this
8-bit ALU is an 8-bit 74283-style adder. The multiplexers M1 and M6 are both controlled by module
M2 in a fashion reminiscent of horizontal microcode; i.e., an external source must ensure that no more
than one function is activated at a time on C(25:0).
Bus Functions
I/O buses
A[8:0]
B[7:0]
C[25:0]
D[3:0]
F[7:0]
G[3:0]
C in
C8
190
Function
Main A bus
Main B bus
Control bus
4-bit bus
Output function
4-bit bus
Carry in
Carry out
C1908
16-bit error detector/corrector
Statistics: 33 inputs; 25 outputs; 880 gates
Function: This is a 16-bit single-error-correcting and double-error-detecting (SEC/DED) circuit with
some byte-error detection capability. It generates a 6-bit syndrome from the 16-bit data input IN,
which is decoded to find the bit in error, if any. If an error is detected and the control inputs are set
appropriately, error correction is performed. C1908 has an output indicating an uncorrectable error;
this is set when more than one erroneous bit is detected. The circuit can also generate syndrome bits,
which are sent out via the SC lines. The external syndrome lines make it possible to cascade several
copies of c1908 so that detection and correction can be done for words of size greater than 16. This
circuit is quite similar to the Advanced Micro Devices Am2960 16-bit error detection and correction
unit.
191
C1908
Modules
M1: generates a 6-bit syndrome (SYN[5:0])
M2: may modify the syndrome with external inputs; outputs SYN'[5:0]
M3: decodes the syndrome to identify the bit in error, if any. Consists of 16 AND gates.
M4: corrects the input bit in error
M5: produces the output syndrome SC[5:0]
M6-M7: calculate a parity bit for the high (M6) and low byte (M7)
M8: asserts its output UE if an uncorrectable error is found in the input data bus
Inputs/Outputs
Inputs
InDataBus[15:0] (IN)
InCheckBits[5:0]
InExtSynBits[3:0]
E,B,F (control inputs)
G,H,K,L (control inputs)
192
Outputs
OutDataBus[15:0] (OUT)
OutSynCheckBits[5:0] (SC)
ByteParHi (BPH)
ByteParLo (BPL)
UncorrError (UE)
C2670
12-bit ALU and controller
Statistics: 233 inputs; 140 outputs; 1193 gates
Function: This benchmark consists of an ALU with a comparator, an equality checker, and several
parity trees. The comparator has two 12-bit inputs X and Y, and computes Y > X using a carrylookahead adder (CLA) that performs the addition !X+Y. It can be programmed to do a 4, 6, 8 or 12bit comparison of its inputs.
Module M7 (EqualZ_W) performs an equality check on two 17-bit buses. The ParityChecker
module (M8) contains five 10-input parity trees, whose outputs are all ANDed. This module seems to
perform a sanity check on the input buses of c2670. There are also several small pieces of logic which
are mostly random.
193
C2670
Inputs/Outputs
Inputs
input buses A[9:0], B[9:0]
Input buses Y1[5:0], Y2[5:0], Y3[3:0]
Inputs X[11:0], Y[11:0] of CompareXY (M4)
Inputs W[16:0], Z[16:0] of Bitwise Comparator (M7)
Q[9:0], R[9:0], S[9:0] (inputs to ParityChecker M8) *
ContA0, ContA1
ContB0, ContB1
ContZ0. ContZ1
ContEq
ContMask0,1,2
ContAlpha
ContBeta
ContPar0,1,2,3
ParTreeIns[11:0] (fanin of Q,R,S)
InTbus[7:0]
MiscRandomIns[11:0]
MiscMuxIn
MiscMuxCont0,1
Outputs
OutYgreaterX (Y>X)
OutYgreaterX_Equal (Y>X)#1 = (Y>X)#2
OutZequalW (Z==W)
OutNot_ZequalW (Z != W)
OutParCheck
OutNot_ParCheck
ParChkOuts[7:0]
OutTbus[7:0]
MiscMuxOuts[10:0]
MiscBusOuts[12:0]
MiscRandomOuts[17:0]
* Q[9:0], R[9:0] and S[9:0] are multiplexed out of Y1, Y2, Y3 and ParTreeIns
194
C3540
8-bit ALU with arithmetic, logic and shift operations
Statistics: 50 inputs; 22 outputs; 1669 gates
Function: This benchmark is an 8-bit ALU that can perform binary and BCD arithmetic operations as
well as logic and shift operations. BCD addition is done via a two's-complement adder by adding 6 to
both digits of the first operand, and then subtracting 6 from the digits of the result if they do not
generate a carry. A total of 14 control inputs are used for multiplexing and masking data inputs. The
largest module is M5 (ALU_Core), which consists of two 4-bit CLAs. Module M8 (Shifter) can shift
the input bus A by 1 to 8 bits in either direction. Parity and zero flags are generated by module M12
(Flags) using the input buses A, B and the output bus Z. Various logic functions of A and B are
calculated by module M13 which does not have an apparent high-level structure.
Modules M1 (BCD_add) and M7 (BCD_sub)
In order to perform BCD addition with a two's complement adder, module M1 adds 6 to each digit of
the input bus, and module M7 subtracts 6 from each digit of the result if there is no carry from that
digit.
195
C3540
Module M3 (MainMux1)
This module consists of two cascaded multiplexers, as shown above. The control signals Cont[3:0]
determine the select inputs of M3.
Module M4 (MainMux2)
Like M3, Module M4 is made up of two cascaded multiplexers. However, its select logic is more
involved. The control signals Cont[6:3] and Cont[1:0] are decoded into the select signals CHi, CLo1,
CLo2 and CLo3.
Module M5 (ALU_Core)
This is the largest module of the c3540 benchmark. The control inputs to this module are Cont[12:7]
and Cont[2:0]. An internal signal called Mode determines whether a logic or an arithmetic operation is
to be performed. Mode is 1 for a logic operation, and 0 for an arithmetic operation. In the case of
arithmetic operations, an additional control signal named Mask7_6 is used to mask bits #7 and #6 of
the MA bus.
A block named Logic_and_GP computes both logic operations as well as the generate and
propagate signals used for binary addition. The carry signals are computed by CalcCarry, and the final
result of the ALU is obtained by XORing the carry signals with a modified propagate signal called XP.
196
C3540
197
C3540
Module M8 (Shifter)
This module contains logic for shifting the input bus A by 1 to 8 bits in either direction. When shifting
towards LSB (MSB), the empty bit positions are filled by a Q (R) bus. The Shifter decodes the control
signals Cont[12:10], and Cont[2] into 8 signals, which are the select inputs for sixteen 8:1
multiplexers.
The X and Y buses are fed into a 2:1 multiplexer controlled by Cont[3]. There is an additional
multiplexer for bit #7 whose second input is A[7]; this can be used for shifting signed input data.
Module M9
This is a relatively small module that appears to calculate some special-purpose logic functions of the
input buses A and B. Five control inputs to this module are Cont[6] and Cont[3:0].
The details of LogicBlockM9 are shown below. It seems to calculate a non-standard function. It
may be some type of code translation or encryption.
198
C3540
Modules M10 and M11
Both these modules contain a set of eight 3:1 multiplexers of type Mux3_1c.
Module M12 (Flags)
This module generates two zero flags and four parity outputs. As shown above, the parities are
calculated from the input buses A and B, and the output bus Z. The zero flags are calculated from the
output bus Z only. Three control inputs to M12 are Cont[13] and Cont[9:8].
Inputs/Outputs
Input
A[7:0]
B[7:0]
Q[7:0]
R[7:0)
T[1:0]
Cin
K
Cont[13:0]
Output
Z[7:0]
OddParZ, OddParZ_Cont
OddParA
OddParB
NotZeroZ, ZeroZ_Cont
XCarry2, Cout_in0
PropThru
MiscOuts[4:0]
199
C5315
9-bit ALU
Statistics: 178 inputs; 123 outputs; 2406 gates
Function: This benchmark is an ALU that performs arithmetic and logic operations simultaneously on
two 9-bit input data words, and also computes the parity of the results. Modules M6 and M7 each
compute an arithmetic or logic operation specified by the control input bus CF[7:0]. Module M5
consists of multiplexers that route the results of M6 and M7 and four input buses to its four outputs.
Output buses OF1 and OF2 can also be set to logic 0 by MuxSel[8]. Modules M3 and M4 compute the
parity of the result of the operation given by CP=CF[7:4]. Module M5 contains four multiplexers
which direct the parity results and an additional set of four inputs to its outputs. The adders in M6 and
M7 as well as the parity logic for the arithmetic operations in M3 and M4 use a carry-select scheme
with 4-bit (low-order) and 5-bit (high-order) blocks. The circuit also includes logic for calculating
various zero and parity flags of the input buses.
200
C5315
201
C5315
202
C5315
203
C5315
204
C5315
Inputs/Outputs
Input
X0[8:0], X1[8:0]
MuxSelX
A[8:0]
Y0[8:0], Y1[8:0]
MuxSelY
B[8:0]
CinFX, CinFY
CinPX, CinPY
WpX[1:0]
WpY[1:0]
QP1,QP2,QP3,QP4
Q1[8:0], Q2[8:0], Q3[8:0], Q4[8:0]
WFX[8:0]
WFY[8:0]
MuxSel[10:0]
CF[7:0]
CP[3:0]=CF[7:4]
ParYin= MuxSelY ? ParYin0 : ParYin1
(ParYin0, ParYin1)
ParXin= MuxSelX ? ParXin0 : ParXin1
(ParXin0, ParXin1)
ContParChk[5:0]
MiscMuxIn[17:0]
MiscContIn[7:0]
MiscIn[8:0]
Output
OP1,OP2,OP3,OP4
OF1[8:0]
OF2[8:0]
OF3[8:0]
OF4[8:0]
NXF[8:0]
NYF[8:0]
CoX,CoY
PoX,PoY
ParityChk[4:0]
ZeroFlagOut[3:0]
MiscMuxOut[10:0]
MiscOut[25:0]
205
C6288
16-bit multiplier
Statistics: 32 inputs; 32 outputs; 2406 gates
Function: The c6288 benchmark, whose multiplication function was previously known, represents a
much larger gate-level circuit that also has a concise functional description. The figure above shows
how the 2406 gates form 240 full and half adder cells arranged in a 15x16 matrix. An alternate
representation is shown below, and the adder cells are detailed below that.
206
C6288
Alternate Depiction
Full Adder Module
The 15 top-row half adders lack the Ci input; each has two inverters at locations V. The single half
adder in the bottom row lacks the B input, thereby acquiring two inverters at locations W.
Bus Functions
I/O Busses
A[15:0]
B[15:0]
P[31:0]
Function
A bus
B bus
Product bus
207
C7552
34-bit adder, comparator and parity checker
High-Level Model of c7552
Statistics: 207 inputs; 108 outputs; 3512 gates
Function: This benchmark circuit contains a 34-bit adder (M5), a 34-bit magnitude comparator (M8)
using another 34-bit adder, and a parity checker (M9). Each of the XA, YA, and YB buses is fed by a set
of 2:1 multiplexers controlled by the Sel input. Bits 31-22 of XA and YB can be set to logic 0 with the
Mask input. The two adders M5 and M8 are identical, and are of carry select type, as are those of
c5315. They consist of alternating 4- and 5-bit blocks, with the last block being 2 bits. The comparator
(M8) of this benchmark is similar to that of c2670. It performs the comparison YB>XB (if Sel=0) or
YB>!YA1 (if Sel=1) by calculating YB+!XB (if Sel=0) or YB+!YA1 (if Sel=1) (Note: the input bus YA1
is assumed to be inverted). The comparator has an output (CoutY) for the whole 34-bit inputs as well
as an output (CoutY_17) for the 17-bit portion of its inputs. Module M7 calculates the parity for the
following four parts of the adder output SumX: SumX[8:0], SumX[17:9], SumX[26:18], SumX[33:27].
Module M9 appears to be a type of sanity checker that calculates the AND of the parities of all its
inputs.
208
C7552
209
C7552
210
C7552
Inputs/Outputs
Input
XA0[31:0]
XA1[31:0]
XB[33:0]
YA1[31:0]
YB0[33:0]
!Sel
CinX, CinY
XYAext, XYBext
PCXA0[6:0]
PCXA1[6:0]
PCYA0[6:0]
PCYA1[6:0]
PCYB0[6:0]
Mask=!Mask1+!Mask2
Mask1, Mask2
StrbIn[15:0]
MiscIn[7:0]
Output
SumX[33:0]
!SumPar[3:0]
CoutX1, CoutX2
CoutY1, CoutY2
CoutY_17
ParCheck[3:0]
XBbuf[33:0]
StrbOut
PCYA0buf[3:0]
MiscOut[5:0]
211
