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FPGA Mux/Demux Implementation Guide

The document describes implementing a 16x1 multiplexer and 1x16 demultiplexer using 4x1 multiplexers and 1x4 demultiplexers in Xilinx. It provides the code for the 16x1 mux entity using 4x1 mux components, and the code for the 1x16 demux entity using 1x4 demux components.

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261 views4 pages

FPGA Mux/Demux Implementation Guide

The document describes implementing a 16x1 multiplexer and 1x16 demultiplexer using 4x1 multiplexers and 1x4 demultiplexers in Xilinx. It provides the code for the 16x1 mux entity using 4x1 mux components, and the code for the 1x16 demux entity using 1x4 demux components.

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suritrue9644
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd

EXPERIMENT NO.

14

AIM: Implement a 16x1 mux using 4x1 mux in Xilinx.


CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--library UNISIM;
--use UNISIM.VComponents.all;
entity mux_16_1 is
Port ( x0,x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15 : in
std_logic;
se0,se1,se2,se3 : in std_logic;
z : out std_logic);
end mux_16_1;
architecture Behavioral of mux_16_1 is
component mux12 is
port ( s0,s1,i1,i2,i3,i4 : in std_logic;
y : out std_logic );
end component;
signal p1,p2,p3,p4:std_logic;
begin
h0:mux12
h1:mux12
h2:mux12
h3:mux12
h4:mux12

port
port
port
port
port

map(se0,se1,x0,x1,x2,x3,p1);
map(se0,se1,x4,x5,x6,x7,p2);
map(se0,se1,x8,x9,x10,x11,p3);
map(se0,se1,x12,x13,x14,x15,p4);
map(se2,se3,p1,p2,p3,p4,z);

end Behavioral;

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OUTPUT:

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EXPERIMENT NO. 15

AIM: Implement a 1x16 demux using 1x4 demux in Xilinx.


CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--library UNISIM;
--use UNISIM.VComponents.all;
entity demux_16_1 is
Port ( cin : in std_logic;
se0,se1,se2,se3 : in std_logic;
O0,O1,O2,O3,O4,O5,O6,O7,O8,O9,O10,O11,O12,O13,O14,O15 : out
std_logic);
end demux_16_1;
architecture Behavioral of demux_16_1 is
component demux1 is
port (x,c1,c2:in std_logic;
y1,y2,y3,y4:out std_logic);
end component;
signal p1,p2,p3,p4:std_logic;
begin
h0:demux1 port map(cin,se0,se1,p1,p2,p3,p4);
h1:demux1 port map(p1,se2,se3,O0,O1,O2,O3);
h2:demux1 port map(p2,se2,se3,O4,O5,O6,O7);
h3:demux1 port map(p3,se2,se3,O8,O9,O10,O11);
h4:demux1 port map(p4,se2,se3,O12,O13,O14,O15);
end Behavioral;

2 | Page

3 | Page

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