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Control System Design Assignments

The document outlines 9 control system design problems involving the design of various controller types (PD, lead, lead-lag, PID) to meet time and error-based specifications for various plant transfer functions. The problems involve designing controllers, stating the final controller transfer function, and annotating step responses to verify the design meets specifications.

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Asfand Yar Akram
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112 views1 page

Control System Design Assignments

The document outlines 9 control system design problems involving the design of various controller types (PD, lead, lead-lag, PID) to meet time and error-based specifications for various plant transfer functions. The problems involve designing controllers, stating the final controller transfer function, and annotating step responses to verify the design meets specifications.

Uploaded by

Asfand Yar Akram
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

HW #3

1. For the system given on slide 9 of lecture15 and 16, design a PD controller to achieve: Mp
~<= 10% and tr ~<= 0.8 sec. You may have to tune your design but give the final version of
your controller TF and the annotate step response for verification.
2. Redo the above problem with a lead controller instead of a PD controller. Do it with two
methods: a) select your lead zero yourself b) bisection. Give your final controller TF and the
annotated closed-loop closed loop step response.
3. For the system given on slide 10 of lecture 17, design a lead-lag controller to achieve the
following time domain specifications: Mp ~<= 10%, ts ~<= 7 sec, tr ~<= 3 sec, ess to step =
0, and ess to ramp ~<= 0.2.
4. Redo the above problem with desired ess to ramp = 0. In this case, you have to use a PI. So
your overall controller could be either a lead-PI, or a PID.
5. For the system given on slide 19 and specifications given on slide 21 except ess to ramp = 0,
design a PID controller and verify your design.
1
6. Design a lead-lag for a plant with TF G( s) , and achieve the following design
s ( s 5)
2

specifications: Mp <= 15%, tr <= 1 sec, and ess to acceleration <= 0.5.
7. B-6-22, but target a Mp of 15% and ess to ramp <= .
8. B-6-21, replace specs by: Mp<=20%, ts<=2s (tol=2%), tr<=0.5s, ess_ramp <=0.01.
9. For the system given in Figure 7-166 (B-7-32), design a controller to achieve the following
specifications: ts <=1.5 sec, tr <= 0.5 sec, Mp <= 12%, and ess to a unit acceleration signal is
<=2.5.

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