IC Applications Laboratory

Experiment No: 1
OP AMP APPLICATIONS
AIM: To verify the operation of given Adder, Subtractor and comparator using 741 op-
amp.
APPARATUS:
1. Operational Amplifier A 741 IC –1No.
2. Resistors 1K - 5, 220, RL=10k
3. Power supply (0-30V)
4. Multi meter
5. Bread board
6. CRO (20MHz/30MHz)

CIRCUIT DIAGRAM:
1. ADDER:
Ra=1K V2 RF=1K
+Va
�
Ia R =1K IF +Vcc
+Vb b

Ib Rc=1K 2 7
+Vc - 6
IB20 V1 741 RF
Ic V0abc
IB10 + abRc
3 4
-VEE
ROM = (Ra  Rb  Rc  RF) RL

Fig. 1.1 Inverting Configuration

R1 V2 RF
Vcc
-
R 741 baFRVc
V1 + V10
+Va R31
R
+Vb VEE RL
R
+Vc

Fig. 1.2 Non Inverting Configuration

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2. SUBTRACTOR:
R R
+Va
+Vcc
-
R 741 V0 = Vb-Va
+Vb +

-VEE
R RL

Fig. 1.3: Subtractor

3. BASIC COMPARATOR: +15V

2 - 7
741
6
3
+ 4
R 1K -15V RL 10K
R 1K

V REF V IN

Fig..1.4. Non- Inverting comparator

MODEL GRAPH: Vin

Vin

Vp
Vp
- Vref 0V
t
0V t -VREF

- Vp
- Vp
V0
V0
Vin >VREF Vin >VREF
+VSAT Vin >VREF
+VSAT
0V t
0V
t -VSAT
Vin <VREF
-VSAT Vin <VREF Vin <VREF

Fig.. 1.5.a. If Vref is positive Fig.. 1.5.b If Vref is negative

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THEORY:
1. SUMMING AMPLIFIERS

(A)INVERTING CONFIGURATION

Fig. 2.1 shows the inverting configuration with three inputs V a, Vb, and Vc using input
resistors Ra, Rb, and Rc. The circuit can be used as a summing amplifier, scaling
amplifier, or averaging amplifier. The circuit’s function can be verified by examining
the expression for the output voltage Vo, which is obtained from Kirchhoff’s current
equation written at node V2.
Referring to Fig, Ia + Ib + Ic = IB + IF
Since Ri and gain A of the op-amp are ideally infinity, IB = 0A and V1 = V2 0V.
Therefore,
V a Vb V c V
   o
R a Rb Rc RF
R R R 
Vo   F Va  F Vb  F  eq. 1
 Ra Rb Rc 
SUMMING AMPLIFIER:
For example, in the circuit of Fig 2.1, Ra = Rb = Rc = R, then equation (1) can be
rewritten as

RF
Vo   Va  Vb  Vc 
R

This means that the output voltage is equal to the negative sum of all the inputs times
the gain of the circuit RF/R: Hence the circuit is called a summing amplifier.

(B) NON INVERTING CONFIGURATION:

If input voltage sources and resistors are connected to the non-inverting terminal as
shown in Fig.2.2, the circuit can be used either as a summing or averaging amplifier
through selection of appropriate values of resistors, that is, R1 and RF.

Using the superposition theorem, the voltage V1 at the non-inverting terminal is

R R R
V1  2 Va  2 Vb  2 Vc
RR RR RR
2 2 2

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Va Vb Vc Va  Vb  Vc
V1     eq. 2
3 3 3 3
 RF 
Hence the output voltage is Vo = 1  V1
 R1 

 R F  Va  Vb  Vc
= 1  
 R 1  3

SUMMING AMPLIFIER:

A close examination of equation (2) reveals that if the gain (1+R F/R1) is equal to the
number of inputs, the output voltage becomes equal to the sum of all input voltages.
That is, if (1+RF/R1) = 3. (From equation (1)),
Vo = Va + Vb +Vc
Hence the circuit is called a non-inverting summing amplifier.

2. SUBTRACTOR:

A basic differential amplifier can be used as a subtractor as shown in Fig. 2.3. In this
Fig, input signals can be scaled to the desired values by selecting appropriate values
for the external resistors; when this is done, the circuit is referred to as scaling
amplifier. However, in the Fig. all external resistors are equal in value, so the gain of
the amplifier is equal to 1. From the Fig, the output voltage of the differential
amplifier with a gain of 1 is
RVa  Vb 
V0  
R
That is, V0  Vb  Va

Thus the output voltage V0 is equal to the voltage applied to the non-inverting
terminal (Vb) minus the voltage applied to the inverting terminal (V a) ,hence the
circuit is called a subtractor.

3. COMPARATOR:
Fig.2.4.a shows an op-amp used as a comparator. A fixed reference voltage V ref of 1V
is applied to the (-) input, and the other time-varying signal voltage V in is applied to
the (+) input. Because of this arrangement, the circuit is called the noninverting
comparator.

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When Vin is less than Vref, the output voltage V0 is at –Vsat(-VEE) because the voltage
at the (-) input is higher than that at the (+) input. On the other hand, when V in is
greater than Vref, the (+) input becomes positive with respect to the (-) input, and V 0
goes to +Vsat (+Vcc). Thus V0 changes from one saturation level to another whenever
Vin  Vref, as shown in Fig. 2.4.b.

In short, the comparator is a type of analog-to-digital converter. At any given time the
V0 waveform shows whether Vin is greater or less than Vref. The comparator is
sometimes also called a voltage-level detector because, for a desired value of V ref, the
voltage level of the input Vin can be detected.

If the reference voltage Vref is negative with respect to ground, with sinusoidal signal
applied to the (+) input, the output waveforms will be as shown in Fig.2.4.c.

PROCEDURE:
Part 1: ADDER:
1. Connect the circuit as shown in Fig. 1.1.
2. Apply different DC input voltages at Va, Vb, and Vc and measure the output voltage
Vo using a multi meter
It should be Vo = Va + Vb + Vc

Part 2: SUBTRACTOR:
1. Connect the circuit as shown in Fig.1.3.
2. Apply different DC input voltages at Va, and Vb and measure the output voltage Vo
using a multi meter.
It should be Vo = Vb – Va.

Part 3: COMPARATOR:
1. Connect the circuit as shown in Fig. 1.4.
2. Apply a reference voltage of (say 1V), to inverting terminal of op-amp.
3. Apply a sinusoidal wave with a peak voltage more than Vref to OP-AMPs
Non-inverting terminal.
4. Observe the output at pin number 6, which will be a square wave with peak to peak
voltage of (Vsat to –Vsat).
5. Observe that when Vref is less than Vin, then the output goes to +Vsat,
when Vref is greater than Vin then output goes to –Vsat.
6. Now set another reference voltage and repeat the steps 4 and 5.
7. Draw the observed waveforms on graph sheet and obtain the practical reference
voltage.

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OBSERVATIONS:
ADDER:
Input Output
[Link]
Va Vb Vc Theoretical Practical
1.
2.
3.

SUBTRACTOR:
[Link]. Input Output
Va Vb Theoretical Practical
1.
2.
3.

COMPARATOR:
Vin= Vsat= –Vsat=

[Link] Vref Vo

1.
2.
3.
RESULT & ANALYSIS:

CONCLUSIONS:
It is observed that the output Values are very much nearer to the desired values. So we
can conclude that Adder, Subtractor, and comparator are functioning properly.

QUESTIONS:
1. What is an IC?
MVGR College of Engineering Department of ECE 6
 R R
1 F
C
1V
F IC Applications Laboratory
7 0
2 +15 -1V

+
Signal -
2. What V 6
are the AC characteristics of an Op-Amp?
Generat 741
2V
3. What are the DC characteristics
or
3
+ of an Op-Amp?
4. What is a monolithic IC? -
4 15 0
5. What isRom=R
a linear IC? 51 R CRO
f
5V L
-2V Experiment No: 2
FREQUENCY RESPONSE OF INTEGRATOR AND DIFFERENTIATOR
USING 741 OP-AMP

AIM: To design and observe the output of an active integrator and differentiator
using 741 op-amp for a given input signal and plot their frequency response
APPARATUS:
1. Operational Amplifier A 741 IC –2No.
2. Resistors
3. RL10K, other resistors of designed values
4. Bread board
5. CRO (20MHz/30MHz)
6. Capacitors
7. Multi meter
8. Power supply( 0-30V)

CIRCUIT DIAGRAM:
R1 Rf

Vi
i1 if Cf
iB
+

Signal 7
Generator 2 +15
- V 6
t(msec)
741 Vo
+
3
-
4 15V
CRO t(msec)
Rom=R1 RL

Fig. 2.1: Integrator

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Fig. 2.2: Differentiator

�A 741
Offset Null 1 8 NC
INV I/P 2 7 V+
Non –Inv I/P 3 6 O/P
V- 4 5 Offset Null
Fig. 2.3: PIN DIAGRAM of OP AMP

Voltage gain in dB

RF
dB
R1
AF VCO

0 fa fb f

Fig. 2.4a: Frequency Response of Integrator

Gain dB

fa fb f

Fig. 2.4b: Frequency Response of differentiator

THEORY:

A) INTEGRATOR:

The circuit shown in Fig. 2.1 in which “the output voltage waveform is the integral of
the input voltage waveform is the integrator or the integration amplifier.

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Such a circuit is obtained by using a basic inverting amplifier configuration, if the

feedback resistor RF is replaced by a capacitor CF.
Analysis of Integrator Circuit:
The expression for the output voltage v 0 can be obtained by writing Kirchhoff’s
current equation at node v2:
i1 = IB + iF
Since IB is negligibly small,
i1  iF
Recall that the relationship between current through and voltage across the capacitor
is
dv c
iC = C
dt
v1  v 2 d 
Therefore,  C F   v1  v 0 
R1  dt 
However, v1 = v2  0 because A is very large. Therefore,
vin d
 CF   v0 
R1 dt
The output voltage can be obtained by integrating both sides with respect to time:
t t
vin d
0 R1 dt  0 C F dt   v0  dt
= CF (-v0) + v 0 t 0

t
1
Therefore, v0 =
R1C F v
0
in dt  C eq. 1

Where C is integration constant and is proportional to the value of the output voltage
v0 at time t=0 seconds.
eq. 1 indicates that the output voltage is directly proportional to the negative integral
of the input voltage and inversely proportional to the time constant R1CF.

If the input to the integrator is a sine wave, the output will be a cosine wave, and if the
input is a square wave, the output will be a triangular wave.

In the circuit shown in Fig. the stability and the low frequency roll-off problems can
be corrected by the addition of a resistor R2 (RF). The term stability refers to a constant
gain as frequency of an input signal is varied over a certain range. Low frequency
roll-off refers to the rate of decrease in gain at lower frequencies. The input signal will
be integrated properly if the time period T of the signal is larger than or equal to RFCF.
The frequency at which gain is 0 dB is given by fb = 1
 2R1C f

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The gain limiting frequency is given by fa = 1

 2R f C f

The Values of fa and in turn R1Cf and RfCf Values should be selected such that

fa<fb.
Ex: If fa=0.1fb, then Rf=10R1.

The input signal will be integrated properly, if the Time period of the signal T

≥ RfCf.

APPLICATIONS:
The integrator is most commonly used in analog computers and analog to digital
converters and signal wave shaping circuits.

B) DIFFERENTIATOR:

The circuit shown in Fig.2.2 performs the mathematical operation of differentiation

that is the output waveform is the derivative of the input waveforms.
The differentiator may be constructed from a basic inverting amplifier if an input
resistor R1 is replaced by a capacitor C1.

ANALYSIS OF DIFFERENTIATOR CIRCUIT:

The expression for the output voltage v 0 can be obtained by writing Kirchhoff’s
current equation at node v2 as follows:
iC = IB + iF
Since IB  0,

iC = iF
d v  v0
C1  vin  v 2   2
dt RF
But v1 = v2  0V, because A is very large. Therefore,

dvin v dvin
C1  0 Or v 0   RF C1
dt RF dt
Thus the output v0 is equal to RFC1 times the negative instantaneous rate of change of
the input voltage vin with time.

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Since the differentiator performs the reverse of the integrators function, a cosine wave
input will produce a sine wave output, or triangular wave input will produce a Square
wave output.
The stability and the high frequency noise problems can be corrected by the addition
of two components R1 and CF.
The frequency at which gain is 0 dB is given by fa = 1
 2R f C1

The gain limiting frequency is given by fb = 1 where R1C1=RfCf

 2R1C1

The input signal will be differentiated properly, if the Time period of the signal

T ≥ RfC1.

 From the frequency f to f b, the gain increases at 20dB/decade. However, after

fb the gain decreases at 20 dB/decade.

APPLICATIONS:
The differentiator is most commonly used in wave shaping circuits to detect
high frequency components in an input signal and also as a rate-of-change detector in
FM modulator.

DESIGN:
Part 1: Design of Integrator
Design an Integrator to integrate an input signal that varies in frequency from 1 KHz
to 10 KHz.
1
[Note: Select T ≥ Rf Cf, where Rf Cf = (T= input signal time period)]
2f a
1. Select fa = 1 KHz. Assume a value of Cf < 1 f. (Let Cf = 0.1 f)
( fa is the gain limiting frequency)
1
2. Calculate the value of Rf using the formula Rf = 2f C
a f

3. let fb=10fa ( fb is the frequency at which gain is 0 dB)

1
4. Calculate R1 using the formula R1= 2f C .
b f

5. Choose Rom = R1.

6. Take load resistor RL = 10K

Part 2: Design of Differentiator

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Design a Differentiator to differentiate an input signal, that varies in frequency from 1

KHz to 20KHz.
1. Select fa = 1 KHz. Assume a value of C1 < 1 f. (Let C1 = 0.1 f)( fa is the
frequency at which gain is 0 dB)
1
2. Calculate the value of Rf using the formula Rf =
2f a C1
3. let fb= 20fa , fb is the gain limiting frequency Calculate R1 using the formula
1
R1=
2f b C1
4. From R1C1 = RfCf calculate Cf
5. Choose Rom = Rf.
6. Take load resistor RL = 10K

PROCEDURE:

Part 1
1. By using the component values as per the above specified design, Connect the
circuit as shown in the Fig.2.1 & Fig.2.2
2. Apply the 1VP-P, 1KHz Sine wave or Square wave as input
3. Observe the output on CRO.
4. Draw the input and output Signals on the Graph paper.
Part 2
1. Vary the input signal (Preferably Sine wave) frequency from 100 Hz to 20
KHz and note down the amplitude of the output signal (V0).
2. Calculate Gain Vo / Vi at each value of the input signal frequency. Also
Calculate dB Value of Gain 20 log Vo / Vi .
3. Plot the graph between frequency (on X-Axis) and dB Value of Gain 20log (
Vo / Vi ) (on Y-Axis)
4. Identify the Practical Values of fa and fb from the Graphs.

(Note: The Practical Values of fa and fb observed from the Graphs must equal to the
Theoretical values)

OBSERVATIONS:
Integrator:
Vin=

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[Link] Input Frequency Output voltage V0 (V) Vo

(Hz) Gain V
i

1. 100
2. 200
3. 300
. .
.
15. 10K

Differentiator:
Vin=
[Link] Input Frequency Output voltage V0 (V) Vo
(Hz) Gain V
i

1. 100
2. 200
3. 300
. .
. .
15. 10K

RESULT & ANALYSIS:

Hence the output of an active integrator and differentiator using op-amp 741 for a
given input signal is observed and plotted their frequency response by
varying the input signal frequency from 100Hz to 10(or 20) KHz.

CONCLUSIONS: The Practical Values of fa and fb observed from the Graphs are
equal to the theoretical values. From this we can conclude that the Integrator and
Differentiator using 741 OP-AMP are satisfying their function properly.

QUESTIONS:

1. What is the condition for integrator and differentiator?

2. What are the applications of integrator and differentiator?
3. What are the equations related to input and output for integrator and
differentiator?

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Experiment No:3
GENERATION OF TRIANGULAR WAVEFORM USING 741 OP-AMP
AIM: To observe the triangular waveform for the given 741 Op-Amp function
generator.

APPARATUS: Op-amp 741-2No,

Capacitor – 0.1f – 2No,
Resistors –14K-1, 10K-1, 28K-1

CIRCUIT DIAGRAM:

C= 0.05µF
R2=28KΩ

Ri= 14KΩ +15V

7
R1=10KΩ +15V
2
6 3
3 741 6
741
7 4 2
VA 7
con 4 VB
-15V
troll
ed -15V
Fig. 3.1.a Circuit osci
diagram of Function generator using 741 OPAMP
llat
OUTPUT WAVEFORMS or

15
V
B
+Vsat

5 V
UT

0 t(ms)
1 2 3

-5 V
LT

- 10
-Vsat

- 15

Fig. 3.1.b Model waveform

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Pin out diagram of �A 741 IC

Offset Null 1 8 NC

741
INV I/P 2 7 V+
Non –Inv I/P 3 6 O/P
V- 4 5 Offset Null
Fig 3.1.c Pin Diagram
THEORY:
A basic bipolar triangle wave generator circuit is presented in Fig. 3.1.a . The triangle
wave VA , is available at the output of the 741 integrator circuit . The square wave
signal VB, is available at the output of the 741 comparator . Assume that VB is high at
+Vsat. This forces a constant current (Vsat/R i) through C (left to right) to drive VA
negative from VUT to VLT. When VA reaches VLT, Pin 3 of the comparator goes
negative and VB snaps to –Vsat. And t =1m sec.

When VB is at -Vsat , it forces a constant current( right to left) through C to drive V A

positive from VLT toward VUT ( the time interval 1 to 2 msec) . When VA reaches VUT at
t= 2msec , pin 3 of the comparator goes positive and VB snaps to +Vsat. This initiates
the next cycle of oscillation .

FREQUENCY OF OPERATION
The peak values of the triangular wave are established by the ratio of resistor
R2 to R and the saturation voltages .
 Vsat R1
They are given by VUT 
R2
Vsat R1
V LT 
R2
If the saturation voltages are reasonable equal , the frequency of oscillation (f)
R2
is given by f 
4 Ri R1C
PROCEDURE:
1. Connect the circuit as shown in the Fig. 3.1.a.
2. Observe the output waveforms on CRO and note down necessary readings and
waveforms.
3. Calculate the time period and amplitude of the waveform theoretically.
4. Compare the theoretical values with the experimental results.
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OBSERVATIONS:
[Link] wave output:
Amplitude= Frequency=
[Link] wave output:
Amplitude= Frequency=
[Link], LT:

Theoretical Practical
UT

LT

RESULT & ANALYSIS:

Hence triangular waveform is generated using 741 Op-Amp function generator .

CONCLUSIONS:

It can be concluded that the 741 integrator has produced a triangle wave (VA) and the
741 comparator has produced a square wave (VB) with amplitude levels –Vsat to +Vsat.
The output of the 741 comparator was given to the integrator’s input. That means
integration of square wave gives the triangle wave.

QUESTIONS:

1. What is the purpose of a Function Generator?

2. How 741 Op-amp acts as function generator?
3. Define the Vut and VLt .
4. How does an Integrator used in the generation of triangular waveform?

Experiment No: 4
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FREQUENCY RESPONSE OF LOWPASS FILTER & HIGH PASS FILTER

USING 741 OPAMP

AIM: To design and plot the frequency response of first order low pass and high pass
filters using741 op-amp and to find higher and lower Cut-off frequencies.

APPARATUS:
1. Signal generator (0-1MHz)
2. Oscilloscope (20/30MHz)
3. Bread board
4. Power supply (0-30V)
5. Resistors 15K (1 No.), 10K (3 No’s)
6. Capacitors 0.01F -1No.
7. Op-amp 741 IC – 1No.

CIRCUIT DIAGRAM:

1. LOW PASS FILTER

R1 V2 RF

+Vcc
Voltage gain
10K
10K
+15v
- -20dB/decade
R 741 V0
+ AF
20K pot at -VEE RL
15.9K Passban Stopband
Vin 0.01F
C 10K 0.707AF d
-15v fH Frequenc
yyyyyyyy
+

yyy

(b)

Fig. 4.1 a Fig. 4.1 b

Fig. 4.1 First-order low-pass Butterworth filters. (a) Circuit. (b) Frequency response

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 R1 V2 RF

10K +Vcc IC Applications Laboratory

10K
+15
- v
2. HIGH C
PASS FILTER 741 V0
1
-VEE
0.01F
-15v
RL
10K Voltage gain
20K pot at R
Vin
15.9K
-20dB/decade

AF

0.707AF
stopband Pass band
dd
fL

Fig.4.2 First-order high-pass Butterworth filters. (a) Circuit. (b) Frequency response

THEORY:

FILTER ANALYSIS:

1. LOW PASS FILTER:

Fig.4.1.a shows a first-order low-pass Butterworth filter that uses an RC network for
filtering. Note that the op-amp is used in the non-inverting configuration;

Hence it does not load down the RC network. Resistors R 1 and RF determine the gain
of the filter.

According to the voltage-divider rule, the voltage at the non-inverting terminal

(across capacitor C) is
 jXc
v1  vin eq. 1
R  jXc
Where
1
j=(-1) and -jXc= j 2fC

Simplifying eq. 1, we get

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vin
v1 
1  j 2fRC
And the output voltage
RF
v 0  (1  )v1
R1
RF vin
That is, v0  (1  )
R1 1  j 2fRC
v0 AF
 eq. 2
vin 1  j ( f / f H )
v0
Where = gain of the filter as a function of frequency
vin
RF
AF  (1  ) = pass band gain of the filter
R1
f = frequency of the input signal
1
fH  = high cutoff frequency of the filter
2RC

The gain magnitude and phase angle equations of the low-pass filter can be obtained
by converting eq. 2 into its equivalent polar form, as follows:
V0 AF


Vin  1  ( f / f H ) 2  eq. 3

 f 
 = -tan-1  
 fH 
Where  is the phase angle in degrees.

The operation of the low-pass filter can be verified from the gain magnitude eq .3:

1. At very low frequencies, that is, ffH,

V0
Vin
 AF

V0 AF
2. At f=fH =  0.707 AF
Vin 2

V0
3. At ffH, Vin
 AF

Thus the low-pass filter has a constant gain A F from 0 Hz to the high cutoff frequency
fH.

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At fH the gain is 0.707 AF, and after fH it decreases at a constant rate with an increase in
frequency see Fig.4.1.b. That is, when the frequency is increased to tenfold (one
decade), the voltage gain is divided by 10.

In other words, the gain decreases 20db (=20 log 10) each time the frequency is
increased by 10. Hence the rate at which the gain rolls off after fH is 20 db/decode or 6
db/octave, where octave signifies a twofold increase in frequency.

The frequency f= fH is called the higher cutoff frequency because the gain of the filter
at this frequency is down by 3 db (=20 log 0.707) from 0 Hz. Other equivalent terms
for cutoff frequency are -3db frequency, break frequency, or corner frequency.

2. HIGH PASS FILTER:

High-pass filters are often formed simply by interchanging frequency-determining
resistors and capacitors in low-pass filters. That is, a first-order high-pass filter is
formed from a first-order low-pass type by interchanging components R and C.
Similarly, a second-order high-pass filter is obtained from a second-order low-pass
filter if R and C are interchanged, and so on.

Fig.4.2.b shows a first-order high-pass Butterworth filter with a low cutoff frequency
of fL. This is the frequency at which the magnitude of the gain is 0.707 times its pass
band value. Obviously, all frequencies higher than fL are pass band frequencies, with
the highest frequency determined by the closed-loop bandwidth of the op-amp.

Note that the high-pass filter of Fig.4.2.a and the low-pass filter of Fig.4.1.a are the
same circuits, except that the frequency-determining components R and C are
interchanged.
For the first-order high-pass filter of Fig.4.2.a., the output voltage is
R j 2fRC
V0  (1  F ) Vin
R1 1  j 2fRC
or
V0
 AF 

 j f / fL   
Vin 1  j  f / f L  
RF
Where AF  (1  ) = pass band gain of the filter
R1
f= frequency of the input signal (Hz)
1
fL = 2RC = low cutoff frequency (Hz)

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Hence the magnitude of the voltage gain is

V0 AF  f / f L 


Vin  1   f / f L  2 
Since high-pass filters are formed from low-pass filters simply by interchanging R’s
and C’s, the design procedure of the low-pass filter is also applicable to the high-pass
filters
FILTER DESIGN:
A) LPF Design:

Design a LPF having Cutoff frequency of 1KHz with a Passband gain of 2.

A low-pass filter can be designed by implementing the following steps:

1. Choose a value of high cutoff frequency fH (let us take 1KHz)

2. Select a value of C less than or equal to 1µf. ( let us take C=0.01µf .)
1
3. Calculate the value of R using the formula R 
2f H C
4. Finally, select values of R1 and RF dependent on the desired pass band gain A F
RF
using AF  (1  ) [Since AF=2,then R1 = RF. Let R1 = RF =10KΩ]
R1
5. Let RL=10KΩ.

B) HPF Design:
Design a HPF having Cutoff frequency of 1 KHz with a Pass band gain of 2.
A High-pass filter can be designed by implementing the following steps:

1. Choose a value of low cutoff frequency fL (Let us take 1KHz)

2. Select a value of C less than or equal to 1µf. (Let us take C=0.01µf.)
1
3. Calculate the value of R using the formula R 
2f L C
4. Finally, select values of R1 and RF dependent on the desired pass band gain A F
RF
using AF  (1  ) [Since AF=2, then R1 = RF. Let R1 = RF =10KΩ]
R1
5. Let RL=10KΩ.

NOTE:
It is better to take a capacitor of a standard (fixed) value, not a variable capacitor.

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If we take variable capacitor value, sometimes, the filter may not give proper response
(output). So in the above design procedure, we have chosen a fixed value for the
capacitor, not a variable capacitor, and then calculated the value of resistor for a
desired frequency.

PROCEDURE:
LOW PASS FILTER& HIGH PASS FILTER FREQUENCY RESPONSE
1. Connect the circuit as shown in Fig. 4.1.a & Fig. 4.2.a
2. Take a signal generator and observe its output (sinusoidal signal) on CRO.
Adjust the Amplitude of the sinusoidal signal (Vi) as [Link] its frequency
as 100Hz.
3. Connect the signal generator to the input of the LPF. Using CRO observe the
input and output waveforms simultaneously.
4. Vary the frequency of input signal from 100Hz to 100KHz
5. Measure the output voltage Amplitude (Vo) for every input frequency using
oscilloscope.
Vo
6. Calculate the Gain of the Filter . Also Calculate its dB Value.
Vi
7. Draw the graph between frequency (Hz) on X-Axis and the Gain on Y –axis
on semi -log sheet.
8. Calculate the cut off frequency from the graph. This is the Practical value of
Cut off frequency. [From the graph find the value of Cut off frequency, at
which the Gain is 0.707 times that of Pass band gain (AF)].
9. Compare the Practical values with Theoretical values.

OBSERVATIONS:
Input Signal Amplitude (Vin) = 1Vp-p

Frequency Output Gain = Vo/Vin Gain(in dB) =

(Hz) voltage(Vo) 20log (Vo/Vin)
100Hz
200Hz
600Hz
900Hz
950Hz
980Hz
1KHz
1.1KHz
1.2KHz
1.4KHz

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2KHz
.
100KHz

RESULT & ANALYSIS:

Hence the frequency response of first order low pass and high pass filters using 741
OP-AMP were plotted, and Calculated the Higher and Lower Cut-off frequencies,
from Graphs.

CONCLUSIONS:

The Practical values are same as the theoretical values in both the cases
(ie.,LPF&HPF) In the First case, for the frequencies below 1KHz the Filter’s Gain is
Constant and after 1KHz there is a decrease in the Gain. So it is called as Low Pass
Filter.
In the Second case, for the frequencies above 1KHz the Filter’s Gain is Constant and
below 1KHz there is a decrease in the Gain. So it is called as High Pass Filter.

QUESTIONS:
1. Define Filter?
2. What are the types of Filters
3. Define LPF & HPF
4. What is the difference between chebyshey and butter worth filter?
5. How to get the ideal characteristics of filter?

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Experiment No: 5
DESIGN AND VERIFICATION OF
MONOSTABLE AND ASTABLE MULTIVIBRATORS USING 555 IC

AIM: To observe the output waveform of Monostable and Astable multivibrators

using 555 IC.

APPARATUS:
Bread Board
CRO (20/30MHz)
Connecting wires

COMPONENTS:

555 IC, Resistors (10K-1) and Capacitors as per the Design

CIRCUIT DIAGRAM:
MONOSTABLE MULTIVIBRATOR

VCC=5V Vi
R 8 4
2 time
7 Trigger i/p Vo
LM 555
6
3
C 1 5 CRO
0.01f time
TON
(1.1 RC)

Fig. 5.1.a Monostable Multivibrator Fig. 5.1.b : Model waveform

GND 1 8 +VCC
NE555

TRIGGER 2 7 DISCHARGE

OUTPUT 3 6 THRESOLD
RESET 4 5 CONTOL VOLTAGE

Fig 5.1.c Pin diagram

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ASTABLE MULTIVIBRATOR
VCC=5V
RA 8 4
3
RB 3 7
RB
6
555
5
5
C CRO
2 51 5 0.01f

Fig. 5.2 .a Astable Multivibrator

0.69(RA+RB)C
GND 1 8 +VCC

NE555
TC
TRIGGER 2 7 DISCHARGE

OUTPUT 3 6 THRESOLD
TD
RESET 4 5 CONTOL VOLTAGE
0.69RBC

Fig. 5.2.b Model waveform Fig. 5.2.c Pin diagram

THEORY:
MONOSTABLE MULTIVIBRATOR:

A Monostable multivibrator is also called as a one-shot multivibrator is a pulse-

generating circuit in which the duration of the pulse is determined by the RC network
connected externally to the 555 timer. In a stable state the output of the circuit is zero
or at logic-low level.

When an external trigger pulse is applied, the output is forced to go high (Vcc). The
time the output remains high is determined by the external RC network connected to
the timer. At the end of the timing interval, the output automatically reverts back to its
logic low stable state. The output stays low until the trigger pulse is again applied.
Then the cycle repeats. The monostable multivibrator has only the stable state.

The applications for the monostable multi vibrator are frequency divider and pulse
stretcher

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DESIGN:
Design a Monostable Multivibrator using 555IC to produce an Output Pulse
width of 10msec.
1. Let R=10KΩ
Tp
2. Calculate the value of C using the formula C 
1.1R
ASTABLE MULTIVIBRATOR:
An Astable multivibrator, often called as free-running multivibrator, is a rectangular-
wave-generating circuit. This circuit does not require an external trigger to change the
stable of the output, hence the name free-running. However the time during which the
output is either high or low is determined by two resistors and a capacitor. Which are
externally connected to the 555 timer.

The applications for astable multivibrator are (1) Square-wave oscillator (2) Free-
running ramp generator.

DESIGN:
Design an Astable Multivibrator using 555IC to produce an output pulse with a
positive pulse width (Tc) = 0.421msec and a a negative pulse width (Td) =
0.269msec.
Let Tc = 0.69 (RA+RB) C eq. 1,
where Tc is the time during which the output is high.
Let Td = 0.69 RBC eq. 2,
where Td is the time during which the output is low
Calculate T = Tc+Td
1. Select C = 0.1 F.
2. Calculate RB using Equation 2
3. Using the results in steps1, 2, calculate RA using eq. 1

PROCEDURE:
MONOSTABLE MULTIVIBRATOR:

1. Connect the circuit as shown in the Fig.5.1.a, by using the component as per
design.
2. Apply the Trigger pulse at Pin no 2. Observe the output waveform at pin no 3.
3. Calculate the time during which the output remains high (tp or tonor Tp)
4. Compare it with the theoretical value.

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OBSERVATIONS:
1. Triggering Pulse:
Amplitude= Frequency=
2. Output wave:
Amplitude= Ton= Tof=
ASTABLE MULTIVIBRATOR:
1. Connect the circuit as shown in the Fig. 5.2.a
2. Select the component values as per design.
3. Observe the output waveform at pin no 3.
4. Calculate the time during which the output is high and output is low. Compare it
with theoretical values.
5. Calculate the % duty cycle using the formula (Tc / T)*100. Compare it with
theoretical value.

OBSERVATIONS:
[Link] wave:
Amplitude= Frequency= Tc= Td=
RESULT & ANALYSIS:
The output of Monostable multivibrator and Astable Multivibrator using 555IC are
observed. It is also observed that practical value of the time during which the output
remains high is same as theoretical value.

CONCLUSIONS:
It can be concluded that, if the MMV is once triggered, its output will remain in the
high state until the set time elapses. The output will not change its state even if an
input trigger is applied again during this time interval Tp. Astable Multivibrator can
be concluded that by changing the values of the Components (i.e., R A, RB and C),the
Pulse widths will be changed.

QUESTIONS:
1. What is the function of a multi vibrator?
2. What are the types of multi vibrator?
3. How does 555 IC acts as a timer?
4. What is the supply voltage range of 555 IC?
5. What are the important features of 555 timer?
6. What are the basic modes in which 555 timer operates?
7. What are the differences between the two operating modes of 555 timer?
8. Which application uses 555 timer as astable multivibrator?
Experiment No : 6
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DESIGN AND VERIFICATION OF SCHMITT TRIGGER

AIM: To design and observe the output of Schmitt trigger using 741 & 555 ICs

APPARATUS:
1. Oscilloscope (20/30MHZ)
2. Power supply (0-30V)
3. Signal generator (0-1MHz)
4. Bread Board
5. Resistors 100K-2
6. Resistors 10KΩ-1,50K-1
7. Op-amp 741IC – 1No.

CIRCUIT DIAGRAM:
+VCC
ROM  R1R 2 +15V
7
- 6
V0
+
-15V
3 4
+

Vin -VEE RL
Vlt
10K

R2=50K

R1=100

Fig. 6.1. Schmitt Trigger using 741 OP-Amp

V cc

R1
100kohm 8 4
6 3 Output
Vi Vcc/2 555
Input 2
R2 5
1
100kohm
0.01micro farad

Fig. 6.2. Schmitt Trigger using 555 IC

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MODEL WAVEFORMS:
Vin
Vp
- Vut
0V
t
Vln - V
p

V0
+VSAT

0V
t
-VSAT

Fig. 6.3. Input and output wave forms

Vo
+Vsat

+V
ut

+V
It

Vin

Hysteresis voltage
(V -V )
ut it

-Vsat

Fig. 6.4 Vo versus Vin Plot of the Hysterisis Voltage

THEORY:

A) SCHMITT TRIGGER USING 741 IC:

Fig. 6.1 shows an inverting comparator with positive feedback. This circuit converts
an irregular –shaped waveform to a square wave or pulse. The circuit is known as the
Schmitt trigger or squaring circuit.

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The input voltage Vin triggers (changes the state of) the output V 0 every time it
exceeds certain voltage levels called the upper threshold voltage Vut and lower
threshold voltage Vlt, as shown in Fig. 6.3.

In Fig. 6.1, these threshold voltages are obtained by using the voltage divider R 1-R2,
where the voltage across R1 is fed back to the (+) input. The voltage across R 1 is a
variable reference threshold voltage that depends on the value and polarity of the
output voltage V0. When V0 = +Vsat, the voltage across R1 is called the upper threshold
voltage, Vut. The input voltage Vin must be slightly more positive than V ut in order to
cause the output Vo to switch from +Vsat to –Vsat. As long as Vin < Vut, Vo is at +Vsat.
Using the voltage-divider rule,
R1
Vut    V sat  eq. 1a
R1  R 2
On the other hand, when V0 = -Vsat, the voltage across R1 is referred to as the lower
threshold voltage, Vlt. Vin must be slightly more negative than Vlt in order to cause V0
to switch from –Vsat to +Vsat. In other words, for Vin values greater than Vlt, V0 is at –
Vsat. Vlt is given by the following equation:
R1
Vlt    V sat  eq. 1b
R1  R 2
Thus, if the threshold voltage Vut and Vlt are made larger than the input noise voltages,
the positive feedback will eliminate the false output transitions. Also, the positive
feedback, because of its regenerative action, will make V0 switch faster between +Vsat
and –Vsat. In [Link] ROM  R1R2 is used to minimize the offset problems.

Fig.6.3 shows that the output of the Schmitt trigger is a square wave when the input is
a sine wave. A non-inverting comparator is used as a Schmitt trigger. When the input
is a triangular wave, the output of the Schmitt trigger is a square wave, where as if the
input is a saw-tooth wave, the output is a pulse waveform.

The comparator with positive feedback is said to exhibit hysteresis, a dead-band

condition. That is, when the input of the comparator exceeds Vut, its output switches
from +Vsat to –Vsat and reverts back to its original state, +V sat, when the input goes
below Vlt., See Fig. 6.4

The Hysteresis voltage is equal to the difference between Vut and Vlt.
Therefore,
Vhy = Vut -Vlt.

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R1
   Vsat    Vsat   eq. 2
R1  R2
ANALYSIS OF THE CIRCUIT 1A:
For 741,the maximum output voltage swing is ±[Link] is +V sat=14V and -Vsat=
-14V.
From eq. 1a &1b,
100
Vut    14  27.5mV
5100
100
Vlt    14  27.5mV
5100

The Hysterisis Voltage=55mV.

B) SCHMITT TRIGGER USING 555:

The use of 555 timer as a Schmitt Trigger is shown in Fig. 6.2. Here the two internal
V
comparators are tied together and externally biased at CC through R1 and R2. Since
2
2 1
the upper comparator will trip at VCC and lower comparator at VCC, the bias
3 3
provided by R1 and R2 is centered within these two thresholds. Thus, a sine wave of
V 2 V
sufficient amplitude (> CC  VCC  CC ) to exceed the reference levels causes the
6 3 2
internal flip-flop to alternately set and reset, providing a square wave output as shown

in Fig.6.3. It may be noted that unlike conventional multi vibrator, no frequency

division is taking place and the frequency of square wave remains the same as that of
input signal.

PROCEDURE:
1. Connect the circuit as shown in Fig.6.1. & Fig.6.2
2. Apply a sinusoidal wave with peak voltage greater than the designed voltage (Ut).
3. Observe the waveform on CRO.
4. Note that, when input sinusoidal voltage is more than V(U t), the output changes
from –Vsat to +Vsat.. When Vin is less than V(Lt) the output changes from +V sat to –
Vsat.
[Link] the output waveform on CRO.
[Link] the CRO in XY Mode[Input signal on Channel1& output signal on Channel2].
Then we can observe the Hysterisis Voltage Curve on the CRO.
From this Note down VUT and VLT. These are the extreme points of the curve on X-
axis. (Extreme Left and Extreme right)
[Link] the waveforms on graph sheets.
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8. Obtain the V(Ut) and V(Lt) from graph and compare them with the following
theoretical values.
 R1 
V(Ut) =   *(+Vsat)
  R1  R2  
 R1 
V(Lt) =   *(-Vsat)
  R1  R2  
9. Note down the Hysterisis voltage Vhy = Vut – VLt.
OBSERVATIONS:- (for 741 op amp and 555 timer)

INPUT:- Amplitude =
Output:- +Vsat = ; -Vsat =
Frequency Vut = ; Vlt =

RESULT & ANALYSIS: Hence the output of Schmitt trigger using 741 & 555 IC’s
is observed.

CONCLUSIONS:

From the Hysteresis voltage curve, it can be observed that, the top and bottom
extremes are +Vsat and –Vsat.
So we can conclude that the Hysteresis voltage curve is existing, in between +V sat and
–Vsat on Y-axis. On X-axis Hysteresis voltage curve is existing in between Vut and VLt.

QUESTIONS:
1. What are the two threshold levels at which the comparators of 555 timer
operates?
2. Define LTP and UTP.
3. In which operating modes 555 timer can be used as Schmitt trigger?

Experiment No: 7
VERIFICATION OF 4 BIT DAC USING OP AMP

AIM: To observe the output of a Digital to analog converter using

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1) Binary weighted resistors

2) R and 2R resistors for different input combinations

APPARATUS:

1. Op-amp IC741 1No.

2. Resistors(R) 10 K 4 No.
2R 20K  6 No.
5K 1No
2.5K 1No
1.25 K 1No
3. Potentiometer 1No.
4. Multimeter 1No

CIRCUIT DIAGRAM: RF= 1K

b0 +15V
R = 10k
- 7
b1 2
R/2
LM741 VO
6
3
b2 R/4 + 4

b3
-15V
R/8

+5V

Fig 7.1 D/A Converter with Binary weighted resistors

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Fig 7.2 D/A Converter with R /2R resistors

THEORY:
A Digital-to-Analog Converter is used when a Binary output from a digital system
must be converted to some equivalent Analog voltage or Current. The Binary output
from a digital system is difficult to interpret. However a DAC makes the
interpretation easier. The function of DAC is exactly opposite to that of ADC.
Advantages:1)It is simpler in construction when compared to ADC 2)It can be used to
form the ADC.

Types of D/A Converters:

There are two types of DACs available
1. D/A converter with Binary –weighted Resistors
2. D/A converter with R and 2R resistors.
i.e., A D/A converter in its simplest form uses an op-amp and either binary weighted
resistors or R and 2R resistors.
1) D/A CONVERTER WITH BINARY –WEIGHTED RESISTORS
The schematic of a DAC is shown in Fig.7.1. The input is an n-bit binary word D and
is combined with a reference voltage VR to give an analog output signal. The output of
a DAC can be either a voltage or current. Theory o/p voltage
V0 = K VFS (b12-1+b22-2+…..+bn2-n) eq.1
Where V0 = output voltage
VFS = full scale output voltage
K = scaling factor usually adjusted to unity
b1b2…..bn = n-bit binary fractional word with the decimal point located at the left
b1 = most significant bit (MSB) with a weight of VFS/2
bn = least significant bit (LSB) with a weight of VFS/2n
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+ VR _

(MSB) I0 +
b1
Binary V0
bn-1 DAC
Word B
bn (LSB)

Fig. 7.3 Schematic of a DAC

OPERATION:
The Fig.7.1 shows D/A converter using op-amp and binary weighted resistors.
Although in this Fig.. the op-amp is connected in the inverting mode it can also be
connected in the non-inverting mode, Since the number of binary inputs is four, the
converter is called 4 bit (binary digit) converter .

Because there are 16(24) combinations of binary inputs for b0 through b3 an analog
output should have 16 possible corresponding values. In Fig 7.1, four switches(b0to
b3) are used to stimulate the binary inputs ;in practice , a 4 bit binary counter such as
7493 may be used instead .

When switch b0 is closed (connected to +5V),the voltage across R is 5V because

V2=V1 =0V. Therefore R is 5V/10k= 0.5mA .However , the input bias current IB is
negligible; hence the current through feedback resistor RF is also 0.5 mA ,which ,in
turn produces an output voltage of –(1k)(0.5mA) = -[Link] that the op-amp is
working as a current –to- voltage converter .

Now suppose that switch b1 is closed and b0 is opened .This action connects R/2 to
the positive supply of +5V, causing twice as much current (1mA) to flow through R F
which in turn doubles the output voltage .Thus the output voltage Vo is -1V When b1
switch is closed .

Similarly, if both switches b0 and b1 are closed, the current through R F will be 1.5
mA, which will be converted to an output voltage of –(1k)(1.5mA)= -1.5V.

Thus, depending on whether switches b0 to b3 are open or closed, the binary weighted
currents will be set up in input resistors .The sum of these currents is equal to the
current through RF, which in turn is converted to a proportional output voltage. When
all the switches are closed, obviously the output will be maximum .The output voltage
equation is given by

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 b0 b1 b2 b3 
Vo = - RF     
 R R / 2 R / 4 R /8
Where each of the inputs b3 ,b2 ,b1 and b0 may either be high (+5V) or low (0V).
If a graph is drawn between Analog outputs versus possible combinations of inputs
.The output is a negative going staircase waveform will 15 steps of -0.5V each in
practice , however the steps may not all be the same size because of the variations of
the logic high voltage level .Notice that the size if the steps depends on the value of
RF Therefore a desired step can be obtained by selecting a proper value of R F
provided that the maximum output voltage does not exceed the saturation levels of an
op-amp .For accurate operation of the D/A converter precision metal film resistors are
recommended

DRAW BACKS: The problem with D/A converter is that it requires binary weighted
resistors which may not readily available, especially if the number of inputs more than
four .An alternative is to use R and 2R resistors for the D/A converter since it
requires only two sets of precision resistance values
D/A CONVERTER WITH R AND 2R
Fig15.2 shows D/A converter with R and 2R resistors. As before, the binary inputs are
simulated by switches b0 through b3 and the output is proportional to the binary
inputs. Binary inputs can be in either the high (+5v) or low (0v) state. Assume that the
most significant bit (MSB) switch b3 is connected to +5V and other switches are
connected to ground, as in Fig.7.2.
Thevenizing the circuit to the left of switch b3. Thevenin’s equivalent resistance R TH
is
RTH = [{[(2R║ 2R +R) ║ 2R]+R}║ 2R]+R
= 2R= 20K RF=20KΩ

The resultant circuit is shown in Fig 7.4.

+15V

RTH=2R
-

Vo
2R +
RL=10KΩ

+15V

+5V

Fig. 7.4 Equivalent Circuit when b3 is high and b0,b1,b2 are low

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In this Fig. the (-) input is at virtual ground (V 2 0V) ; therefore , the current through
5V
RTH (= 2R) is zero However , the current through 2R connected to +5V is =
20 K
0.25mA .The same current flows through RF and in turn produces the output voltage
Vo = -(20k) (0.25mA) = - 5V
Using the same analysis, the output voltage corresponding to all possible
combinations of binary inputs can be calculated .The maximum or full –scale output
of -9.375 V is obtained when all the inputs are high .The output voltage equation can
be written as
 b3 b 2 b1 b0 
V o = - RF     
 2 R 4 R 8 R 16 R 
Where each of the inputs b3, b2, b1 and b0 may be either high(+5V) or low (0V)
The great advantage of the D/A Converter of Fig. 7.2 is that it requires only two sets
of precision resistance values; nevertheless, it requires more resistors and is also more
difficult to analyze than the binary –weighted resistor type.
As the number of binary inputs is increased beyond four, both D/A converter circuit
get complex and their accuracy degenerates. Therefore, in critical applications an
integrated circuit specially designed as D/A converter should be used.

PROCEDURE:

1. Connect the Circuit as shown in Fig.. 7.1 or 7.2

2. Connect the inputs b0,b1,b2,b3 to either +5V or to Ground (Zero) that means
take the different combinations of the inputs from 0000 to 1111.
3. Observe the output of op-amp 741(for every input combination) with DMM.
4. For each value of input variation measure the output voltage with DMM and
tabulate the values.

OBSERVATIONS:
[Link] Digital Inputs Analog Output
1 0 0 0 0
2 0 0 0 1
3 0 0 1 0
4 0 0 1 1
5 0 1 0 0
6 0 1 0 1
7 0 1 1 0
8 0 1 1 1
9 1 0 0 0
10 1 0 0 1
11 1
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12 1 0 1 1
13 1 1 0 0
14 1 1 0 1
15 1 1 1 0
16 1 1 1 1
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RESULT:
Hence the output of a Digital to analog converter using “(1)Binary weighted resistors
(2) R and 2R resistors” for different input combinations are observed.

CONCLUSIONS:
It can be concluded that the output of the DAC is Equivalent to the given input
combination.

QUESTIONS:
1. What is DAC?
2. Mention the types of DAC techniques?
3. Write application of R-2R Ladder?
4. What is the resolution of DAC?
5. What is the resolution of 4 bit DAC?

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Experiment No: 8
VERIFICATION OF ADC OPERATION USING OP AMP

AIM: To verify the operation of an analog to digital converter IC 741.

APPARATUS: 1. IC 741.
2. ADC Trainer Kit
3. Connecting wires

THEORY:

The most commonly used method for Analog to Digital conversion is the
successive approximation method. It has a fixed conversion time and is faster than the
dual slope A/D conversion. The successive approximation converter is however
slower than the flash converter. The main components of a successive approximation
converter are the successive approximation register (SAR), a digital to analog
converter and a comparator.

Fig 8.1 Successive Approximation type Analog to Digital Converter

The main part of the circuit is the 8-bit SAR, whose output is given to an 8-bit D/A
converter. The analog output Va of the D/A converter is then compared to an analog
signal Vin by the comparator. The output of the comparator is a serial data input to the
SAR. Till the digital output (8 bits) of the SAR is equivalent to the analog input
Vin, the SAR adjusts itself. The 8-bit latch at the end of conversation holds onto the
resultant digital data output.

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WORKING

At the start of a conversion cycle, the SAR is reset by making the start signal (S) high.
The MSB of the SAR (Q7) is set as soon as the first transition from LOW to HIGH is
introduced. The output is given to the D/A converter which produces an analog
equivalent of the MSB and is compared with the analog input Vin.

If comparator output is LOW, D/A output will be greater than Vin and the MSB will be
cleared by the SAR. If comparator output is HIGH, D/A output will be less than
Vin and the MSB will be set to the next position (Q7 to Q6) by the SAR. According to
the comparator output, the SAR will either keep or reset the Q6 bit. This process goes
on until all the bits are tried. After Q0 is tried, the SAR makes the conversion
complete (CC) signal HIGH to show that the parallel output lines contain valid data.
The CC signal in turn enables the latch, and digital data appear at the output of the
latch. As the SAR determines each bit, digital data is also available serially. As shown
in the figure above, the CC signal is connected to the start conversion input in order to
convert the cycle continuously.

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Experiment No: 9
Verification of 3 to 8 Decoder operation

AIM: To verify the operation of a 3 to 8 decoder using IC 74138.

APPARATUS: 1. IC 74138.
2. Digital IC Trainer Kit
3. Connecting wires

THEORY:

A decoder is a device which does the reverse of an encoder, undoing the encoding so
that the original information can be retrieved. The same method used to encode is
usually just reversed in order to decode.

In digital electronics this would mean that a decoder is a multiple-input, multiple-

output logic circuit that converts coded inputs into coded outputs, where the input and
output codes are different. e.g. n-to-2n, BCD decoders.

Enable inputs must be on for the decoder to function, otherwise its outputs assume a
single "disabled" output code word. Decoding is necessary in applications such as
data multiplexing, 7 segment display and memory address decoding.

The simplest decoder circuit would be an AND gate because the output of an AND
gate is "High" (1) only when all its inputs are "High".

A slightly more complex decoder would be the n-to-2 n type binary decoders. These
type of decoders are combinational circuits that convert binary information from 'n'
coded inputs to a maximum of 2n unique outputs. We say a maximum of 2n outputs
because in case the 'n' bit coded information has unused bit combinations, the decoder
may have less than 2n outputs. We can have 2-to-4 decoder, 3-to-8 decoder or 4-to-16
decoder. We can form a 3-to-8 decoder from two 2-to-4 decoders (with enable
signals).

Similarly, we can also form a 4-to-16 decoder by combining two 3-to-8 decoders. In
this type of circuit design, the enable inputs of both 3-to-8 decoders originate from a
4th input, which acts as a selector between the two 3-to-8 decoders. This allows the
4th input to enable either the top or bottom decoder, which produces outputs of D(0)
through D(7) for the first decoder, and D(8) through D(15) for the second decoder.

It is important to note that a decoder that contains enable inputs is also known as a
decoder-demultiplexer. Thus, we have a 4-to-16 decoder produced by adding a 4th
input shared among both decoders, producing 16 outputs.

The DM74LS138 decodes one-of-eight lines, based upon the conditions at the three
binary select inputs and the three enable inputs. Two active-low and one active-high
enable inputs reduce the need for external gates or inverters when expanding. A 24-
line decoder can be implemented with no external inverters, and a 32-line decoder

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requires only one inverter. An enable input can be used as a data input for
demultiplexing applications. The DM74LS139 comprises two separate two-line-to-
four line Decoders in a single package. The active-low enable input can be used as a
data line in demultiplexing applications. All of these decoders/demultiplexers feature
fully buffered inputs, presenting only one normalized load to its driving circuit. All
inputs are clamped with high-performance Schottky diodes to suppress line-ringing
and simplify system design.

PROCEDURE:
1. The IC is placed on the board in the digital IC trainer kit.
2. Then a supply of 5Volts is provided to the V cc pin (Pin No.16) of the IC from
the RPS and the Ground pin of the IC (Pin No.8) is connected to the ground
terminal.
3. Then IC is verified for its performance by giving appropriate values i.e Logic
0 ( 0 Volts- Ground) and Logic 1( 5 Volts-Supply) to the inputs of the ICs and
the respective Truth tables are verified
4. The outputs are observed at the respective pins of the ICs.

Fig 9.1 74LS138 connection diagram

Fig 9.2 74LS138 logic diagram

FUNCTIONAL TABLE FOR DM74LS138

Inputs
Outputs
Enable Signal
~G2B ~G2A G1 C B A ~Y0 ~Y1 ~Y2 ~Y3 ~Y4 ~Y5 ~Y6 ~Y7
H X X X X X H H H H H H H H
X H X X X X H H H H H H H H
X X 0 X X X H H H H H H H H
L L H L L L L H H H H H H H
L L H L L H H L H H H H H H

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L L H L H L H H L H H H H H
L L H L H H H H H L H H H H
L L H H L L H H H H L H H H
L L H H L H H H H H H L H H
L L H H H L H H H H H H L H
L L H H H H H H H H H H H L

RESULT & ANALYSIS: The performance of the 3 - 8 decoder has been verified
according to the truth tables by applying various sets of data inputs.

CONCLUSION: Conclusion can be made on comparison of 3 to 8 Decoder

functionality in hardware results and the truth table.

QUESTIONS:

1. What is a decoder?
2. Compare Encoder and Decoder?
3. Design a 4X16 decoder using two 3X8 decoders.
4. Write the applications of decoders.

Experiment No: 10
Verification of Priority Encoder (74148) operation

AIM: To verify the operation of 8 to 3 Priority Encoder using IC 74148.

APPARATUS: 1. IC 74148.
2. Digital IC Trainer Kit
3. Connecting wires

THEORY:

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Encoder An encoder is a digital function that produces a reverse operation from that
of a decoder. An Encoder has 2n (or less) inputs lines and n output lines. The output
lines generate the binary code for the 2n inputs variables.

PRIORITY ENCODER: A simple encoder may produce an erroneous output if more

than one of its inputs is high. A Priority Encoder is one that responds to just one input
among those that may be simultaneously high, in accordance with some priority
system. The most common priority system is based on the relative magnitudes of the
inputs: whichever decimal input is largest, is the one that is encoded.

The MC54/74F148 provides three bits of binary coded output representing the
position of the highest order active input, along with an output indicating the presence
of any active input. It is easily expanded via input and output enables to provide
priority encoding over many bits.
 Encodes Eight Data Lines in Priority
 Provides 3-Bit Binary Priority Code
 Input Enable Capability
 Signals When Data Present on Any Input
 Cascadable for Priority Encoding of n Bits

FUNCTIONAL DESCRIPTION: The 74148 8-input priority encoder accepts data

from eight active LOW inputs (I0–I7) and provides a binary representation on the
three active LOW outputs. A priority is assigned to each input so that when two or
more inputs are simultaneously active, the input with the highest priority is
represented on the output, with input line 7 having the highest priority.

A HIGH on the Enable Input (E1) will force all outputs to the inactive (HIGH) state
and allow new data to settle without producing erroneous information at the outputs.
A Group Signal output (GS) and Enable Output (EO) are provided along with the
three priority data outputs (A2, A1, A0). GS is active LOW when any input is LOW;
this indicates when any input is active. EO is active LOW when all inputs are HIGH.
Using the Enable Output along with the Enable Input allows cascading for priority
encoding on any number of input signals. Both EO and GS are in the inactive HIGH
state when the Enable Input is HIGH.

PROCEDURE:
1. The IC is placed on the board in the digital IC trainer kit.
2. Then a supply of 5Volts is provided to the V cc pin (Pin No.16) of the IC from
the RPS and the Ground pin of the IC (Pin No.8) is connected to the ground
terminal.
3. Then IC is verified for its performance by giving appropriate values i.e Logic
0 ( 0 Volts- Ground) and Logic 1( 5 Volts-Supply) to the inputs of the ICs and
the respective Truth tables are verified
4. The outputs are
observed at the
respective pins of
the ICs.

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Fig

74LS148

10.1 74LS148 connection diagram

Fig 10.2 74LS148 logic diagram

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RESULT & ANALYSIS: The performance of the 8 to 3 Priority encoder have been
verified according to the truth tables by applying various sets of data inputs.

CONCLUSION: Conclusion can be made on comparison of priority encoder

functionality in hardware results and truth table.

QUESTIONS:

1. What is an encoder?
2. What is priority encoder?
3. What are the differences between an encoder and priority encoder?
4. Write the applications of priority encoder.

Experiment No: 11
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Performance of 8x1 Multiplexer and 2x4 De-Multiplexer

AIM: To study the performances of 8x1 multiplexer using digital IC 74151 and
2x4 De-Multiplexer using digital IC 74155.
APPARATUS: 1. IC74151 (8 X1 Multiplexer)
2. IC74155 (2X4 De-Multiplexer)
3. Digital IC Trainer Kit
4. Connecting wires

THEORY 8 X1 MULTIPLEXER:

A multiplexer is a device that performs multiplexing i.e it selects one of many analog
or digital input signals and outputs that into a single line.

An electronic multiplexer makes it possible for several signals to share one expensive
device or other resource, for example one A/D converter or one communication line,
instead of having one device per input signal.

A multiplexer performs the function of selecting the input on any one of 'n' input lines
and feeding this input to one output line.

Multiplexers are used as one method of reducing the number of integrated circuit
packages required by a particular circuit design. This in turn reduces the cost of the
system.
If ‘n’ are the number of select lines, then ‘2 n’ inputs may be multiplexed on to a single
output line

Assume that we have four lines, C0, C1, C2 and C3, which are to be multiplexed on a
single line, Output (f). The four input lines are also known as the Data Inputs.

Since there are four inputs, we will need two additional inputs to the multiplexer,
known as the Select Inputs, to select which of the C inputs is to appear at the output.
Call these select lines A and B.

Fig 11.1 Gate implementation of a 4-line to 1-line multiplexer

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The gate implementation of a 4-line to 1-line multiplexer is shown above.

The circuit symbol for the above multiplexer is:

Fig 11.2 Logic symbol for 4-line to 1-line multiplexer

Similarly other multiplexers are also designed.

THEORY FOR 2X4 DE-MULTIPLEXER:

A demultiplexer is a device which essentially performs the opposite operation to the

MUX. The demultiplexer is the inverse of the multiplexer, in that it takes a single data
input and n address inputs. It has 2n outputs. The address input determine which data
output is going to have the same value as the data input. The other data outputs will
have the value 0.
That is, it functions as an electronic switch (or data distributor) to route an incoming
data signal to one of several outputs.

Demultiplexers take one data input and a number of selection inputs, and they have
several outputs. They forward the data input to one of the outputs depending on the
values of the selection inputs. Demultiplexers are sometimes convenient for designing
general purpose logic, because if the demultiplexer's input is always true, the
demultiplexer acts as a decoder. This means that any function of the selection bits can
be constructed by logically OR-ing the correct set of outputs.

The below F igure1 shows the logic symbol for the 1-line-to-4-line demultiplexer
circuit and table is the associated Truth table. The corresponding logic circuit
implementation is then shown in Figure.

Figure 11.3 : Logic symbol for 1-line-to-4-line demultiplexer

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Demultiplexer Function Table

Da Address Output
ta S1 S0 Y0 Y1 Y2 Y3
D 0 0 D 0 0 0
D 0 1 0 D 0 0
D 1 0 0 0 D 0
D 1 1 0 0 0 D

Fig 11.4 Gate implementation of 1-line-to-4-line Demultiplexer

PROCEDURE:

1. The IC is placed on the board in the digital IC trainer kit.

2. Then a supply of 5Volts is provided to the V cc pin (Pin No.14) of the IC from
the RPS and the Ground pin of the IC (Pin No.7) is connected to the ground
terminal.
3. Then each IC is verified for its performance by giving appropriate values i.e
Logic 0 ( 0 Volts- Ground) and Logic 1( 5 Volts-Supply) to the inputs of the
ICs and the respective Truth tables are verified.
4. The outputs are observed at the respective pins of the ICs.

74LS151

11.5 74LS151 connection diagram

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11.6 74LS151 Logic diagram

Functional Table for IC74151

Enable Select Lines Output

En_l S2 S1 S0 Z Z
1 X X X 0 1
0 0 0 0 I0
Ī0
0 0 0 1 I1
Ī1
0 0 1 0 I2
Ī2
0 0 1 1 I3
Ī3
0 1 0 0 I4
Ī4
0 1 0 1 I5
Ī5
0 1 1 0 I6
Ī6
0 1 1 1 I7 Ī7

74155
PROCEDURE:

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1. The IC is placed on the board in the digital IC trainer kit.

2. Then a supply of 5Volts is provided to the V cc pin (Pin No.16) of the IC from
the RPS and the Ground pin of the IC (Pin No.8) is connected to the ground
terminal.
3. Then each IC is verified for its performance by giving appropriate values i.e
Logic 0 ( 0 Volts- Ground) and Logic 1( 5 Volts-Supply) to the inputs of the
ICs and the respective Truth tables are verified.
4. The outputs are observed at the respective pins of the ICs.

Fig 11.7 74LS155 connection diagram

Fig. 11.8 74LS155 Logic diagram

Functional Table for 74LS155

Inputs Outputs

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Select Strobe Data

1Y0 1Y1 1Y2 1Y3
B A 1G` 1C

X X H X H H H H
L L L H L H H H
L H L H H L H H
H L L H H H L H
H H L H H H H L
X X X L H H H H

RESULT & ANALYSIS: The performance of the IC as 8*1 multiplexers and 2*4
De-Multiplexer have been verified according to the truth tables by applying various
sets of data inputs

CONCLUSION: Conclusion can be made on comparison of 8X1 multiplexers and

2X4 De-Multiplexer functionality in hardware results and truth table.

QUESTIONS:

1. How many 8X1 multiplexers are needed to construct 16X1 multiplexer?

2. Compare decoder with demultiplexer?
3. Design a full adder using 8X1 multiplexer?
4. Implement 16X1 multiplexer using structural model?
5. Write the applications of multiplexer and demultiplexer?
6. Design 32X1 multiplexer using 16X1 multiplexer?

Experiment No: 12
Verification of 4-Bit Comparator operation

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AIM: To verify the operation of a 4 bit comparator using IC 7485.

APPARATUS: 1. IC 7485.
2. Digital IC Trainer Kit
3. Connecting wires
THEORY:

A digital comparator is a hardware electronic device that compares two numbers in

binary form and generates a one or a zero at its output depending on whether they are
the same or not.

Comparators can be used in a central processing unit (CPU) or microcontroller in

branching software. A comparator can be simulated by subtracting the two values (A
& B) in question and checking if the result is zero. This works because if A = B then A
- B = 0.

The operation of a single bit digital comparator can be expressed as a truth table:

Inputs Outputs

A B A<B A=B A>B

0 0 0 1 0

0 1 1 0 0

1 0 0 0 1

1 1 0 1 0

The 74F85 is a 4-bit magnitude comparator that can be expanded to almost any
length. It compares two 4-bit binary, BCD, or other monotonic codes and presents
the three possible magnitude results at the outputs. The 4-bit inputs are weighted (A0–
A3) and (B0–B3) where A3 and B3 are the most significant bits. The operation of the
74F85 is described in the Function Table, showing all possible logic conditions.

The upper part of the table describes the normal operation under all conditions that
will occur in a single device or in a series expansion scheme. In the upper part of the
table the three outputs are mutually exclusive.

In the lower part of the table, the outputs reflect the feed-forward conditions that exist
in the parallel expansion scheme. The expansion inputs IA>B, and IA=B and IA<B
are the least significant bit positions. When used for series expansion, the A>B, A=B
and A<B outputs of the lease significant word are connected to the corresponding
IA>B, IA=B and IA<B inputs of the next higher stage. Stages can be added in this
manner to any length, but a propagation delay penalty of about 15ns is added with
each additional stage.

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For proper operation, the expansion inputs of the least significant word should be tied
as follows: I (A>B) = Low, I (A=B) = High, and I (A<B) = Low.

PROCEDURE:

1. The IC is placed on the board in the digital IC trainer kit.

2. Then a supply of 5Volts is provided to the Vcc pin (Pin No.16) of the IC
from the RPS and the Ground pin of the IC (Pin No.8) is connected to the
ground terminal.
3. Apply the comparing and cascading inputs to corresponding inputs.
4. The outputs are observed at the respective pins of the ICs.

Pin out diagram

Fig. 12.1 74LS85 pinout diagram Fig. 12.2 74LS85 Logic diagram

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Fig. 12.8 74LS85 Connection diagram

Functional table
Comparing Inputs Expansion Inputs Outputs
A3,B3 A2,B2 A1,B1 A0,B0 IA>B IA<B IA=B A>B A<B A=B
A3>B3 X X X X X X H L L
A3<B3 X X X X X X L H L
A3=B3 A2>B2 X X X X X H L L
A3=B3 A2>B2 X X X X X L H L
A3=B3 A2=B2 A1>B1 X X X X H L L
A3=B3 A2=B2 A1<B1 X X X X L H L
A3=B3 A2=B2 A1=B1 A0>B0 X X X H L L
A3=B3 A2=B2 A1=B1 A0<B0 X X X L H L
A3=B3 A2=B2 A1=B1 A0=B0 H L L H L L
A3=B3 A2=B2 A1=B1 A0=B0 L H L L H L
A3=B3 A2=B2 A1=B1 A0=B0 L L H L L H
A3=B3 A2=B2 A1=B1 A0=B0 X X H L L H
A3=B3 A2=B2 A1=B1 A0=B0 H H L L L L
A3=B3 A2=B2 A1=B1 A0=B0 L L L H H L

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RESULT & ANALYSIS: The performance of 4 bit comparator verified according to

the truth tables by applying various sets of data inputs.

CONCLUSION: Conclusion can be made on comparison of 4 bit comparator

functionality in hardware results and truth table.

QUESTIONS:
1. How many 4-bit comparators are needed to construct 12-bit comparator?
2. What does a digital comparator mean?
3. Design a 2-bit comparator using gates?

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Experiment No: 13
Performance of D-Flip Flop

AIM: To verify the performance of D-Flip Flop using digital IC74S74.

APPARATUS: 1. SN74S74
2. Digital IC Trainer Kit
3. Connecting wires

THEORY:.

A flip-flop circuit can be constructed from two NAND gates or two NOR gates. These
flip-flops are shown in Figure 2 and Figure 3. Each flip-flop has two outputs, Q and
Q', and two inputs, set and reset. This type of flip-flop is referred to as an SR flip-flop
or SR latch. The flip-flop in Figure 2 has two useful states. When Q=1 and Q'=0, it is
in the set state (or 1-state). When Q=0 and Q'=1, it is in the clear state (or 0-state).
The outputs Q and Q' are complements of each other and are referred to as the normal
and complement outputs, respectively. The binary state of the flip-flop is taken to be
the value of the normal output.

When a 1 is applied to both the set and reset inputs of the flip-flop in Fig 13.1, both Q
and Q' outputs go to 0. This condition violates the fact that both outputs are
complements of each other. In normal operation this condition must be avoided by
making sure that 1's are not applied to both inputs simultaneously.

Logic diagram

Truth table

Fig 13.1. Basic flip-flop circuit with NOR gates

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Logic diagram

Truth table

Fig 13.2 . Basic flip-flop circuit with NAND gates

The NAND basic flip-flop circuit in Figure 13.2 operates with inputs normally at 1
unless the state of the flip-flop has to be changed. A 0 applied momentarily to the set
input causes Q to go to 1 and Q' to go to 0, putting the flip-flop in the set state. When
both inputs go to 0, both outputs go to 1. This condition should be avoided in normal
operation.

INTRODUCTION - D FLIP-FLOP

The D flip-flop shown in Figure 13.3 is a modification of the clocked SR flip-flop.

The D input goes directly into the S input and the complement of the D input goes to
the R input. The D input is sampled during the occurrence of a clock pulse. If it is 1,
the flip-flop is switched to the set state (unless it was already set). If it is 0, the flip-
flop switches to the clear state.

(a) Logic diagram with NAND gates

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(b) Graphical symbol

(c) Transition table

Fig 13.3. Clocked D flip-flop

The 74F74 is a dual positive edge-triggered D-type flip-flop featuring individual data,
clock, set, and reset inputs; also true and complementary outputs. Set (SD) and reset
(RD) are asynchronous active low inputs and operate independently of the clock
input. When set and reset are inactive (high), data at the D input is transferred to the Q
and Q outputs on the low-to-high transition of the clock. Data must be stable just one
setup time prior to the low-to-high transition of the clock for predictable operation.
Clock triggering occurs at a voltage level and is not directly related to the transition
time of the positive-going pulse. Following the hold time interval, data at the D input
may be changed without affecting the levels of the output.

PROCEDURE:

1. Place the IC on the trainer kit.

2. Apply PRE, CLR, CLK, D inputs to the corresponding inputs.
3. Verify the output at output pins as per the truth table.

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Circuit Diagram:

Fig. 13.4 74LS74 Logic diagram Fig. 13.5 74LS74 Connection diagram

RESULT & ANALYSIS The performance of the D-Flip Flop have been verified
according to the truth tables by applying various sets of data inputs

CONCLUSION: Conclusion can be made on comparison of D-Flip Flop

functionality in hardware results with the truth table.

QUESTIONS:

1. What is the difference between sequential and combinational circuit?

2. Explain the functions of preset and clear inputs in flip-flop.
3. What is the difference between flip-flop and latch?
4. What are the various methods used for triggering flip-flops?
5. Explain level triggered flip-flop.

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Experiment No: 14
Performance of Decade Counter using IC7490

AIM: To verify the performance of Decade Counter using digital IC7490

APPARATUS: 1. IC7490
2. Digital IC Trainer Kit
3. Connecting wires
THEORY:

A binary counter can be constructed from J-K flip-flops by taking the output of one
cell to the clock input of the next. The J and K inputs of each flip-flop are set to 1 to
produce a toggle at each cycle of the clock input. For each two toggles of the first cell,
a toggle is produced in the second cell, and so on down to the fourth cell. This
produces a binary number equal to the number of cycles of the input clock signal.
This device is sometimes called a "ripple through" counter. The same device is useful
as a frequency divider.

Fig. 14.1 Binary counter

Each of these monolithic counters contains four master-slave flip-flops and additional
gating to provide a divide-by two counter and a three-stage binary counter for which
the count cycle length is divide-by-five for the 'LS90 and divide by- eight for the
'LS93. All of these counters have a gated zero reset and the LS90 also has gated set-
to-nine inputs for use in BCD nine's complement applications. To use their maximum
count length (decade or four bit binary), the B input is connected to the QA output.
The input count pulses are applied to input A and the outputs are as described in the
appropriate truth table. A symmetrical divide- by-ten count can be obtained from the
'LS90 counters by connecting the QD output to the A input and applying the input
count to the B input which gives a divide-by-ten square wave at output QA.

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PROCEDURE:
1. The IC is placed on the board in the digital IC trainer kit.
2. Then a supply of 5Volts is provided to the V cc pin (Pin No.5) of the IC and
ground to pin 10.
3. Clock input is applied to 1 and 14 pins
4. The Reset / Set input are connected to corresponding pins
5. The CP1input is externally connected to Q 0 [Link] CPinput
0 receives the
incoming count and the BCD count sequence is obtained at Q0 to Q3.

CIRCUIT DIAGRAM:

Fig. 14.2 74LS90 Logic diagram

Fig. 14.3 74LS90 Connection diagram

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RESULT & ANALYSIS: The performance of the Decade Counter has been verified
according to the truth tables by applying various sets of data inputs.

CONCLUSION: Conclusion can be made on comparison of Decade Counter

functionality in hardware results with the truth table.

QUESTIONS:

1. What is a counter?
2. What is a sequential circuit?
3. Differentiate between synchronous and asynchronous counter?
4. How many no. of flip-flops are required for decade counter?
5. How many no. of flip-flops are required for mod-n counter?

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Experiment No: 15
Performance of Shift Register using IC 7495

AIM: To verify the operation of a Shift Register using IC 7495.

APPARATUS: 1. IC 7495
2. Digital IC Trainer Kit
3. Connecting wires
THEORY:

These 4-bit registers feature parallel and serial inputs, parallel outputs, mode
control, and two clock inputs. The registers have three modes of operation:

Parallel (broadside) load

Shift right (the direction QA toward QD)
Shift left (the direction QD toward QA)

Parallel loading is accomplished by applying the four bits of data and taking the mode
control input high. The data is loaded into the associated flip-flops and appears at the
outputs after the high-to-low transition of the clock-2 input. During loading, the entry
of serial data is inhibited.

Shift right is accomplished on the high-to-low transition of clock 1 when the mode
control is low; shift clock 2 when the mode control is high by connecting the output of
each flip-flop to the parallel input of the previous flip-flop (Q D to input C, etc.) and
serial data is entered at input D. The clock input may be applied commonly to clock 1
and clock 2 if both modes can be clocked from the same source. Changes at the mode
control input should normally be made while both clock inputs are low; however,
conditions described in the last three lines of the function table will also ensure that
register contents are protected.

PROCEDURE:

1. The IC is placed on the board in the digital IC trainer kit.

2. Then a supply of 5Volts is provided to the V cc pin (Pin No.14) of the IC from
the RPS and the Ground pin of the IC (Pin No.7) is connected to the ground
terminal.
3. Apply the clk inputs cp1,cp2 to pin 9 and 8 respectively.
4. The outputs are observed at the respective pins of the ICs.

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CIRCUIT DIAGRAM:

Pin configuration:

Fig. 15.1 74LS95 Connection diagram Fig. 15.2 74LS95 Logic diagram

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RESULT & ANALYSIS: The performance of the Shift Register have been verified
according to the truth tables by applying various sets of data inputs.

CONCLUSION: Conclusion can be made on comparison of Shift Register

functionality in hardware results and the truth table.

QUESTIONS:

1. What is a register
2. What is a shift register?
3. What is a parallel shift register
4. Write some applications of shift register?
5. What are the different modes of operations in a shift registers.

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Experiment No: 16
Performance of Universal Shift Register (74194/195)

AIM: To verify the performance of Universal Shift Register using IC 74194.

APPARATUS: 1. IC74194
2. Digital IC Trainer Kit
3. Connecting wires

THEORY:

The purpose of the parallel-in/ parallel-out shift register is to take in parallel data,
shift it, then output it as shown below. A universal shift register is a do-everything
device in addition to the parallel-in/ parallel-out function.

Fig 16.1 Parallel-in Parallel-out shift register with four stages

The M54/74HC194 is a high speed CMOS 4BIT PIPO SHIFT REGISTER fabricated
in silicon gate C2MOS technology. It has the same high speed performance of LSTTL
combined with true CMOS low power consumption. This SHIFT REGISTER is
designed to incorporate virtually all of the features a system designer may want in a
shift register. It features parallel inputs, parallel outputs, right shift and left shift serial
inputs, clear line. The register has four distinct modes of operation: PARALLEL
(broadside) LOAD; SHIFT RIGHT (in the direction QA QD); SHIFT LEFT;
INHIBITCLOCK (do nothing). Synchronous parallel loading is accomplished by
applying the four data bits and taking both mode control inputs, S0 and S1 high. The
data are loaded into their respective flip-flops and appear at the outputs after the
positive transition of the CLOCK input. During loading, serial data flow is inhibited.
Shift right is accomplished synchronously with the rising edge of the clock pulse
when S0 is high and S1 is low. Serial data for this mode is entered at the SHIFT
RIGHT data input. When S0 is low and S1 is high, data shifts left synchronously and
new data is entered at the SHIFT LEFT serial input. Clocking of the flip-flops is

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inhibited when both mode control inputs are low. The mode control inputs should be
changed only when the CLOCK input is high. All inputs are equipped with protection
circuits against static discharge and transient excess voltage.

PROCEDURE:

1. The IC is placed on the board in the digital IC trainer kit.

2. Then a supply of 5Volts is provided to the V cc pin (Pin No.16) of the IC and
ground to pin 8.
3. Apply the clk, clr and load inputs to the corresponding pins.
4. Then each IC is verified for its performance by giving appropriate values i.e
Logic 0 (0 Volts- Ground) and Logic 1(5 Volts-Supply) to the inputs of the ICs
and the respective Truth tables are verified.
5. The outputs are observed at the respective pins of the ICs.

FUNCTIONAL TABLE:

CIRCUIT DIAGRAM:

Fig. 16.2 74LS195 Logic diagram

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RESULT & ANALYSIS: The performance of Universal Shift Register has been
verified according to the truth tables by applying various sets of data inputs.

CONCLUSION: Conclusion can be made on comparison of Universal Shift Register

functionality in hardware results and the truth table.

QUESTIONS:
1. Write some applications of universal shift register.
2. What is difference between ring and Johnson counter?
3. What are the specific functions in 74194 universal shift register?

Design Experiments
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Experiment No: 17

VOLTAGE REGULATION CHARACTERISTICS OF LM 723 IC

AIM: To plot the regulation characteristics of the given IC LM 723
APPARATUS:
1. Voltage Regulator LM 723 IC 1 No.
2. Resistors 7.5 KΩ 2 No.
3.9 KΩ 1 No.
3. Capacitors 100 µF 1No.
4. Voltmeter 0-30V 1No.
5. Ammeter 0-100mA 1No.
6. Decade resistance box 1No.

PIN DIAGRAM & FUNCTIONAL BLOCK DIAGRAM:

LM 723

NC NC
Current limit Freq. Compensation
Current Sense V+
INV-Terminal VCC
NON INV-Terminal Vout
Voltage REF VZ
Fig. 17.1 Pin diagram of LM723
Gnd NC

VC V0 CL
+
Q1
+ V
Vz D Q2
- Vref(-7V) V+ CS
Ref
Amp
NI
Constant Err
current Amp
source INV
V-
V-
Freq. Comp.

Section-1 Section-2
Fig. 17.2. Functional Block diagram of 723 IC

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CIRCUIT DIAGRAM:

Part-1 : Input Voltage versus Output Voltage

Vcc

12 11

LM 723
6 10
3.9K 2 7.5K
3
5 V 0-30V
4
13 RL
7
7.5K
100F

Fig. 17.3 Circuit diagram for Input Voltage versus Output Voltage

Part-2 Load Resistance RL versus Output Voltage (Vo)

Line Voltage
(From DC power supply)

12 11
LM 723

6 10

3.9K 2 7.5K A
3
5
4 RL
7 13
7.5K V 0-30V
100F RL

Fig. 17.4 Circuit diagram for Load Resistance RL versus Output Voltage

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%R

RL

Fig.17.5 RL versus % Regulation curve

THEORY:
With the advent of Micro-electronics, it is possible to incorporate the complete circuit
on a monolithic silicon chip. This gives low cost, high reliability, reduction in size and
excellent performance.

Examples of Monolithic regulators are 78xx/79xx series(Three terminal regulators)

and 723 general purpose regulators.

The three terminal regulators have the limitations

(1) No short circuit protection. (2) Output voltage (positive or negative) is fixed.

These limitations have been overcome in the 723 general purpose regulators, which
can be adjusted over a wide range of both positive and negative regulated voltage.
This IC is inherently low current device, but can be boosted to provide 5amps or more
current by connecting external components.

The limitation of 723 is that it has no in built thermal protection. It also has no short
circuit current limits. 723 regulator IC is available in 14-pin, dual-in-line package.
Fig..13.1-b shows the functional block diagram of a 723 regulator IC. It has two
separate sections. The zener diode, a constant current source and reference amplifier
produce a fixed voltage of about 7 volts at the terminal V ref. The constant current
source forces the zener to operate at a fixed point so that the zener outputs a fixed
voltage.

The other section of the IC consists of an error amplifier, a series pass transistor Q1
and a current limit transistor limit transistor Q2. The error amplifier compares a
sample of the output voltage applied at the 1NV input terminal to the reference
voltage Vref applied at the NI input terminal. The error signal controls the conduction
of Q1. These two sections are not internally connected but the various points are

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brought out on the IC package. 723 Regulated IC is available in 14 Pin Dual – in –

line package or 10 pin metal can.
The important features of 723 Regulated IC are as follows:
1) Input voltage 40V max
2) Output voltage adjustable from 2V to 37V
3) 150mA output current without external pass transistor
4) Output currents in excess of 10A possible by adding external
transistors
5) It can be used as either a linear or a switching regulator.
The electrical characteristics of 723 Regulated IC can be seen from Appendix.
The 723 IC can be used as Low Voltage (2V to 7V) and High Voltage (>7V)
Regulators

CURRENT LIMIT PROTECTION:

The 723 IC is provided with a current limit facility. Current limiting refers to the
ability of a regulator to prevent the load current from increasing above a present
value. The characteristic curve of a current limited regulator is shown in the following
Fig.13.3

V0

I limit
V Load
ILoad
Fig 17.6 Characteristic curve of a current limited regulator
The output voltage remains constant for load current below I limit. As current
approaches the limit the output voltages drops. The current limit I limit is set by
connecting an external resistor Rsc between the terminals CL and CS . The CL
terminal is also connected to the output terminal Vo and CS terminal is connected to
the load resistance.
I limit = 0.5V/Rsc
CURRENT FOLD BACK:
In current limiting technique, the load current is maintained at a present value and
when overload condition occurs , the output voltage Vo drops to zero . However , if
the load is short circuited , maximum current does flow through the regulator. To
Protect the regulator one must devise a method which will limit the short circuit
current and yet allow higher currents to the load . Current fold back is the method
used for this. The following Fig.13.4. shows the current fold back characteristic curve

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V0

V Load
Isc I ILoad
knee
Fig 17.7 Current fold back characteristic curve
OBSERVATIONS:
Table:
1. Variation of Vout withVin 2. Variation of % Regulation with RL
VNL =
Line Output RL IL(mA) Output %
voltage voltage (Ω) voltage Regulation
(Vin ) (Vout ) (Vout ) V NL  V FL
V FL

1.0 2111
2.0 1111
3.0 911
4.0 711
. 511
. 411
. 311
12.0 211
13.0 111
14.0 100
15.0 90
16.0
17.0

PROCEDURE:
Part 1: Input Voltage versus Output Voltage

1. Connect the circuit as shown in the Fig.13.2-a.

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2. Connect the supply between 12 & 7 terminals

3. Connect the voltmeter to 10 & ground terminals
4. Increase the input voltage and note down the corresponding output voltage
5. Initially the output voltage is increasing with an increase in input Voltage
At some value of input Voltage , the output voltage becomes constant
Note down all these readings from the multimeter.
6. Draw the Graph between the line voltage(Vin ) Versus output voltage( Vout )
Part 2: Load Resistance RL versus Output Voltage (Vo)

1. Connect the circuit as shown in the Fig.13.2.b.

2. Keep the voltage constant at which part 1 is obtained.
3. Keep the load resistance (DRB) in the maximum position
(Keep all the Knobs of DRB in maximum position)
4. Decrease the load resistance (RLoad) and note down the output current (ILoad)and
output voltage.
5. Decrease the load resistance till the output current reaches maximum rated
current and note down the corresponding values of the output voltage.
6. Draw the Graph between the load resistance (RLoad) and % regulation

RESULT & ANALYSIS:

Hence the output voltage of 723 regulator is observed for different input voltages and
the Characteristics of the IC LM 723 are plotted.

CONCLUSIONS:
It is concluded that the % regulation is decreased with an increase in the load
resistance (RLoad ).

QUESTIONS:
1. Define Voltage regulator.
2. Mention types of regulators.
3. Explain how it regulate the o/p voltage
4. Explain the characteristics of current limited regulator.
5. What is the operation of the error amplifier in 723 IC

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Experiment No: 18
Performance of Arithmetic Logic Unit

AIM: To verify the performance of 4-Bit Arithmetic Logic Unit using IC 74181.
.

APPARATUS: 1. IC 74181
2. Digital IC Trainer Kit
3. Connecting wires

THEORY:

FUNCTIONAL DESCRIPTION

The DM74LS181 is a 4-bit high speed parallel Arithmetic Logic Unit (ALU).
Controlled by the four Function Select inputs (S0–S3) and the Mode Control input
(M), it can perform all the 16 possible logic operations or 16 different arithmetic
operations on active HIGH or active LOW operands. The Function Table lists these
operations When the Mode Control input (M) is HIGH, all internal carries are
inhibited and the device performs logic operations on the individual bits as listed.
When the Mode Control input is LOW, the carries are enabled and the device
performs arithmetic operations on the two 4-bit words.

The device incorporates full internal carry look-ahead and provides for either ripple
carry between devices using the Cn+4 output, or for carry look-ahead between
packages using the signals P (Carry Propagate) and G (Carry Generate). In the ADD
mode, P indicates that F is 15 or more, while G indicates that F is 16 or more. In the
SUBTRACT mode, P indicates that F is zero or less, while G indicates that F is less
than zero. P and G are not affected by carry in.

When speed requirements are not stringent, it can be used in a simple ripple carry
mode by connecting the Carry output (Cn+4) signal to the Carry input (Cn) of the
next unit. For high speed operation the device is used in conjunction with the 9342 or
93S42 carry look-ahead circuit. One carry look-ahead package is required for each
group of four DM74LS181 devices. Carry look-ahead can be provided at various
levels and offers high speed capability over extremely long word lengths. The A = B
output from the device goes HIGH when all four F outputs are HIGH and can be used
to indicate logic equivalence over four bits when the unit is in the subtract mode. The
A = B output is open-collector and can be wired- AND with other A = B outputs to
give a comparison for more than four bits. The A = B signal can also be used with the
Cn+4 signal to indicate A > B and A < B. The Function Table lists the arithmetic
operations that are performed without a carry in. An incoming carry adds a one to
each operation.

Thus, select code LHHL generates A minus B minus 1 (2s complement notation)
without a carry in and generates A minus B when a carry is applied. Because
subtraction is actually performed by complementary addition (1s complement), a
carry out means borrow; thus a carry is generated when there is no underflow and no

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carry is generated when there is underflow. As indicated, this device can be used with
either active LOW inputs producing active LOW outputs or with active HIGH inputs
producing active HIGH outputs. For either case the table lists the operations that are
performed to the operands labeled inside the logic symbol.

PROCEDURE:

1. The IC is placed on the trainer kit.

2. The data inputs are applied at pins 2,23,21,19 and 1,22,20,18.
3. Depending on selection lines (6,5,4,3), logical and arithmetic operations will
be performed.
4. The outputs are to be taken at the corresponding output pins.

Fig. 18.1 74LS181 Connection diagram

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LOGIC DIAGRAM

Fig. 18.2 74LS181 logic diagram

FUNCTIONAL TABLE

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RESULT & ANALYSIS: The performance of the 4-Bit Arithmetic Logic Unit have
been verified according to the truth tables by applying various sets of data.

CONCLUSION: Conclusion can be made on comparison 4-Bit Arithmetic Logic

Unit functionality in hardware results with truth table.

QUESTIONS:

1. What is ALU?
2. What are different ICs available for ALU?
3. Explain the functions of ALU?

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ADDITIONAL EXPERIMENTS
Experiment No: 19
VERIFICATION OF CLAMPERS USING 741 OP-AMP

AIM: To Study and observe the output wave forms of CLAMPER Circuits
Using 741 OP-AMP with Positive and Negative reference voltages.

APPARATUS:
1. Op-amp IC741 1No.
2. Resistors 10 K 2 No.
3. Capacitor 0.1µF 1 No
4. Function generator 1No.
5. Power supply. 1No

CIRCUIT DIAGRAM:
C1 (0.1F)
V0
+

Vi V-
R RL
D
4 10K
-
+ V
7
V+
10K
Vref

Fig.19.1Peak Clamper with +Vref

C1 (0.1F)
V0
+

V V
R + RL
D
i
7 10K
-
+ V
4 

-
10K V
-Vref

Fig.19.2 Peak Clamper with -Vref

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WAVE FORMS:

Part1) Clamper with Positive reference Voltage.

Vi

t V0
VR
t
Fig..:19.3.a Input waveform Fig. 19.3.b Output waveform

Part2) Clamper with Negative Reference Voltage.

Vi V0

t
-VR

Fig..:19.4.a Input waveform Fig.19.4.b Output waveform.

THEORY:

The clamper is also known as dc inserter or restorer. The circuit is used to add a
desired dc level to the output voltage. In other words, the output is clamped to a
desired dc level. If the clamped dc level is positive, it is called positive clamper.
Similarly if the clamped dc level is negative, the clamper is called negative clamper.

Fig.19.1 shows a clamper with a variable positive dc voltage applied at the (+) input
terminal. This circuit clamps the peaks of the input wave form and therefore is also
called as peak clamper. The output voltage in the circuit is the net result of ac & dc
input voltages applied to the (-) & (+) input terminals respectively. Let us first see the
effect of Vref applied at the (+) input terminal. For positive Vref, the voltage v’ is also
positive, so that the diode D is forward biased. The circuit operates as a voltage
follower & therefore output voltage v0= +Vref.

Now consider the ac input signal vi= Vm sin wt applied at the (-) input terminal.
During the negative half cycle of vi, diode D conducts. The capacitor C1 charges

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through diode D to the negative peak voltage Vm. However, during the positive half
cycle of vi , diode D is reverse biased. The capacitor retains its previous voltage V m.
Since this voltage Vm is in series with the ac input signal, the output voltage now will
be vi +Vm. The total output voltage is, therefore, Vref +vi +Vm . The input and output
waveforms are shown in Fig..19.3.

It is possible to obtain negative peak clamping by reversing the diode D and using a
negative reference voltage -Vref .The Circuit diagram is shown in Fig.19.2.
The resistor R is used for protecting the op-amp against excessive discharge currents
from capacitor C1 especially when the dc supply voltages are switched off. The input
and output waveforms are shown in Fig..19.4.

PROCEDURE:
1. Apply the sinusoidal input having a specific amplitude and frequency to the
input terminal of Clamper.
2. Observe the output of the Clamper from output terminals.
3. Draw the Input and output wave forms on a graph paper.

RESULT & ANALYSIS:

Hence the output waveforms of Clampers using 741 Op-Amp are observed. They are
matched with theoretical wave forms.

CONCLUSIONS:
It can be concluded that, the clampers are producing the output wave forms with
necessary clamping in positive and negative directions.

QUESTIONS:
1. Define Clamper.
2. Differentiate between positive and Negative clamping.
3. What are the applications of clampers?

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Experiment No: 20
16 X 4 RAM (Read and Write Operations)

AIM: To study the performance of 16 X4 Ram using IC 74189.

APPARATUS: 1. IC 74189
2. Digital IC Trainer Kit
3. Connecting wires

THEORY:

Random access memory (usually known by its acronym, RAM) is a type of

computer data storage. Today it takes the form of integrated circuits that allow the
stored data to be accessed in any order, i.e. at random. The word random thus refers to
the fact that any piece of data can be returned in a constant time, regardless of its
physical location and whether or not it is related to the previous piece of data.[1]

This contrasts with storage mechanisms such as tapes, magnetic discs and optical
discs, which rely on the physical movement of the recording medium or a reading
head. In these devices, the movement takes longer than the data transfer, and the
retrieval time varies depending on the physical location of the next item.

The word RAM is mostly associated with volatile types of memory (such as DRAM
memory modules), where the information is lost after the power is switched off.
However, many other types of memory are RAM as well (i.e. Random Access
Memory), including most types of ROM and a kind of flash memory called NOR-
Flash.

A memory cell array organized with N by M cells can store N words with each word
being M bits long. For example, the IC type 7489 is a 16 by 4 RAM chip. It can store
up to 16 different words, and each word is 4 bits long. Apart from memory cell array,
RAM circuits also need address decoding logic and read/write control logic. The
address decoding logic translates the data address (in binary format) into the physical
location of a particular word in the memory cell array. Therefore, the memory cells in
the specified memory word are activated and ready to either put the data on to the data
output pins (read process), or to receive data from the data input pins (write process).
Whether the process is read or write depends upon the read/write control logic. Read
and write processes are also referred to as data fetch and data load respectively.

ROM circuits are similar to RAM circuits except that data are already stored
permanently in the memory cell array. Only the read process is allowed. Therefore
ROMs do not have the read/write control logic. The PROM, programmable ROM,
holds semi-permanent data; data can be modified, but slowly. One important measure
for a memory element is its access time. In order to read data, an appropriate address
must be applied to the address inputs, and perhaps an enable signal asserted. After a
short period of time, the data are valid on the output pins. The short time period is
called the access time of the memory. Access time of a memory reflects how fast the

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memory can respond to the request for data. Fig. 1 illustrates how access time is
measured assuming all enable signals are asserted true.

Fig. 20.1 Access time of memory chip.

The IC chip you are going to use in this experiment is 7489 which is a bipolar 16 by 4
random access memory. Its pin assignment to the inputs and outputs is shown in Fig.
2. The four address inputs select one of the 16 words in the memory. The least
significant bit of the address is A, and the most significant bit is D. The read/write
control logic has two control inputs. The memory enable (ME) input must be equal to
low to enable the memory. If ME is high, the memory is disabled and all four outputs
are at high impedance level. The write enable (WE) input determines the type of

operation as indicated in the function table. The write operation is performed when
WE is low. This is a transfer of the binary data from the data input lines into the
selected word in memory.

The read operation is performed when WE is high. This transfers the complement
value stored in the selected word into the output data lines. The output inverters have
open-collectors to allow external wired-OR logic to be performed for memory
expansion.

Fig. 20.2. 74189 RAM

PROCEDURE:
1. The IC is placed on the trainer kit.
2. The data inputs are applied at pins 4, 6, 10, 12 for Write operation.
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3. The address inputs are applied to pins 1,13,14,15 from which the data is to be
read/write
4. The enable should be asserted for performing read / write operation and
enables the chip.
5. The outputs are to be taken at the corresponding output pins which are
inverted to the data stored.

PIN OUT DIAGRAM

Fig. 20.3 74LS189 Connection diagram

Fig. 20.4 74LS189 logic diagram

RESULT & ANALYSIS: The performance of the 16 X4 Ram have been verified
according to the truth tables by applying various sets of data inputs.

CONCLUSION: Conclusion made on comparison of 16 X4 Ram functionality.

QUESTIONS:

1. Explain about different types of RAMs?

2. How to specify the memory size?
3. Explain read and write operations?
4. What are the differences between RAM and ROM?

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OPEN ENDED EXPERIMENTS

1. Design a clipper for a particular voltage using an op-amp.

2. Design a divide by 20 counter using two IC7490s.

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