Computer Architecture Design and performance Barry Wilkinson Department of Computer Science University of North Carolina, Charlotte Prentice Hall New York London Toronto Sydney Tokyo Singapore“08 2 3. JUNI 1992 First published 1991 by Prentice Hall International (UK) Led (66 Wood Lane End, Hemel Hempstead Hertfordshire HP2 4G A division of Simon & Schuster Intemational Group © Preptice Hall Intemational (UK) Lid, 1991 All rights reserved. No part ofthis publication may be ‘reproduced, stored in «retrieval system, or transmitted, in any form, or by any means, electronic, mechanical, Photocopying, recording or otherwise, without prior permission, in writing, from the publisher, For permission within the United States of America ‘contact Prentice Hall Inc.. Englewoad Cliffs, NJ 07632. Typeset in 16/12pt Times with Courier Printed in Great Britain at the University Press, Cambridge Library of Congress Catalogiag-in-Publishing Data Wilkinson, Barry Computer architecture: design and performance(by Barry Wilkinson P. em, Includes bibliographical references and index. ISBN 0-13.173899-2. — ISBN 0-13-173007-7 (pbk) 1.-Computer architecture. 1, Tide QA76.9.A73WS4 1991 004.22" de20 90.2953 ce Wilkinson, Barry 1947— Computer architecture: design and [. High performance computer syst L Title (008,22 ISBN 0-13-173809-2 ISBN 0-13-173907-7 pb 45 94 93 92 91 99 OHL BLLETo my wife, Wendy and my daughter, JohannaContents Preface Part | Computer design techniques 1 Computer systems 1.1 The stored program computer 1.11 Concept 1.12 Improvements i performance 1.2 Microprocessor systems 1.2.1 Development 12.2 Microprocessor architecture 1.3 Architectural devetopments 13.1 Gener 132 Processor functions 33 Memory hierarchy 134 Processor-memory interface 1355 Multiple procesor systems 1.36 Performance and cost 2 Memory management 2.1 Memory management schemes 2.2 Paging 2.2.1 General 2.2.2 Addzess translation 2.2°3 Translation look-aside butters 2.24 Page size 2.2.5 Multilevel page mapping 23 Replacement algorithms 23.1 General wa 10 2 2 rr 16 16 16 18 19 2 m 25 28 21 2 2 36 38 x» 4 4l vilvi Contents, 24 2.32 Random ceplacement algorithm, 23,3 First-in first-out replacement algorithm 2.3.4 Clock replacement algorithm 2.3.5 Least recently used replacement algorithm 2.3.6 Working set replacement algorithm 2.3.7 Performance and cost Segmentation 24.1 General 2.4.2 Paged segmentation 2.4.3 8086/286/386 segmentation Problems Cache memory systems 3.1 Cache memory 3.1.1 Operation 3.1.2 Hit ratio 3.2 Cache memory organizations 3.2.1 Direct mapping 3.2.2 Fully associative mapping 3.2.3 Set-associative mapping 3.2.4 Sector mapping 3.3 Fetch and write mechanisms 3.3.1 Fetch policy 3.3.2 Write operations 3.3.3 Write-through mechanism 3.3.4 Write-back mechanista, 3.4 Replacement policy 3.4.1 Objectives and constrains 3.4.2 Random replacement algorith 3.4.3 Firstin first-out replacement algorithin 3.44 Least rocontly used algorithm for a cache 3.5 Cache performance 3.6 Virtual memory systems with cache memory 3.6.1 Addressing cache with real addresses 3.62 Addressing cache with virtual addresses 3.6.3 Access time 3.7 Disk caches 3.8 Caches in multiprocessor systems Problems 8 45 45 a 49 31 3 55 7 61 64 64 or 68 68 " B 1” 15 15 18 n 80 81 aI 82 a2 86 % 83 94 95 99ipelined systems 4.1 Overlap and pipelining 4.1.1 Technique 4.1.2 Pipeline data transfer 4.13 Performance and cost 4.2 Instruction overlap and pipelines 4.2.1 Instruction fetchyexecute overlap, 4.22 Branch instructions 4.2.3 Data dependencies 4.24 Internal forwarding 4.25 Multistreaming 4.3 Arithmetic processing pipelines 4.3.1 General 4.3.2 Fixed point arithmetic pipelines 4.3.3 Floating point arithmetic pipelines 4.4 Logical design of pipelines 4A.1 Reservation tables 4.42 Pipoline scheduling and control 4.5 Pipelining in vector computers Problems Reduced instruction set computers 5.1 Cmpley instruction set computers (CISCs) 5.1.1 Characteristics 5.1.2 Instruction usage and encoding 5.2 Reduced instruction set computers (RISCs) 5.2.1 Design philosophy 5.2.2 RISC characteristics 5.3 RISC examples 53.1 IBM SOL 5.3.2 Early university research prototypes RISC [/Iand MIPS 5.33 A commercial RISC = MC8BIO0 5.3.4 The Inmos transputer 5.4 Concluding comments on RISCs Problems Contents ix 102 02 102 103 108 107 107 un 121 2 123 123 124 127 130 130 133, 138 140 144 144 144 146 148 148 150 153 153 136 160 165 166 iorx Contents Part It Shared memory multiprocessor systems 169 6 Multiprocessor systems and programming 71 6.1 General m 6.2 Multiprocessor classification 3 62.1 Flynn's classification 173 6.2.2 Other classifications 175 6.3 Array computers Ms 6.3.1 General architecture 175 6.3.2 Features of some array computers 7 6.33 Bit-organized array computers 180 6.4 General purpose (MIMD) multiprocessor systems 182 54.1 Architectures 182 6.4.2 Potential for increased speed 188 6.5 Programming multiprocessor systems 193, 6.5.1 Concurrent processes 193 65.2 Explicit parallelism 198 6.5.3 Implicit parallelism 199 6.6 Mechanisms for handling concurrent processes 203 6.6.1 Critical sections 203 6.62 Locks 203 6.6.3 Semaphores 207 Problems 210 7 Single bus multiprocessor systems 213 7.1 Sharing a bus 213 7.11 General 213 TA.2 Bus request and grant signals a5 7.13 Muliple bus requests 216, 7.2 Priority schemes 218 7.2.1 Parallel priority schemes 218 72.2 Serial prosity sehemes 27 7.2.3 Additional mechanisms in serial and parallel priority schemes 234 7.24 Polling schemes 235 7.3 Performance analysis, 237 7.3.1 Bandwidth and execution time 237 7312 Access time 240 7.4 System and local buses 2a 1.5 Coprocessors 243 7.5.1 Arithmetic copeocessors 283 78.2 Inpatioutpat and other eopeocessors 07 Problems 248Contents xi 8 Interconnection networks 250 8.1 Multiple bus multiprocessor systems 250 8.2 Cross-bar switch multiprocessor systems 252 2.1 Architecture 252 8.2.2 Modes of operation and examples 253 8.3 Bandwidth analysis 256 8.3.1, Methods and assumptions 256 83.2 Bandwidth of cross-bar switch 21 8.3.3 Bandwidth of multiple bus systems 260 8.4 Dynamic interconnection networks 262 84.1 General 262 8.4.2 Single stage networks 263 8.4.3 Multistage networks 263 8.4.4 Bandwidth of mulistage networks 270 8.4.5 Hor spots ca 8.5 Overlapping connectivity networks 215 8.5.1 Overlapping eross-bar switeh networks 216 85.2 Overlapping multiple bus networks 29 8.6 Static interconnection networks 282 282 tic interconnections 282 8.6.3 Limited static interconnections 282 8.6.4 Evaluation of static notworks 287 Problems 290 Part III Multiprocessor systems without shared memory 293 9 Message-passing multiprocessor systems 295 9.1 General 295 9.1.1 Architecture 295 9.1.2 Communication paths 298, 9.2 Programming 301 9.2.1 Message-passing constructs and routines 301 92.2 Synchronization and process structure 308 9.3 Message-passing system examples 308 9.3.1 Cosmic Cube 308 9.3.2 Intl iPSC system 309 9.4 Transputer an 9.4.1 Philosophy an 9.4.2 Processor architecture 312 9.5 Oceam 314 9.1 Structure 31410 Contents 9.5.2 Data types 9.5.3 Data transfer statements 9.5.4 Sequential, parallel and alternative processes 9.5.3 Repetitive processes 9.5.6 Conditional processes 9.5.7 Replicators 9.5.8 Other features Problems Multiprocessor systems using the dataflow mechanism 10.1 General 10.2 Dataflow computational 10.3 Dataflow systems 10311 Static dataflow 103.2 Dynamic dataiow 1033 VLSI datfiow structures 103.4 Dataflow languages 10.4 Macrodataftow 104.1 General 104.2 Macroéatatlow architectures 10.5 Summary and other directions Problems iodel References and further reading Index 315 316 317 320 321 323 wa 325 329 329 330 334 3M 337 342 344 349 349 350 353, 354 357 366Preface Although computer systems employ a range of performance-improving techniques, intense effort to improve present performance and to develop completely new types of computer systems with this improved performance continues. Many design techniques involve the use of parallelism, in which more than one operation is performed simultaneously. Parallelism can be achieved by using multiple functional units at various levels within the computer system. This book is concerned with design techniques to improve the performance of computer systems, anc mostly with those techniques involving the use of parallelism, ‘The book is divided imto three parts. In Part I, the fundamental methods 10 improve the performance of computer systems are discussed: in Past Tl, muli- processor systems using shared memory are examined in detail and in Part HL compurer systems not using shared memory are examined; these are often suitable for VLSI fabrication. Dividing the book into parts consisting of closely related ‘groups of chapters helps delineate the subject matter. Chapter 1 begins with an introduction to computer systems, microprocessor systems and the scope for improved performance. ‘The chapter introduces the topics dealt with in detail in the subsequent chapters, in particular, parallelism within the processor, paralfelism in the memory system, management of the memory for improved performance and multiprocessor systems. Chapters 2 and 3 concentrate upon memory management — Chapter 2.0n main memory/secondary memory manage ‘ment and Chapter 3 on processor/high speed buffer (cache) memory management. ‘The importance of cache memory has resulted in a full chapter on the subject, rather than a small section combined with main memory/secondary memory as almost always found elsewhere, Similarly, Chapter 4 deals exclusively with pipetining as applied within a processor, this being the basic technique for parallelism within « processor. Scoge for overall improved performance exists when choosing the actual instructions to implement in the instruction set. In Chapter 5, the concept of the so. called reduced struction set computer (RISC). which has a very limited number of instructions and is used predominantly for register-to-tepister operations, is discussed. Chapter 6, the first chapter in Part M, intcoduces the design of shared memoryxiv. Preiace multiprocessor systems, including a section on programming shared memory multi- processor systems. Chapter 7 concentrates upon the design of a single bus multi- processor system and its variant (system/local bus systems); the bus arbitration logic is given substantial treatment. Chapter & considers single stage and multistage interconnection networks for linking together processors and memory in a shared memory multiprocessor system. This chapter presents bandwidth analysis of crost-bar switch, multiple bus and multistage networks, including overlapping connectivity networks. Chapter 9, the first chapter in Part 111, presents multiprocessor systems having local memory only. Message-passing concepts and architectures are described and the transputer is outlined, together with its language, Occam, Chapter 10 is devoted to the dataflow technique, used in a variety of applications. Dataflow languages are presented and a short summary is given at the end of the chapter. ‘The text can serve as a course tex! for senior level/eraduate computer science, ‘compater engincering or electrical engineering courses in computer architecture and multiprocessor system design, The text should also appeal to design engineers ‘working on 16-/32-bit microprocessor and multiprocessor applications. The material presented is a natural extension to material in introductory computer organization/ computer architecture courses, and the book can be used in a variety of ways. Material from Chapters 1 10 6 could be used for a senior computer architecture course, whereas for a course on multiprocessor systems, Chapters 6 w 10 could be studied in detail. Alternatively, for a computer architecture course with greater scope, material could be selected from all or most chapters, though generally from the first parts of sections. It is assumed that the reader has a basic knowledge of logic design, computer organization and computer architecture, Exposure to computer programming languages, both high level programming languages and low level microprocessor assembly languages, is also assumed. I would like to record my appreciation to Andrew Binnie of Prentice Hall, who helped me start the project, and to Helen Martin, also of Prentice Hall, for her support throughout the preparation of the manuscript. Special thanks are extended to my students in the graduate courses CPGR 6182, CSCI 5041 and CSCI 5080, at the University of Nonh Carolina, Charlotte, who, between 1988 and 1990, helped me “classroom-test” the material; this process substantially improved the manuscript. I should also like fo thank two anonymous reviewers who made constructive and helpfut comments, Barry Wilkinson University of North Carolina CharlottePART | | Computer design techniquesCHAPTER Computer systems In this chapter, the basic operation of the traditional stored program digital computer and microprocessor implementation are reviewed. The limitations cf the single processor computer system are outlined and methods to improve the performance are suggested. A general introduction to one of the fundamental techniques of increasing performance — the introduction of separate functional units operating concurrently within the system ~ is also given 1.1 The stored program computer 1.1.1 Concept The computer system in which operations are encoded in binary, stored in a memory and performed in a defined sequence is known as a stored program computer. Most computer systems presently available are stored program computers. The concept of computer which executes a sequence of steps to perform a particular computation can be traced back over 100 years to the mechanical decimal computing machines proposed and partially constructed by Charles Babbage. Babbage's Analytical Engine of 1834 contained program and data input (punched cards), memory (mechanical), a central processing unit (mechanical with decimal arithmetic) and output devices (printed output or punched cards) — all the key features of a modern computer system. However, a complete, large scale working machine could no: be finished with the available mechanical technology and Babbage’s work seems 1o have been largely ignored for 100 years, until electronic circuits, which were developed in the mid-1940s, made the concept viable The true binary programmable clectronic computers hegan to be ceveloped by several groups in the mid-1940s, notably von Neumann and his colleagues in the United States; stored program computers are often called von Newman computers after his work. (Some pioneering work was done by Zuse in Germany during the 1930s and 1940s, but this work was not widely known at the time. During the 34 Computer design techniques 1940s, immense development of the stored program computer took place and the basis of complex modern computing systems was created, However, there are alternative computing structures with stored instructions which are nor executed in a sequence related to the stored sequence (e.¢. dataflow computers, which are described in Chapter 10) or which may not even have instructions stored in memory at all (e.g. neural computers). ‘The basic von Neumann stored program computer has: 1. A memory used for holding both instructions and the data required by those instructions. 2. A control unit for fetching the instructions from memory. 3. An aritimetic processor for performing the specified operations. Input/output mechanisms and peripheral devices for transferring data to and from the system. ‘The control unit and the arithmetic processor of a stored program computer are normally combined into a ceniral processing unit (CPU), which results in the general arrangement shown in Figure 1.1. Binary representation is used throughout for the number representation and arithmetic, and corresponding Boolean values are used for logical operations and devices. Thus. only two voltages of states are needed to represent each digit (0 or 1). Multiple valued representation and logic have been, and are still being, investigated. ‘The instructions being executed (or about to be executed) and their associated data are held in the main memory, This 1s organized such that each binary word is stored in a location idemtfied by a number called an address. Memory addresses are allocated in strict sequence, with consecutive memory locations given consecutive Input devices) Output dvicts t Input Outeut interfaces) intertacess) Canta processing tant (ePUy Figure 1.1. Stored program digital computerComputer systems 5 addresses. Main memory must access individual storage locations in any order and. at very high speed; such memory is known as random access memory (RAM) and is, essential for the main memory of the system. ‘There is usually additional memory, known as secondary memory ot backing store, provided to extend the capacity of the memory system more economically than when main memory alone is used. Main memory usually consists of semi conductor memory and is more expensive per bit than secondary memory, which usually consists of magnetic memory. However, magnetic secondary memory is not capable of providing the required high speed of data transfer, nor can it locate individual storage locations in a random order at high speed (ic. it is not truely random access memory). Using the same memory for data and instructions is a key feature of the von Neumann stored program computer. However, having data memory and program ‘memory separated, with separate transfer paths between the memory and the processor. is possible. This scheme is occasionally called the Harvard architecture. The Harvard architecture may simplify memory read/write mechanisms (see Chapter 3), particularly as programs are normally only read during execution, while data might be read or altered. Also, data and unrelated instructions can be broughé into the processor simultaneously with separate memories. However, using one memory to hold both the program and the associated data gives more efficient use of memory, and itis usual for the bulk of the main memory in a computer system t hold both ‘The early idea that stored instructions could be altered during execution was quickly abandoned with the introduction of other methods of modifying instruction execution. The (central) processor has a number of intemal registers for holding specific operands used in the computation, other numbers, addresses and control information. ‘The exact allocation of registers is dependent upon the design of the processor. However, certain registers are always present. The program counter (PC), also called the instruction pointer (IP), is an internal register holding the address of the next instruction to be executed. The contents of the PC are usually incremented each time an instruction word has been read from memory in preparation for the next instruction ‘word, which is often in the next location. A stack pointer register holds the address of the “top” location of the stack. The stack is a set of locations, reserved in memory, ‘which holds return addresses and other parameters of subroutires. ‘A set of general purpose registers or sets of data registers and address registers are usually provided (registers holding data operands and addresses pointing to memory locations). In many instances these registers can be accessed more quickly than main memory locations and hence can achieve a higher computational speed. The binary encoded instructions are known as machine instructions, The operations. specified in the machi ons are normally reduced to simple operations, such as arithmetic operations, to provide the greatest flexibility. Atithmetic and other simple operations operate on one or two operands, and produce a numeric result. More complex operations are created from a sequence of simple instructions, by the user. From a fixed set of machine instructions available in the computer (the instruction set) the user selects instructions to perform a particular computation. instruct6 Computer design techniques The list of instructions selected is called a computer program. The selection is done by a programmer. The program is stored in the memory and, when the system is ready. each machine instruction is read from (main) memory and executed Each machine instruction needs to specify the operation to be performed, e.g. addition, subtraction, etc. The operands also need to be specified either explicitly in the instruction or implicitly by the operation. Often, cach operand is specified in the instruction by giving the address of the location holding it. This results in a general instruction format having three addresses: 1. Address of the first operand. 2. Address of the second operand. 3. Storage address for the result of the operation. AA further address could be included, that of the next instruction to be executed. This, is the four-address instruction format. The EDVAC computer, which was developed in the 1940s, used a four-address instruction format (Hayes, 1988) and this format hhas been retained in some microprogrammed control units, but the fourth address is always eliminated for machine instructions, This results in a shree-addrets instruction format by arranging that the next instruction to be executed is immediately following ‘the current instruction in memory. It is then necessary to provide an alternative ‘method of specifying non-sequential instructions, normally by including instructions in the instruction set which alter the subsequent execution sequence, sometimes under specific conditions. The third address can be eliminated to obtain the two-address instruction format by always placing the result of arithmetic or logic operations in the location where the first operand was held: this overwrites the first operand. The second address can be eliminated to obtain the one-address instruction format by having only one place for the first operand and result. This location, which would be within the processor itself rather than in the memory, is known as an accumulator, because it accumulates results. However, having only one location for one of the operands and for the subsequent result is rather limiting, and a small group of registers within the processor can be provided. as selected by a small field in the instruction; the corresponding instruction format is the one-and-a-half-address instruction format or register type. All the addresses can be eliminated to obtain the zero-address instruction format, by using two known locations for the operands. These locations are specified as the first and second locations of a group of locations known as & stack. The various formats are shown in Figure 1.2. The one-and-a-half. or two- address formats are mostly used, though there are examples of three-address processors, e.g. the AT&T WE3210 processor Various methods (addressing modes) can be used to identify the locations of the operands. Five different methods are commonly incorporated into the instruction setComputer systems 7 Operation | Tetoperand (Four adiesomet ptr | epee [top] Rei (0) Teo adres mat Ton} atoperan Speration | Tandvesut | ndoperand (6) Tworadcrss format ‘Operation | Register [2nd operand (©) Cne-and-a-natl adres format Operation Tescrearal (6) One-adress format (0 oradcress format Figure 1.2 Instruction formats (a) Four-address format _(b) Three-address format (©) Two-address format (d) One-and-a-half-address formate) One-address format (f) Zero-address format Immediate addressing when the operand is part of the instruction. Absolute addressing — when the address of an operand is held in the instruction. Register direct addressing — when the operand is held in an addressed register. Register indirect addressing ~ when the address of the operand location is held in a register. 5. Various forms of relative addressing — when the address of the operand is, computed by adding an offset held in the instruction to the contents of specific registers. ‘The operation of the processor can be divided into two distinet steps, as shown in Figure 1.3. First, an instruction is obtained from the memory and the program counter is incremented ~ this step is known as the fetch cycte. Then the operation is performed — this step is known as the execure cycle and includes fetching any operands and storing the result. Sometimes, more than one memory location is necessary to hold an instruction (depending upon the design of the instructions).® Computer design techniques ‘When this occurs the program counter is incremented by one as each location is accessed to extract a part of the instruction, The contents of the program counter can ‘be purposely altered by the execution of “jump” instructions, used to change the ‘execution sequence. This facility is essential to create significant computations and different computations which depend upon previous computations. = >| contrat (Mesnory ‘Address t<— ae 7 mz estes clon om SE ose be mo E (representative) ry > ]eontro! Memory ‘Address J — soe Il = ls location Control [> Control Processor | aa (0) Execute cycle Figure 1.3 CPU mode of operation (a) Fetch cycle (b) Execute cycle (SP, stack pointer; PC, program counter; IR, instruction register: ‘ALU, arithmetic and logic unit)Computer systems 9 ‘The operations required to execute (and fetch) an instruction can be divided into a number of sequential steps performed by the control unit of the processor. The ‘control unit can be designed using interconnected logic gates and counters t0 generate the required signals (a random logic approach). Alternatively, each step could be binary-encoded into a microinstruction. A sequence of these micro- instructions is formed for each machine instruction and is then stored in a control, memory within the internal control unit of the processor. The sequence of micro- instructions is known as a microprogram (or microcode) and one sequence must be executed for each machine instruction read from the main memory. This technique was first suggested by Wilkes in the early 1950s (Wilkes, 1951) but was not put into practice in the design of computers until the 1960s, mainly because the performance ‘was limited by the centrol memory, which needs to operate much faster than the main memory. Given a control memory with alterable contents, it is possible to alter the machine instruction set by rewriting the microprograms; this leads to the ‘concept of emulation. In emulation, a computer is microprogrammed to have exactly the same instruction set as another computer, and to behave in exactly the same ‘manner, so that machine instruction programs written for the emulated computer will run on the microprogrammed computer. ‘The general arrangement of a microprogrammed control unit is shown in Figure 1.4. An instruction is fetched into an instruction register by a standard instruction fetch microprogram. The machine instruction “points” to the first microinstruction of the microprogram for that machine instruction. This microinstruction is executed, together with subsequent microinstructions for the machine instruction. The sequence ‘ean be altered by conditions occurring within or outside the processor. In particular, ‘microprogram sequences of conditional jump instructions may be altered by conditions indicated in a processor condition code register. Also, subroutine microinstructions, ‘can be provided to reduce the size of the microprogram. Just as a stack is used to hold the return address of machine instruction subroutines, a control memory stack irsracon register Machine pee ‘Gontrot memory Ned inputs —} ascress | —+| }< | nicroinstruction logic Lbs contrat New adress om conto! [Condition code at regster Figure 1.4 Microprogrammed control unit10 Computer design techniques can be provided to hold the return address of a microinstruction subroutine return ‘The microinstructions can have one bit for each signal to be generated, binaiy- encoded fields, or a combination. A two-level approach is also possible, in which a short microinstruction points to a set of much longer nanoinstructions held in another control memory. To summarize, we can identify the main operating characteristics of the stored rogram computer as follows: 1. Only elementary operations are performed (e.g. arithmetic addition, logical operations). 2. ‘The user (programmer) selects operations to perform the required computation. Encoded operations are stored in a memory. 4, Strict sequential execution of stored instructions occurs (unless otherwise directed). 5. Data may also be stored in the same memory. ‘The reader will find a full treatment of basic computer architecture and organization, in Stallings (1987) and Mano (1982). 1.1.2 Improvements in performance Since the 1940s the development of stored program computer systems has con- centrated upon three gencral areas: 1. Improvements in technology. 2. Software development. 3. Architectural enhancements. Improvements in technology, i. in the type of components used and in fabrication techniques, have led to dramatic increases in speed. Component speeds have typically doubled every few years during the period. Such improvements are unlikely to continue for electronic components because switching times now approach the limit set by the velocity of electrical signals (about 2/3 speed of light 0.2 m ns“) and the delay through interconnecting paths will begin to dominate. In fact, this limit hhas been recognized for some time and has led seme researchers to look at alternative technologies, such as optical technology (optical computers). ‘After the overall design specification has been laid down and cost constraints are made, one of the first decisions made at the design stage of a computer is in the choice of technology. This is normally between TTL/CMOS (transistor-transistor logic/complementary metal oxide semiconductor) and ECL. (emitter-coupled logic) for high performance systems. Factors to be taken into account include the availabilityComputer systems 11 of very large scale integration (VLSI) components and the consequences of the much higher power consumption of ECL. ECL has a very low level of integration compared to CMOS but has still been chosen for the highest performance systems because, historically, it is much faster than MOS (metal oxide semiconductor). Predictions need to be made‘as to the expected developments in technology, especially those developments that can be incorporated during the design phase of the system. For exemple, it might be possible to manufacture a chip with improved performance, if certain design tolerances are met (see Maytal et al., 1989). ‘A computer system can be characterized by its instruction execution speed, the internal processor cycle time or clock period, the capacity and cycle time of memory, the number of bits in each stored word and by features provided withis instruction set among other characteristics. The performance of a high performance computer system is often characterized by the basic speed of machine operations, e.g. millions of operations per second, MOPS (or sometimes millions of instruc- tions per second, MIPS). These operations are further specified as millions of floating point operations per second, MFLOPS, or even thousands of MELOPS, called gigaflops, GFLOPS, especially for large, high performance computer systems. A computer is considered to be a supercomputer if it can perform hundreds of millions of floating point operations per second (100 MFLOPS) with a word length of approximately 64 bits and a main memory capacity of millions of words (Hwang, 1985). However, as technology improves, these figures need to be revised upwards. A Cray X-MP computer system, one of the fastest computer systems developed in the early 1980s, has a peak speed of about 2 GFLOPS. This great speed has only been achieved through the use of the fastest electronic components available, the ‘most careful physical design (with the smallest possible distances between com- Ponents), very high speed pipelined units with vector processing capability (see discussion, page 138 and Chapter 4), a very high speed memory system and, finally, multiple processors, which were introduced in the Cray X-MP and the Cray 2 after the single processor Cray 1. ‘The internal cycle time (clock period) specifies the period allotted to each basic internal operation of the processor. In some systems, notably microprocessor systems Gee page 12), the clock frequency is a fundamental figure of merit, especially for otherwise similar processors. A clock frequency of 10 MHz would correspond to a clock period of 100 ns. If one instruction is completed after every 100 ns clock period, the instruction rate would be 10 MOPS. This would be the peak rate. One oF ‘mote periods may be necessary to fetch an instruction and execute it, but very high speed systems can generate results at the end of each period by using pipelining and ‘multiple unit techniques. The Cray X-MP computer had a 9.5 ns clock period in 1980 and finally achieved its original design objective of an 8.5 ns clock period in 1986, by using faster components (August er al., 1989). Each subsequent design has called for a shorter clock period, e-g. 4 ns and 1 ns for the Cray 2 and Cray 3, respectively. Other large “mainframe” computer systems have had cycle times/elock periods in the range 10-30 ns. For example, the IBM 308X, first delivered in 1981, had a cycle time of 26 ns (later reduced to 24 ns) using TTL circuits mounted on12. Computer design techniques ceramic thermal conduction modules. The IBM 3090, a development of the 3080 ith faster components, first introduced in 1985, had a cycle time of 18.5 ns (Tucker, 1986). Software development, i.e. the development of programming techniques and the support environment, have included various high level languages such as PASCAL and FORTRAN and complex multitasking operating systems for controlling more than one user on the system, Some developments in software have led to variations in the internal design of the computer. For example, computers have been designed for the efficient handling of common features of high level languages by providing, special registers or operating system operations in hardware. Most computer systems, now have some hardware support for system software. In this text we are concerned with architectural developments, i.e. developments in the internal structure of the computer system to achieve improved performance. Such developments will be considered further in the next section. First though, let us examine the most striking technological development in recent years ~ the development of the microprocessor — as this device is central to the future develop- ‘ment of multiprocessor systems, particularly those systems with large numbers of processors. 1.2 Microprocessor systems 1.2.1. Development Since the late 1960s, logic components in computer systems have been fabricated on integrated circuits (chips) toachieve high component densities. Technological develop- ments in integrated circuits have produced more logic components in a given area, allowing more complex systems to be fabricated on the integrated circuit, first in small scale integration (SSI, 1 to 12 gates) then medium scale integration (MSI, 12 to 100 gates), large scale integration (LSI, 100 to 1000 gates), through to very large scale integration (VLSI, usually much greater than 1000 gates). This process led directly to the microprocessor, a complete processor on an integrated circuit. The ‘early microprocessors required the equivalent of large scale integration, Later integration methods are often characterized by the applied integrated circuit design rules specifying the minimum features, e.g. 1.25 jum and then 0.8 um line widths. Smaller line widths increase the maximum number of transistors fabricated on one integrated circuit and reduce the gate propagation delay time. The number of transistors that can be reasonably fabricated on one chip with acceptable yield and 1.25 ym design rules is in excess of one million, but this number is dependent upon the circuit complexity. Repetitive cells, as in memory devices, can be fabricated at higher density than irregular designs. Microprocessors are often manufactured with different guaranteed clock fre- quencies, e.g. 10 MHz, 15 MHz or 20 MHz. There is a continual improvement in theComputer systems 13 clock frequencies due to an improved level of component density and the attendant reduced gate propagation delay times. By increasing the clock frequency the processor immediately operates more quickly, and in direct proportion to the increase in clock frequency, assuming that the main memory can also operate at the higher speed. The choice of clock frequency is often closely related to the speed of available memory. Microprocessors are designated 4-bit, 8-bit, 16-bit, 32-bit or 64-bit depending uupon the basic unit of data processed internally. For example, a 32-bit micro- processor will usually be able to add, subtract, multiply or divide two 32-bit integer ‘numbers directly. A processor can usually operate upon smaller integer sizes addition to their basic integer size. A 32-bit microprocessor can perform arithmetic ‘operations upon 8-bit and 16-bit integers directly. Specific machine instructions ‘operate upon specific word sizes. An interesting computer architecture not taken up in microprocessors (or in most other computer systems), called a tagged architecture, uses the same instruction to specify an operation upon all allowable sizes of integers. The size is specified by bits (a ixg) attached to each stored number. The first microprocessor, the Intel 4004, introduced in 1971, was extremely primitive by present standards, operating upon 4-bit numbers and with limited external memory, but it was a milestone in integrated circuits. Four-bit micro- processors are now limited to small system applications involving decimal arithmeti such as pocket calculators, where 4 bits (a nibble) can conveniently represent one decimal digit. The 4004 was designed for such applications and in the ensuing period, more complex 8-bit, 16-bit and 32-bit microprocessors have been developed, in that order, mostly using MOS integrated circuit technology. Binary-coded decimal (BCD) arithmetic is incorporated into these more advanced processors as it is not subject to rounding, and is convenient for financial applications. Eight-bit microprocessors became the standard type of microprocessor in the mid. 1970s, typified by the Intel 8080, Motorola MC6800 and Zilog Z-80. At about this time, the microprocessor operating system CP/M, used in the 8080 and the Z-80, became widely accepted and marked the beginning of the modern microprocessor system as a computer system capable of being used in complex applications. Sixteen-bit microprocessors started to emerge as a natural development of the increasing capabilities of integrated circuit fabrication techniques towards the end of the 1970s, e.g. the Intel 8086 and Motorola MC68000, both introduced in 1978. Subsequent versions of these processors were enhanced to include further instrue- tions, circuits and, in particular, memory management capabilities and on-chip cache memory (see pages 18-20 and Chapters 2 and 3). In the Intel 8086 family, the 80186 included additional on-chip circuits and instructions and the 80286 included ‘memory management, In the Motorola family, the MC68010 included memory ‘management. Thirty-two bit versions also appeared in the 1980s (e.g. the Intel 80386 with paged memory management, the Motorola MC68020 with cache memory and the MC68030 with instruction/data cache memories and paged memory management). In 1989 the 64-bit Intel 80486 microprocessor was introduced. Floating point numbers can be processed in more advanced microprocessors by additional special processors intricately attached to the basic microprocessor,14 Computer design techniques theugh a floating point unit can also be integrated into the processor chip. Floating point numbers correspond to real numbers in high level languages and are numbers represented by two parts, a mantissa and an exponent, such that the number = ‘mantissa x base®*P", where the base is normally two for binary representation. For fumher details see Mano (1982). 1.2.2 Microprocessor architecture ‘The basic architecture of a microprocessor system is shown in Figure 1.5, and consists of a microprocessor, a semiconductor memory and input/output interface components all connected through a common set of lines called the bus. The memory holds the program currently being executed, thos> to be executed and the associated data. There would normally be additional secondary memory, usually disk memory and input/output interfaces are provided for external communication, ‘The bus-based architecture is employed in all microprocessor systems, but micro- processor systems were not the first or only computer systems to use buses; the PDP 8E minicomputer, introduced in 1971, used a bus called the Omnibus and the PDP 11, first introduced in 1970, used a bus called Unibus. The expansibility of a bus structure has kept the technique common to most small and medium size computer systems, The bus is the communication channel between the various parts of the system, and can be divided into three parts: 1. Data lines. 2. Address lines. 3. Control lines. cow] [ Bem, oe eo Disk Input wae] [rem] [oe] [ae ra] [rar] [ou] | sea, os Figure 1.5. Fundamental parts of a microprocessor system,Computer systems 15 ‘The data lines carry (1) the instructions from the memory to the processor during each irstruction fetch cycle, and (2) data between the processor and memory of input/output interfaces during instruction execute cycles, dependent upon the instruc tion being executed. Eight-bit microprocessors have eight data lines, 16-bit micro- processors have sixteen data lines (unless eight lines are used twice for each 16-bit data transfer, as in some 16-bit microprocessors). Similarly, 32-bit microprocessors have thirty-two data lines, unless reduced by the same technique. Notice that the microprocessor bit size ~ 8-bit, 16-bit, 32-bit or whatever ~ does not specify the number of data lines. It specifies the basic size of the data being processed internally and the size of the internal arithmetic and logic unit (ALU). “The instructions fetched from memory to the processor comprise one oF more 8-bit words (bytes), or one or more 16-bit words, depending upon the design of the 1microprocessor. The instructions of all 8-bit microprocessors have one or more bytes, ‘ypically up to five bytes, One byte is provided forthe operation including information oon the number of subsequeat bytes, and two bytes each for each operand address when required. Sixteen/32-bit microprocessors can have their instructions in mul- tiples of bytes or in multiples of 16-bit words, generally up 1o 6 bytes or three words. ‘When the data bus cannot carry the whole instruction in one bus eycle, additional cycles are performed to fetch the remaining parts ofthe instruction. Hence, the basic instruction fetch cycle can consist of several data buls transfers, and the timing of ‘microprocessors is usually given in terms of bus cycles. Similarly, the operands (if any) transferred during the basic execute cycle may require several bus cycles. In all, the operation of the microprocessor is given in read and write bus transfer cycles, whether these fetch instructions or transfer operands/resuls Daring a bus eycle, the bus transfer might be 10 the processor, when an instruction ‘or data operand is fetched fron memory or a data operand is read from an input/ ‘output interface, or from the processor, to @ location in the memory or an output imerface to transfer a result, Hence, the data lines are bidirectional, though simul taneous transfers in both directions are impossible and the direction of transfer must be controlled by signals within the control section of the bus. ‘The address lines carry addresses of memory locations and input/output locations to be accessed. A sufficient number of lines must be available to address @ large number of memory locations. Typically, 8-bit microprocessors in the 1970s provided for sixteen address lines, enabling 2!6 (65 536) locations to be specified uniquely. More recent microprocessors have more address lines, e.g. the 16-bit 8086 has twemty address lines (capable of addressing 1 048 576 bytes, i.e. 1 megabyte), the 16-bit 80286 and MC68000 have twenty-four (capable of addressing 16 megabytes) and the 32-bit MC68020, MC68030 and 80386 have thirty-two (capable of addressing 4294 megabytes, ie. 4 gigabytes). ‘The contro lines carry signals to activate the data/instruction transfers and other ‘events within the system; there are usually twelve or more control lines. The control signals, as a group, indicate the time and type of a transfer. The types of transfer include transfers to or from the processor (i.e. read or write) and involve memory and inpu¥output interfaces which may be differentiated.16 Computer design techniques 1.3 Architectural developments 1.3.1 General ‘There have been many developments in the basic architecture of the stored program computer to increase its speed of operation. Most of these developments can be reduced to applying parallelism, i.e. causing more than one operation to be performed simultaneously, but significant architectural developments have also come about 10 satisfy requirements of the software or to assist the application areas. A range of architectural developments has been incorporated into the basic stored program ‘computer without altering the overall stored program concept. In general, important architectural developments can be identified in the following areas: 1. Those concerned with the processor functions. 2. Those concerned with the memory system hierarchy. 3. ‘Those around the processor-memory interface. 4. Those involving use of multiple processor systems. Let us briefly review some of these developments, which will be presented in detail in the subsequent chapters. 1.3.2 Processor functions As we have noted, the oper operations: jon of the processor is centered on two composite 1, Fetching an instruction. 2. Executing the fetched instruction. First, an instruction is read from memory using the program counter as a pointer to the memory location, Next, the instruction is decoded, that is, the specified operations, are recognized. In the fetch/execute partition, the instruction decode occurs during the latter pert of the fetch cycle and once the operation has been recognized, the instruction can be executed. The operands need to be obtained from registers or ‘memory at the beginning of the execute cycle and the specified operation is then performed on the operands. The results are usually placed in a register or memory location at the end of the execute cycle. ‘The execution of an instruction and the fetching of the next instruction can be performed simultaneously in certain circumstances; this is known as instruction fetch execate overlap. The principal condition for success of the instruction fetch/execute overlap is that the particular instruction fetched can be identified before the previous instruction has been executed. (This is the case in sequentially executed instruc-Computer systems 17 tions. However, some instructions will not be executed sequentially, or may only be executed sequentially after certain results have been obtained.) ‘The two basic cycles, fetch and execute, can be broken down further into the following three steps which, in some cases, can be overlapped, 1. Fetch instruction. 2. Decode instruction and fetch operands. 3. Execute operation. ‘The execute operation can be broken into individual steps dependent upon the instruction being executed. Simple arithmetic operations operating upon integers ‘may only need one step while more complex operations, such as flosting point multiplication or division, may require several steps. In high speed processors the sequence of operations to fetch and decode, and the steps to execute an instruction, are performed in a pipeline. In general, a pipeline consists of a number of stages, as shown in Figure 1.6, with each stage performing ‘one sequential step of the overall task. Where necessary, the output of one stage is passed to the input of the next stage. Information required to start the sequence centers the first stage and results are produced by the final (and sometimes inter- mediate) stage. ‘The time taken to process one complete task in the pipeline will be at least as long as the time taken when one complex homogeneous functional unit, designed to achieve the same result as the multistage pipeline, is used. However, if a sequence of identical operations is required, the pipeline approach will generate results a: the rate at which the inputs enter the pipeline, though each result is delayed by the Processing time within the pipeline. For sequential identical operations, the pipeline ‘could be substantially faster than one homogeneous unit, Clearly, instruction operations are not necessarily identical, nor always sequential ‘and predictable, and pipelines need to be designed to cope with non-sequential, dissimilar operations. Also, it is not always possible to divide a complex operation into a series of sequential steps, especially into steps which all take the same length of time, Each stage need not take the same time, but if the times are different, the Pipeline must wait for the slowest stage to complete before processing the next set of inputs. However, substantial speed-up can be achieved using the pipeline tech- ‘nique and virtually all computer systems, even modern microprocessors, have a Fetch operana om Gat fetehunt | + mae -O-O-O-O-O- Figure 1.6 Processor pipeline18 Computer design techniques pipeline structure (Chapter 4 deals with pipelining and pipelined processors in