Programmable Logic Arrays

Need of Programmable Logic Array

• All bit patterns available in ROM are not used, which may be waste of available
inputs.
• PLA is similar to ROM but it does not provide full decoding of variables and does
not generate all minterms (as in ROM).
• In PLA decoder is replaced by a group of AND gates, each of which can be used to
generate a Product term of the input variable..
• Size of PLA is determined by number of I/P’s (n), number of product term (k) and
the number of O/P’s (m) (Number of sum term is equal to number of outputs).
• Number of programmed Links:
2n*k+k*m+m (In ROM it is 2n X m )
e.g) Circuit has three Input AB‘,AC,BC & two output (F1,F2)
n (Input)=3, k (Product term)=3, m (Output)=2
Total Link= 2n*k+k*m+m = 2*3*3+3*2+2=18+6+2=26 Links
 PLA Program Table
• PLA is used in situations, Where large number of don’t care
conditions exist in the circuit.
• Programming a PLA means making or breaking connections
among the gates.
• PLA implement the circuit in SOP form not in Sum of
minterms form (as in ROM)
• Consider TT of CC as example.
• Obtain the simplified function in SOP form using K-map.
• Then prepare the PLA program Table (Means program the
PLA)?
3
 PLA Program table Example
Now find the Distinct/Minimum product term in this CC and for the
given example these are :
AB‘,AC,BC
Circuit has three distinct product term AB‘,AC,BC & two output (F1,F2),
n (Input)=3, k (Product term)=3, m (Output)=2
Total Link= 2n*k+k*m+m = 2*3*3+3*2+2=18+6+2=26 Links
Second Col form the required path between input & AND gate.
(1-means variable is in its normal form, 0- means variable is in its
complement form, -(dash) means variable is absent in product term)
Third Col specify the path between AND gate and OR gate.
(Write 1- for all those product term those are present in the function,
-(dash) means no connection)
Under each output variable write ‘T’ (True) if output inverter is to be
bypassed and write ‘C’ (Complement) if the function is to be
complemented with the output inverter.
 Programmable Logic Array

1. It is Pre – fabricated block having array of NOT/AND/OR

gates.
2. It is used for designing "Personalized" circuits.
3. Programming a PLA means making or breaking connections
among the gates.
4. General purpose logic building blocks.

7
Programming by burning the fuses.

(a) Before programming. (b) After programming.

OR - PLA Notation
AND - PLA Notation
 PLA as Black Box

Logic gates
Inputs and Outputs
(logic variables) programmable (logic functions)
Switches
Fuse

Number of variables at input and output doesn’t fall into any relationship
 Block Diagram of PLA

Inputs

Dense array of Dense array of

AND gates Product OR gates
AND Plane terms OR Plane

Outputs

12
Programmable Logic Array (PLA) x1 x2 xn
We may need X1, or X1’ and X2, or X2’

Hence we need array of NOT gate. Input

Buffers and
Invertors

x1 x1 xn xn

P1

AND plane OR plane

Pk

f1 fm
 Gate Level Diagram of PLA
PLA with 3×2

PLA Specification say 3x2

Significance of 3x2 PLA:

3 : Number of Input variables

2 : Number of output variables

Example :
Full Adder , having three bits as input out of two bits i.e. “SUM” and “CARRY”
14
 Gate Level Diagram of PLA
PLA with 3×2 with 4 product terms.

Input :Three x1, x2, x3

Product terms :Four P1, P2,P3,P4
Output :Two f1, f2
 Gate Level Diagram of PLA
PLA with 3×2 with 4 product terms.

Give the terms of P1,P2,P3,P4 Find out f1 and f2.

 Question 1: Implement the following using suitable PLA.

F0 = A + B' C’, F1 = A C' + A B, F2 = B' C' + A B, F3 = B' C + A

F0 = A + B' C'
F1 = A C' + A B
F2 = B' C' + A B
F3 = B' C + A
Input Side:
1 = asserted in term
0 = negated in term
- = does not participate
PLA Table

Output Side:
Product Inputs Outputs
1 = term connected to output
term A B C F0 F1 F2 F3 0 = no connection to output
AB 1 1 - 0 1 1 0
BC - 0 1 0 0 0 1
AC 1 - 0 0 1 0 0
BC - 0 0 1 0 1 0
A 1 - - 1 0 0 1
17
 Question 1: Implement the following using suitable PLA.

F0 = A + B' C‘, F1 = A C' + A B, F2 = B' C' + A B, F3 = B' C + A

A B C

F0 = A + B' C' AB
F1 = A C' + A B
F2 = B' C' + A B
F3 = B' C + A B’C

AC’
PLA table
B’C’
Product Inputs Outputs
term A B C F0 F1 F2 F3 A
AB 1 1 - 0 1 1 0
BC - 0 1 0 0 0 1
AC 1 - 0 0 1 0 0
BC - 0 0 1 0 1 0
A 1 - - 1 0 0 1 F0 F1 F2 F3
18
 Question 2: Implement the following using suitable PLA.
f1 = x1x2 + x1x3‘ + x1'x2'x3 f2 = x1x2 + x1'x2'x3 + x1x3
x1 x2 x3

Programmable
connections

OR plane
P1

P2

P3

P4

AND plane

f1 f2
 Question 2: Implement the following using suitable PLA.
f1 = x1x2 + x1x3‘ + x1'x2'x3 f2 = x1x2 + x1'x2'x3 + x1x3
x1 x2 x3 x1 x2 x3

Programmable
connections
OR plane
OR plane
P1 P1

P2 P2

P3 P3

P4
P4

AND plane AND plane

f1 f2
f1 f2

x marks the connections left in place after programming

 Need of Read – Only Memory (ROM)
• Combinational circuit with small number of outputs can be implemented
with MUX
• Combinational circuit with many outputs can be implemented with
DECODER because it uses less IC’s.
• DECODER’s are mostly used for decoding binary information and MUX’s
are used to form a selected path between multiple sources and Single
destination.
• For large Combinational circuit with multiple inputs and multiple outputs,
Designer may use ROM and PLA.
e.g) Like 32/128 …….. links are available. How to handle them with SSI and MSI?
In this situation designer may use LSI, Where flexibility is given to the designer
regarding opening/broken and closing of links based upon requirement of circuit.
 Read – Only Memory (ROM)
• Memory device in which permanent binary information is stored.
• Process of entering information in ROM is known as Programming.
• ROM can be used for designing of CC.
Advantages:
• Faster than MSI/LSI circuits
• Cost is reduced.
• Ease of design since no simplification of logic function is required.
• Design can be modified rapidly.
Disadvantages:
• Increased power requirement
• Increase in size with increase in no of input variables making it impractical.
• Non utilization of complete circuit.
Read – Only Memory (ROM)
• ROM include both decoder and OR gate with in single
IC package.
• ROM is used to implement complex CC in one IC
package and finally eliminate all interconnecting wires.
• ROM came with special internal links that can be fused
or broken.
• Programmable values determined by user.
• Nonvolatile contents retained (No issue of power).
• Uniform (Random) Access delay is uniform for all
addresses.
Read – Only Memory (ROM)
• A combinational circuit with n inputs and m outputs:

Address n 2n x m m Data
inputs ROM outputs
A(n-1, ... , 0) D(m-1, ... , 0)

• Each bit combination of the input variable is called address.

• Each bit combination that come out from the output is called Word.
• Number of bits per word is equal to the number of output lines m.
• Address denotes one minterm of n variable.
• Number of distinct address = 2n with n variables.
• ROM is characterized by number of words 2n and number of bits per word m.
e.g.) Consider 32X8 ROM. Unit consist of 32 words of 8 bit each.
• There are 25 =32 (05) Five Input lines that form binary no from 0 to 31 for the address.
e.g.) If Input ‘00000’ then word no ‘0’ is selected and it appears on the output line.
 Read – Only Memory (ROM)
• Total no of bits contained in ROM is calculated (2n X m):
29 X 4 =512*4=2048 bits
(That means 2048 bits ROM may be organized as 512 words of 4
bit each. This means 04 O/P lines and 9 I/P lines)
In ROM AND gate connected as Decoder and number of OR gates
equal to the no of O/P in the unit.
ROM is used to implement complex CC with only one IC package.
 Procedure to Implement CC from ROM
1. Identify no of I/P’s and O/P’s. Determine the size of ROM.
2. Obtain TT (Programming (Means opening and closing of Link))
then see whether manipulation/simplification required?
(Means in some cases no need to generate specific output
because it is equal to I/P etc.)
3. 0’s in TT are those links that must be removed to provide
required combinations.
Read-Only Memory (ROM)

• Two views of ROM:

• ROM stores 2n words of m bits each, or
• ROM stores an n-input, m-output truth table

n=2 m=4
Example: A1 A0 D3 D2 D1 D0
0 0 0 1 0 1 Stores 4 4-bit words, or
0 1 1 1 1 1 stores 4 functions of 2
1 0 0 0 0 1 input variables
1 1 1 0 0 0
 Procedure to Implement CC from ROM
• Give the logic implementation of Boolean function: F1(A1,A0 )=(1,2,3) & F2
(A1,A0 =(0,2) using ROM with (AOI) and without inverter.
00
I/P n = 2 O/P m = 2= No of OR Gates
Example: A1 A0 F1 F2 A1 01
0 0 0 1 2 to 4
0 1 1 0 Decoder 10
A0
1 0 1 1
1 1 1 0 11

22 X 2 = ROM size : 4*2=8 bits

Means unit consist of 04 words
of 02 bits each
 Internal Structure of 44 Diode
ROM +5 V

R3 R2 R1 R0

/w0 0101 1 of n Word Lines

A1
/w1 1111
2 to 4
Decoder /w2
A0 0001
/w3 1000
Bit Lines
D0
Diode 1 D1
D2
No Diode 0
D3
Using ROMs for Combinational Logic
Example: A 3-input, 4-output combinational logic function:

Inputs Outputs
A2 A1 A0 D3 D2 D1 D0
8  4ROM
0 0 0 1 1 1 0
0 0 1 1 1 0 1
0 1 0 1 0 1 1 I0 A0 D0 Y0
0 1 1 0 1 1 1 I1 A1 D1 Y1
1 0 0 0 0 0 1 POL A2 D2 Y2
1 0 1 0 0 1 0 D3 Y3
1 1 0 0 1 0 0
1 1 1 1 0 0 0

Function: 2-to-4 Decoder with Polarity Control

A2 = Polarity (0 = active Low, 1= active High)
A1, A0 = I1, I0 (2-bit input )
D3...D0 = Y3...Y0 (4-bit decoded output)
Types Of ROMs
Mask ROM
Connections made by the semiconductor vendor
Expensive setup cost, Several weeks for delivery. High volume only
Bipolar or MOS technology
PROM
Programmable ROM
Vaporize (blow) fusible links with PROM programmer using high voltage/current
pulses
Bipolar technology
One-time programmable
EPROM
Erasable Programmable ROM
Charge trapped on extra “floating gate” of MOS transistors
Exposure to UV light removes charge. Limited number of erasures (10-100)
EEPROM (E2ROM)
Electrically Erasable ROM
Not RAM (relatively slow charge/discharge)
limited number of charge/discharge cycles (10,000)
Flash Memory
Electronically erasable in blocks
100,000 erase cycles
Simpler and denser than EEPROM
Memory Devices
• Read Only Memory (ROM)
• Structure of diode ROM
• Types of ROMs.
• ROM with 2-Dimensional Decoding.
• Using ROMs for Combinational Logic

• Read/Write Memory
(Random Access Memory, RAM):
• Types of RAM:
• Static RAM (SRAM)
• Dynamic RAM (DRAM)
• SRAM Timing
• DRAM Timing