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EC464 LOW POWER VLSI
Non clocked circuit design style-
Fully complementary logic - NMOS
Pseudo –NMOS logic
Differential cascade voltage switch logic(DCVS)
Pass transistor logic
Design and test of low voltage CMOS

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Design and test of low voltage CMOS

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 Fully complementary logic

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 NMOS and Pseudo- NMOS logic

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 NMOS and Pseudo- NMOS logic

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Differential cascade voltage Switch Logic

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 Pass transistor logic

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 Complementary pass transistor

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 Complementary pass transistor

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 EC464 LOW POWER VLSI

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Non clocked circuit design style-
Fully complementary logic - NMOS
Pseudo –NMOS logic
Differential cascade voltage switch
logic(DCVS)
Pass transistor logic
Design parameters for logic circuits

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 Static characteristics - Critical voltage points
 Dynamic (transient) response characteristics of the
circuit - Speed
 Silicon area occupied by the circuit
 Power dissipation.
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Static complementary CMOS Circuit

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 The most widely used logic style is static complementary
CMOS.
 The static CMOS style is really an extension of the static
CMOS inverter to multiple inputs.
 Primary advantage of the CMOS structure is robustness
(i.e, low sensitivity to noise), good performance, and low power
consumption with no static power dissipation
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Static CMOS Circuit

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At every point in time (except during the switching
transients) each gate output is connected to either
VDD or Vss via a low-resistive path.
The outputs of the gates assume at all times the value
of the Boolean function, implemented by the circuit
(ignoring, once again, the transient effects during
switching periods).
This is in contrast to the dynamic circuit class, which
relies on temporary storage of signal values on the
capacitance of high impedance circuit nodes.
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Static Complementary CMOS - concept

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VDD
In1
PMOS only
In2 PUN
InN
F(In1,In2,…InN)
In1
In2 PDN
NMOS only
InN
PUN and PDN are dual logic networks
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4/27/2019
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In constructing the PDN and PUN networks -Design
1 NMOS Transistors -in Series/Parallel Connection

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Transistors can be thought as a switch controlled by its gate
signal
NMOS switch closes when switch control input is high
A B
X Y Y = X if A and B
A
X B Y = X if A OR B
Y
NMOS Transistors pass a “strong” 0 but a “weak” 1
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2 PMOS Transistors - in Series/Parallel Connection

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PMOS switch closes when switch control input is low
A B
X Y Y = X if A AND B = A + B
A
X B Y = X if A OR B = AB
Y
PMOS Transistors pass a “strong” 1 but a “weak” 0
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3 NMOS as PDN & PMOS as PUN --Threshold Drops

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VDD VDD
PUN
S D
VDD
D 0  VDD S 0  VDD - V Tn
VGS
CL CL
PDN VDD  0 VDD  |V Tp|
VGS
D CL S CL
VDD
S D
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 4 Complementary CMOS Logic Style

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 5 Complementary CMOS

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• The complementary gate is naturally inverting,
implementing only functions such as NAND, NOR, and
XNOR
•The realization of a non-inverting Boolean function
(such as AND OR, or XOR) in a single stage is not
possible, and requires the addition of an extra inverter
stage.
•The number of transistors required to implement an
N-input logic gate is 2N.
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Example Gate: NAND

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 Example Gate: NOR
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Construct Complex Gate

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_________
 X = C • (A + B)
15
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Construct Complex Gate

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_________
 X = C • (A + B)
16
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Construct Complex Gate

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_________
X = (A+B)•(C+D)
17
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Construct Complex Gate

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_________
X = (A+B)•(C+D)
18
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Complex CMOS Gate

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B
A
C
D
OUT = D + A • (B + C)
A
D
B C
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Static Properties of Complementary CMOS Gates

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Complementary CMOS gates inherit all the properties of the
basic CMOS inverter
High noise margins:
VOH and VOL are at VDD and GND, respectively.
No static power consumption:
There never exists a direct path between VDD and
VSS (GND) in steady-state mode.
Comparable rise and fall times:
(under appropriate sizing conditions)
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Static Properties of Complementary CMOS Gates

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 Full rail-to-rail swing; high noise margins
 Logic levels not dependent upon the relative
device sizes; ratioless
 Always a path to Vdd or Gnd in steady state; low
output impedance
 Extremely high input resistance; nearly zero
steady-state input current
 No direct path steady state between power and
ground; no static power dissipation
 Propagation delay function of load capacitance
and resistance of transistors
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Static Properties of Complementary CMOS Gates

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 The analysis of the DC voltage transfer
characteristics and the noise margins is more
complicated than for the inverter
 these parameters depend upon the data input
patterns applied to gate.
 For a 2 input NAND gate – 3 cases
1 A=B= 0 to 1
2 B=1, A = 0 to 1
3 A=1, B = 0 to 1
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DC voltage transfer characteristics- input patterns

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 A=B=0, representing a strong pull-up
 Threshold voltage of transistor M2 will be higher than
transistor M1 due to the body effect
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Power consumption in CMOS

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Dynamic power
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Short circuit power

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Short circuit power

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Power Consumption in CMOS Logic Gates

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Power dissipation is a strong function
transistor sizing (physical capacitance)
input and output rise/fall times (short-circuit
power)
 device thresholds and temperature (leakage
power)
switching activity
Power supply
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 For more visit www.ktunotes.in
Power Consumption in CMOS Logic Gates
switching activity has two components:
 static component- function of the topology of
the logic network
dynamic –results from the timing behavior of the
circuit—the latter factor is also called glitching.
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 For more visit www.ktunotes.in
Design Techniques to Reduce Switching Activity
1. Logic Restructuring
2. Input ordering
3. Time-multiplexing resources
4. Glitch Reduction by balancing signal paths
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 For more visit www.ktunotes.in
Disadvantages of static complementary CMOS
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Ratioed Logic- Concept

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 Ratioed logic - attempt to reduce the number of
transistors at the cost of reduced robustness and extra
power dissipation
 In ratioed logic, the entire PUN is replaced with a single
unconditional load device that pulls up the output for a
high output
 Gate consists of an NMOS pull-down network that realizes
the logic function, and a simple load device.
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Ratioed Logic- Concept

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VDD VDD VDD
Resistive Depletion PMOS
Load RL Load VT < 0 Load
VSS
F F F
In1 In1 In1
In2 PDN In2 PDN In2 PDN
In3 In3 In3
VSS VSS VSS
(a) resistive load (b) depletion load NMOS (c) pseudo-NMOS
Goal: to reduce the number of devices over complementary CMOS
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 NMOS INVERTER: General structure

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• The next circuit seen by the
output node can be represented
as a lumped capacitance, Cout
• No current flow into or out of
the input and output terminals in
DC steady state
ID (Vin, Vout) =IL (VL)
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NMOS INVERTER: VTC

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•Inverter threshold voltage Vth
Vout = Vin
•VOH: Maximum output voltage
when the output level is logic " 1“
•VOL Minimum output voltage
when the output level is logic "0“
•VIL: Maximum input voltage
which can be interpreted as logic
"0“
•VIH: Minimum input voltage
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Depletion-Load nMOS Inverter

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Depletion-Load nMOS Inverter

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 The fabrication process is slightly more
complicated and requires additional
processing steps, especially for the channel
implant to adjust the threshold voltage of the
load device
Advantages
(i) sharp VTC transition and better noise margins
compared to resistive load
(ii) single power supply
(iii)smaller overall layout area
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For more visit www.ktunotes.in
Depletion-Load nMOS Inverter

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Pseudo-NMOS
 Pseudo-NMOS no of transistors (N+1)

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versus 2N for complementary CMOS)
 VOH is VDD since the pull-down devices
are turned off when the output is pulled
high
 VoL not 0 V since there is a fight
between the devices in the PDN and
the grounded PMOS load
 This results in reduced noise margins
and large static power dissipation.
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Pseudo-NMOS

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 The sizing of the load device relative to the pull-down
devices can be used to trade-off parameters such a noise
margin, propagation delay and power dissipation
 Voltage swing on the output and the overall
functionality of the gate depends upon the ratio
between the NMOS and PMOS sizes, the circuit is called
ratioed.
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Pseudo-NMOS

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 To make VOL as small as possible, the PMOS device should
be sized much smaller than the NMOS pull-down
devices.
 But negative impact on the propagation delay
 static power consumption in the low-output mode
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Pseudo-NMOS
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Pseudo-NMOS
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Pseudo-NMOS

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 The static power dissipation of pseudo-NMOS limits its use
 Pseudo- NMOS use in large fan-in circuits
 When area is most important, the reduced transistor count
compared to complimentary CMOS is quite attractive.
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4/27/2019
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How to Build Even Better Loads

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 To create a ratioed logic style that completely eliminates
static currents and provides rail-to-rail swing
 Gate combines two concepts: differential logic and
positive feedback
 A differential gate requires that each input is provided in
complementary format, and produces complementary
outputs in turn
 The feedback mechanism ensures that the load device is
turned off when not needed
 such a logic family, called Differential Cascode Voltage
Switch Logic (or DCVSL)
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Differential Cascode Voltage Switch Logic (or

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DCVSL) - XOR/XNOR DCVSL gate
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XOR/XNOR DCVSL gate

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 The pull-down networks PDN1 and PDN2 use NMOS
devices and are mutually exclusive (this is, when PDN1
conducts, PDN2 is off, and when PDN1 is off, PDN2
conducts),
 Required logic function and its inverse are simultaneously
implemented.
 For a given set of inputs, PDN1 conducts while PDN2 does
not, and that Out and Out’ are initially high and low,
respectively
 Turning on PDN1, causes Out to be pulled down, although
there is still a fight between M1 and PDN1.
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XOR/XNOR DCVSL gate

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 Out’ is in a high impedance state, as M2 and PDN2 are
both turned off
 PDN1 must be strong enough to bring Out below VDD-
|VTp|, the point at which M2 turns on and starts charging
Out’ to VDD—eventually turning off M1. This in turn
enables Out to discharge all the way to GND.
 Possible to share transistors among the two pull-down
networks, which reduces the implementation overhead
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AND/NAND DCVSL gate

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Differential Cascode Voltage Switch Logic (or
DCVSL) properties

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 Circuit exhibits a rail-to-rail swing, and the static power
dissipation is eliminated
 In steady state, none of the stacked pull-down networks
and load devices are simultaneously conducting
 Circuit is still ratioed since the sizing of the PMOS
devices relative to the pull-down devices is critical to
functionality, not just performance.
 Increase complexity in design & power-dissipation
problem that is due to cross-over currents
 During the transition, there is a period of time when PMOS
and PDN are turned on simultaneously, producing a short
circuit path.
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Design Consideration: Single-ended versus Differential

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 The DCVSL gate provides differential outputs.
 Both the output signal (Vout1) and its inverted value (Vout2)
are simultaneously available.
 This is a distinct advantage, as it eliminates the need for
an extra inverter to produce the complementary signal.
 Differential implementation of a complex function may
reduce the number of gates required by a factor of two
 The number of gates in the critical timing path is often
reduced as well.
 Prevents some of the time-differential problems introduced
by additional inverters.
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Design Consideration: Single-ended versus Differential

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 In logic design both a signal and its complement are
needed simultaneously
 When the complementary signal is generated using an
inverter, the inverted signal is delayed with respect to
the original
 Causes timing problems, especially in very high-speed
designs.
 With all these positive properties, why not always use
differential logic?
 Differential nature virtually doubles the number of
wires that has to be routed
 Dynamic power dissipation is high.
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Design Consideration: Single-ended versus Differential

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Pass-Transistor Logic

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 A popular and widely-used alternative to
complementary CMOS is pass-transistor logic
 Attempts to reduce the number of transistors
which required to implement logic by allowing the
primary inputs to drive gate terminals as well as
source/drain terminals in contrast to logic families
studied so far, which only allow primary inputs to drive
the gate terminals of MOSFETS.
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 Pass-Transistor Logic
B

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Switch Out A
Out
Inputs

Network B
B
• N transistors
• No static consumption
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Pass Transistor working with clock as control voltage
• Pass transistor MP is an NMOS device

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• Cx represents the equivalent capacitance
of the input gate of the second NMOS
device & the PN junction capacitance of
MP’s drain (source)
– When clock CK goes high, MP is turned
on and allows the input voltage Vin to be
placed on capacitor Cx
• Vin could be a high (“1”) or a low (“0”)
voltage
– When CK goes low, MP is turned off,
trapping the charge on Cx
– Instead of clock we can also give other
inputs
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Pass Transistor working with clock as control voltage

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• Operation for a 1 or a 0:
– If Vin is high (say VOH), then MP
will allow current to flow into Cx,
charging it up to Vdd – Vtn
(assume CK up level is Vdd)
– If Vin is low (say GND), then MP
will allow current to flow out of
Cx, discharging it to GND
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 • NMOS pass transistor :

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􀂃 Passes 0 (low ) well but degrades 1 (high)
􀂃 Maximum value of output is VDD – Vthn
• PMOS pass transistor
􀂃 Passes 1 without any degradation
􀂃 Low value is degraded to Vthp
NMOS pass transistor pass “strong 0” but “weak 1”
PMOS pass transistor pass “strong 1” but “weak 0”
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 AND gate using Pass Transistor logic

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• When the input A is high, Q1 is
turned on and input B is copied
to the output Z.
• If A is low, the pass transistor Q2
is turned on and passes 0 to Z.
• The transistor Q2 offers low
impedance path to the supply
rails even when A is low.
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Pass-Transistor Logic
 If the B input is high, the top transistor is turned on

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and copies the input A to the output F.
 When B is low, the bottom pass transistor is turned on
and passes a 0.
 The switch driven by B seems to be redundant but..
 To ensure that the gate is static, this is that a low-
impedance path exists to the supply rails
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Pass-Transistor Logic

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 Fewer transistors are required
 AND gate requires 4 transistors (with inverter)
 Complementary CMOS implementation would require 6
 The reduced number of devices has the additional
advantage of lower capacitance.
 NMOS device is effective at passing a 0 but is poor at
pulling a node to VDD.
 When the pass transistor pulls a node high, the output only
charges up to VDD -VTn.
 Devices experience body effect, as there exists a significant
source-to-body voltage when pulling high.
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Pass-Transistor Logic

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Pass-Transistor Logic

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 pass-transistor gates cannot be cascaded by
connecting the output of a pass gate to the gate
input of another pass transistor
 Output of M1 (node x) drives the gate of another MOS
device.
 Node x can charge up to VDD-VTn1.
 If node C has a rail to rail swing, node Y only charges
up to the voltage on node x - VTn2, which works out to
VDD-VTn1-VTn2.
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Pass-Transistor Logic

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Pass-Transistor Logic

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Pass-Transistor Logic
 VTC of pass transistor logic is data-dependent

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 When B = VDD, the top pass transistor is turned on, while the
bottom one is turned off the output just follows the input A until
the input is high enough to turn off the top pass transistor
 when A=VDD, and B makes a transition from 0 to 1. Since the
inverter has a threshold of VDD/2, the bottom pass transistor is
turned on till then and the output is close to zero. Once the
bottom pass transistor turns off, the output follows the input B
minus a threshold drop.
 A similar behavior is observed when both inputs A and B
transition from 0 to 1.
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Differential Pass Transistor Logic

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 For high performance design, a differential pass-
transistor logic family, called CPL or DPL
 The basic idea (similar to DCVSL) is to accept true
and complementary inputs and produce true and
complementary outputs
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Differential Pass Transistor Logic –(CPL)

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Differential Pass Transistor Logic properties
1 circuits are differential, complementary data inputs and

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outputs are always available.
 Although generating the differential signals requires extra
circuitry, the differential style has the advantage that some
complex gates such as XORs and adders can be realized
efficiently with a small number of transistors.
 Availability of both polarities of every signal eliminates the
need for extra inverters
2 CPL belongs to the class of static gates, because the output-
defining nodes are always connected to either VDD or GND
through a low resistance path
3 The design is very modular. This makes the design of a library
of gates very simple.
 More complex gates can be built by cascading the standard
pass-transistor modules.
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Differential Pass Transistor Logic

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Differential Pass Transistor Logic

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 CPL is a conceptually simple and modular logic
style
 Its applicability depends strongly upon the logic
function to be implemented
 The availability of a simple XOR as well of the ease of
implementing some specific gate structures makes
it attractive for structures such as adders and
multipliers
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Robust and Efficient Pass-Transistor Design

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 CPL suffers from static power dissipation and reduced
noise margins
Solution 1: Level Restoration
 use of a level restorer, which is a single PMOS
configured in a feedback path
•Advantage: Full Swing
•Restorer adds capacitance,
takes away pull down
current at X
• Ratio problem
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Robust and Efficient Pass-Transistor Design

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Solution 2: Multiple-Threshold Transistors.
 Using zero threshold devices for the NMOS pass-
transistors eliminates most of the threshold drop, and
passes a signal close to VDD
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Robust and Efficient Pass-Transistor Design

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Solution 3: Transmission Gate Logic
by placing a NMOS device in parallel with a PMOS
device
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Transmission Gate Logic

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Transmission Gate Logic

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Pass-Transistor Logic

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Boolean Decision Diagram and Pass Transistor Logic

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Pass Transistor Logic Synthesis System

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Pass Transistor Logic Synthesis System

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