Device Features _äìÉ`çêÉ OJbñíÉêå~ä= qj

Single Chip Bluetooth System

„ Low power 1.8V operation
Production Information Data Sheet for:
„ Small footprint in 96-ball VFBGA
and LGA packages (6x6mm 8x8mm BC212013
and 10x10mm) (UART only version)
„ Fully qualified Bluetooth component BC212015
„ 0.18µm CMOS technology (USB and UART version)

„ Full speed BluetoothTM operation

with full piconet support March 2003

_äìÉ`çêÉOJbñíÉêå~ä Product Data Sheet

„ Support for 8Mbit external flash
„ Minimum external components

General Description Applications

BlueCore2-External is a single chip radio and
baseband IC for Bluetooth 2.4GHz systems. „ PCs
It is implemented in 0.18µm CMOS technology.
„ Cellular Handsets
When used with external flash containing the CSR „ Cordless Headsets
Bluetooth software stack, it provides a fully
compliant Bluetooth system for data and voice „ Personal Digital Assistants (PDAs)
communications. „ Computer Accessories (Compact flash
Cards, PCMCIA Cards, SD Cards and USB
Dongles)
„ Mice, Keyboards and Joysticks
„ Digital Cameras and Camcorders

BlueCore2-External has been designed to reduce

Up to the number of external RF components required,
8Mbit which ensures module production costs are
FLASH minimised.
ROM
The device incorporates auto calibration and
built-in self-test routines to simplify development,
type approval and production test. All hardware
and device firmware is fully compliant with the
SPI Bluetooth specification v1.1.
RAM

UART/USB
RF IN
2.4 GHz
DSP I/O
Radio
RF OUT PIO

MCU
PCM

XTAL

BlueCore2-External Block Diagram

BC212015-ds-001f Production Information Page 1 of 36

 Table of Contents

Table of Contents
1 Key Features .................................................................................................................................................. 3
2 Device Pinout Diagram .................................................................................................................................. 4
3 Device Terminal Functions ........................................................................................................................... 5
4 Electrical Characteristics .............................................................................................................................. 9
5 Device Diagram ............................................................................................................................................ 14
6 Description of Functional Blocks ............................................................................................................... 15
6.1 RF Receiver ............................................................................................................................................ 15
6.1.1 Low Noise Amplifier .................................................................................................................. 15
6.1.2 Analogue to Digital Converter ................................................................................................... 15
6.2 RF Transmitter ........................................................................................................................................ 15

_äìÉ`çêÉOJbñíÉêå~ä Product Data Sheet

6.2.1 IQ Modulator ............................................................................................................................. 15
6.2.2 Power Amplifier ........................................................................................................................ 15
6.3 RF Synthesiser ....................................................................................................................................... 15
6.4 Baseband and Logic ............................................................................................................................... 15
6.4.1 Memory Management Unit ....................................................................................................... 15
6.4.2 Burst Mode Controller............................................................................................................... 15
6.4.3 Physical Layer Hardware Engine DSP ..................................................................................... 16
6.4.4 RAM.......................................................................................................................................... 16
6.4.5 External Memory Driver ............................................................................................................ 16
6.4.6 USB .......................................................................................................................................... 16
6.4.7 Synchronous Serial Interface.................................................................................................... 16
6.4.8 UART........................................................................................................................................ 16
6.4.9 Audio PCM Interface................................................................................................................. 16
6.5 Microcontroller ........................................................................................................................................ 17
6.5.1 Programmable I/O .................................................................................................................... 17
7 CSR Bluetooth Software Stacks ................................................................................................................. 18
7.1 BlueCore HCI Stack................................................................................................................................ 18
7.1.1 Key Features of the HCI Stack ................................................................................................. 19
7.2 BlueCore RFCOMM Stack ...................................................................................................................... 21
7.2.1 Key Features of the BlueCore2-External RFCOMM Stack ....................................................... 21
7.3 BlueCore Virtual Machine Stack ............................................................................................................. 22
7.4 Host-Side Software ................................................................................................................................. 23
7.5 Device Firmware Upgrade ...................................................................................................................... 23
7.6 Additional Software for Other Embedded Applications ........................................................................... 23
7.7 CSR Development Systems.................................................................................................................... 23
8 External Interfaces ....................................................................................................................................... 24
8.1 Transmitter/Receiver Inputs and Outputs ............................................................................................... 24
8.2 Asynchronous Serial Data Port (UART) and USB Port ........................................................................... 24
8.3 PCM CODEC Interface ........................................................................................................................... 24
8.4 Serial Peripheral Interface ...................................................................................................................... 25
8.5 Parallel PIO Port ..................................................................................................................................... 25
2
8.6 I C Interface ............................................................................................................................................ 25
9 Schematic ..................................................................................................................................................... 26
10 Package Dimensions ................................................................................................................................... 27
10.1 96-Ball VFBGA....................................................................................................................................... 27
10.2 96-Ball LGA............................................................................................................................................ 28
10.3 96-Ball LFBGA ....................................................................................................................................... 29
11 Ordering Information ................................................................................................................................... 30
12 Contact Information ..................................................................................................................................... 31
13 Document References ................................................................................................................................. 32
14 Acronyms and Definitions........................................................................................................................... 33
15 Record of Changes ...................................................................................................................................... 36

BC212015-ds-001f Production Information Page 2 of 36

 Key Features

1 Key Features

Radio Baseband and Software

„ Operation with common TX/RX terminals „ External 8Mbit flash for complete system solution
simplifies external matching circuitry and and application flexibility
eliminates external antenna switch „ 32kbyte on-chip RAM allows full speed Bluetooth
„ Extensive built-in self-test minimises production data transfer, mixed voice and data, plus full 7
test time slave piconet operation
„ No external trimming is required in production „ Dedicated logic for forward error correction,
„ Full RF reference designs are available header error control, access code correlation,
demodulation, cyclic redundancy check,
encryption bitstream generation, whitening and
Transmitter transmit pulse shaping

_äìÉ`çêÉOJbñíÉêå~ä Product Data Sheet

„ Up to +6dBm RF transmit power with level „ Transcoders for A-law, µ-law and linear voice
control from the on-chip 6-bit DAC over a from host and A-law, µ-law and CVSD voice over
dynamic range greater than 30dB air
„ Supports Class 2 and Class 3 radios without the
need for an external power amplifier or TX/RX Physical Interfaces
switch
„ Synchronous serial interface up to 4Mbaud
„ Supports Class 1 radios with an external power
amplifier provided by a power control terminal „ UART interface with programmable Baud rate up
controlled by an internal 8-bit voltage DAC and to 1.5MBaud
an external RF TX/RX switch „ Full speed USB interface supports OHCI and
UHCI host interfaces. Compliant with USB v1.1
Receiver „ Synchronous bi-directional serial programmable
„ Integrated channel filters audio interface

„ Digital demodulator for improved sensitivity and „ Optional I2CTM compatible interface
co-channel rejection
„ Digitised RSSI available in real time over the Bluetooth Stack Running on an
HCI interface Internal Microcontroller
„ Fast AGC for enhanced dynamic range CSR’s Bluetooth Protocol Stack runs on-chip in a
variety of configurations:
Synthesiser „ Standard HCI (UART or USB)
„ Fully integrated synthesiser; no external VCO „ Fully embedded to RFCOMM, thus reducing host
varactor diode or resonator CPU load
„ Compatible with crystals between 8 and 32MHz
(in multiples of 250kHz) or an external clock Package Options
„ 96-ball LFBGA 10x10x1.4mm 0.80mm pitch
Auxiliary Features „ 96-ball VFBGA 8x8x1.0mm 0.65mm pitch
„ Crystal oscillator with built-in digital trimming
„ 96-ball VFBGA 6x6x1.0mm 0.50mm pitch
„ Power management includes digital shut down
and wake up commands and an integrated low „ 96-ball VFLGA 6x6x0.65mm 0.50mm pitch
power oscillator for ultra-low Park/Sniff/Hold
mode power consumption
„ Device can be used with an external Master
oscillator and provides a ‘clock request signal’ to
control external clock source
„ Uncommitted 8-bit ADC and 8-bit DAC are
available to application programs

BC212015-ds-001f Production Information Page 3 of 36

 Device Pinout

2 Device Pinout Diagram

Orientation from top of device
1 2 3 4 5 6 7 8 9 10 11

_äìÉ`çêÉOJbñíÉêå~ä Product Data Sheet

C

Figure 2.1: BlueCore2-External Device Pinout Diagram

Notes:
Device pinout diagram is the same for:
10x10mm LFBGA (BN)
8x8x1mm VFBGA package (DN)
6x6x1mm VFBGA package (EN)
6x6x0.6mm LGA package (LN)

BC212015-ds-001f Production Information Page 4 of 36

 Device Terminal Functions

3 Device Terminal Functions

Radio Ball Pad Type Description
RF_IN E1 Analogue Single ended receiver input
Bi-directional with weak
PIO[0]/RXEN C1 Control output for external LNA (if fitted)
internal pull-up/down
Bi-directional with weak Control output for external PA Class 1
PIO[1]/TXEN C2
internal pull-up/down applications only
TX_A G1 Analogue Transmitter output/Switched Receiver input
TX_B F1 Analogue Complement of TX_A
AUX_DAC D2 Analogue Voltage DAC output

_äìÉ`çêÉOJbñíÉêå~ä Product Data Sheet

Synthesiser and
Ball Pad Type Description
Oscillator
XTAL_IN L1 Analogue For crystal or external clock input
XTAL_OUT L2 Analogue Drive for crystal
LOOP_FILTER J1 Analogue Connection to external PLL loop filter

External Memory
Ball Pad Type Description
Port
CMOS output, tristatable Read enable for external memory (active
REB D10
with internal weak pull-up low)
CMOS output, tristatable Write enable for external memory (active
WEB E10
with internal weak pull-up low)
CMOS output, tristatable
CSB C10 Chip select for external memory (active low)
with internal weak pull-up

Address Lines Ball Pad Type Description

A[0] D9 CMOS output, tristatable Address line
A[1] E9 CMOS output, tristatable Address line
A[2] E11 CMOS output, tristatable Address line
A[3] F9 CMOS output, tristatable Address line
A[4] F10 CMOS output, tristatable Address line
A[5] F11 CMOS output, tristatable Address line
A[6] G9 CMOS output, tristatable Address line
A[7] G10 CMOS output, tristatable Address line
A[8] G11 CMOS output, tristatable Address line
A[9] H9 CMOS output, tristatable Address line
A[10] H10 CMOS output, tristatable Address line
A[11] H11 CMOS output, tristatable Address line
A[12] J8 CMOS output, tristatable Address line
A[13] J9 CMOS output, tristatable Address line
A[14] J10 CMOS output, tristatable Address line
A[15] J11 CMOS output, tristatable Address line
A[16] K9 CMOS output, tristatable Address line
A[17] K10 CMOS output, tristatable Address line
A[18] K11 CMOS output, tristatable Address line

BC212015-ds-001f Production Information Page 5 of 36

 Device Terminal Functions

Data Bus Ball Pad Type Description

Bi-directional with weak
D[0] K8 Data line
internal pull-down
Bi-directional with weak
D[1] L9 Data line
internal pull-down
Bi-directional with weak
D[2] L10 Data line
internal pull-down
Bi-directional with weak
D[3] L11 Data line
internal pull-down
Bi-directional with weak
D[4] L8 Data line
internal pull-down
Bi-directional with weak
D[5] J7 Data line
internal pull-down
Bi-directional with weak
D[6] K7 Data line

_äìÉ`çêÉOJbñíÉêå~ä Product Data Sheet

internal pull-down
Bi-directional with weak
D[7] L7 Data line
internal pull-down
Bi-directional with weak
D[8] J6 Data line
internal pull-down
Bi-directional with weak
D[9] K6 Data line
internal pull-down
Bi-directional with weak
D[10] L6 Data line
internal pull-down
Bi-directional with weak
D[11] J5 Data line
internal pull-down
Bi-directional with weak
D[12] K5 Data line
internal pull-down
Bi-directional with weak
D[13] L5 Data line
internal pull-down
Bi-directional with weak
D[14] J4 Data line
internal pull-down
Bi-directional with weak
D[15] K4 Data line
internal pull-down

PCM Interface Ball Pad Type Description

CMOS output, tristatable
PCM_OUT B9 Synchronous data output
with internal weak pull-down
CMOS input, with internal
PCM_IN B10 Synchronous data input
weak pull-down
Bi-directional with weak
PCM_SYNC B11 Synchronous data SYNC
internal pull-down
Bi-directional with weak
PCM_CLK B8 Synchronous data clock
internal pull-down

USB and UART Ball Pad Type Description

UART_TX C8 CMOS output UART data output active high
CMOS input with weak
UART_RX C9 UART data input active high
internal pull-down
CMOS output, tristatable
UART_RTS B7 UART request to send active low
with internal pull-up
CMOS input with weak
UART_CTS B6 UART clear to send active low
internal pull-down
USB_D+ (1) A7 Bi-directional USB data plus
(1)
USB_D- A6 Bi-directional USB data minus

BC212015-ds-001f Production Information Page 6 of 36

 Device Terminal Functions

Test and Debug Ball Pad Type Description

CMOS input with weak Reset if high. Input debounced so must be
RESET F3
internal pull-down high for >5ms to cause a reset
CMOS input with weak Chip select for Synchronous Serial Interface
SPI_CSB A4
internal pull-up active low
CMOS input with weak
SPI_CLK B5 Serial Peripheral Interface clock
internal pull-down
CMOS input with weak
SPI_MOSI A5 Serial Peripheral Interface data input
internal pull-down
CMOS output, tristatable
SPI_MISO B4 with weak internal pull- Serial Peripheral Interface data output
down

_äìÉ`çêÉOJbñíÉêå~ä Product Data Sheet

CMOS input with strong
TEST_EN G3 For test purposes only (leave unconnected)
internal pull-down

PIO Port(3) Ball Pad Type Description

PIO[2]/ Bi-directional with

PIO or USB pull-up (via 1.5kΩ resistor to
B3 programmable weak
USB_PULL_UP (1) (2) USB_D+)
internal pull-up/down
Bi-directional with
PIO[3]/USB_WAKE_ PIO or output goes high to wake up PC when
B2 programmable weak
UP/RAM_CSB (1) (2) in USB mode or external RAM chip select
internal pull-up/down
Bi-directional with
PIO or USB on (input senses when VBUS is
PIO[4]/USB_ON (1) (2) B1 programmable weak
high, wakes BlueCore2-External)
internal pull-up/down
Bi-directional with
PIO[5]/USB_DETACH PIO line or chip detaches from USB when
(1) (2) A3 programmable weak
this input is high
internal pull-up/down
Bi-directional with
PIO line or clock request output to enable
PIO[6]/CLK_REQ C3 programmable weak
external clock for external clock line
internal pull-up/down
Bi-directional with
PIO[7] E3 programmable weak Programmable input/output line
internal pull-up/down
Bi-directional with
PIO[8] D3 programmable weak Programmable input/output line
internal pull-up/down
Bi-directional with
PIO[9] C4 programmable weak Programmable input/output line
internal pull-up/down
Bi-directional with
PIO[10] C5 programmable weak Programmable input/output line
internal pull-up/down
Bi-directional with
PIO[11] C6 programmable weak Programmable input/output line
internal pull-up/down
AIO[0] K3 Bi-directional Programmable input/output line
AIO[1] L4 Bi-directional Programmable input/output line
AIO[2] J3 Bi-directional Programmable input/output line
Notes:
(1)
USB functions are available on BC212015 only.
(2)
USB functions can be software mapped to any PIO terminal.
(3)
All PIO’s are configured as inputs with weak pull-downs at reset.

BC212015-ds-001f Production Information Page 7 of 36

 Device Terminal Functions

Power Supplies
Ball Pad Type Description
and Control
D1
VDD_RADIO VDD Positive supply connection for RF circuitry
H3
Positive supply for VCO and synthesiser
VDD_VCO H1 VDD
circuitry
VDD_ANA K1 VDD Positive supply for analogue circuitry
VDD_CORE A8 VDD Positive supply for internal digital circuitry
VDD_PIO A1 VDD Positive supply for PIO and AUX DAC
VDD_PADS A10 VDD Positive supply for all other input/output
Positive supply for external memory port and
VDD_MEM D11 VDD
AIO

_äìÉ`çêÉOJbñíÉêå~ä Product Data Sheet

E2
VSS_RADIO F2 VSS Ground connections for RF circuitry
G2
J2 Ground connections for VCO and
VSS_VCO VSS
H2 synthesiser
L3
VSS_ANA VSS Ground connections for analogue circuitry
K2
Ground connection for internal digital
VSS_CORE A9 VSS
circuitry
VSS_PIO A2 VSS Ground connection for PIO and AUX DAC
Ground connection for input/output except
VSS_PADS A11 VSS
memory port
VSS_MEM C11 VSS Ground connection for external memory port
Ground connection for internal package
VSS C7 VSS
shield

BC212015-ds-001f Production Information Page 8 of 36

 Electrical Characteristics

4 Electrical Characteristics
Absolute Maximum Ratings

Rating Min Max

Storage Temperature -40°C +150°C
Supply Voltage: VDD_RADIO, VDD_VCO, VDD_ANA,
-0.40V 1.90V
VDD_CORE
Supply Voltage: VDD_PADS, VDD_PIO, VDD_MEM -0.40V 3.60V

Recommended Operating Conditions

_äìÉ`çêÉOJbñíÉêå~ä Product Data Sheet

Operating Condition Min Max
(1)
Operating Temperature Range -40°C 105°C
Supply Voltage: VDD_RADIO, VDD_VCO, VDD_ANA,
1.70V 1.90V
VDD_CORE
Supply Voltage: VDD_PADS, VDD_PIO, VDD_MEM 1.70V 3.60V
Note:
(1)
The device functions across this range. See long form data book for guaranteed performance over
temperature.

BC212015-ds-001f Production Information Page 9 of 36

 Electrical Characteristics

Input/Output Terminal Characteristics

Digital Terminals Min Typ Max Unit
Input Voltage
VIL input logic level low (VDD=3.0V) -0.4 - +0.8 V
(VDD=1.8V) -0.4 - +0.4 V
VIH input logic level high 0.7VDD - VDD+0.4 V
Output Voltage
VOL output logic level low, (lO = 4.0mA), VDD=3.0V - - 0.2 V
VOL output logic level low, (lO = 4.0mA), VDD=1.8V - - 0.4 V

_äìÉ`çêÉOJbñíÉêå~ä Product Data Sheet

VOH output logic level high, (lO = -4.0mA), VDD=3.0V VDD-0.2 - - V
VOH output logic level high, (lO = -4.0mA), VDD=1.8V VDD-0.4 - - V
Input and Tristate Current with:
Strong pull-up -100 -20 -10 µA
Strong pull-down +10 +20 +100 µA
Weak pull-up -5 -1 0 µA
Weak pull-down 0 +1 +5 µA
I/O pad leakage current -1 0 +1 µA
CI Input Capacitance 2.5 - 10 pF

Input/Output Terminal Characteristics (Continued)

USB Terminals Min Typ Max Unit

Input threshold
VIL input logic level low - - 0.3VDD_PADS V
VIH input logic level high 0.7VDD_PADS - - V
Input leakage current
VSS_PADS< VIN< VDD_PADS(1) -1 - 1 µA
CI Input capacitance 2.5 - 10 pF
Output levels to correctly terminated USB
Cable
VOL input logic level low 0 - 0.2 V
VOH input logic level high 2.8 - VDD_PADS V

Notes:
VDD_CORE, VDD_RADIO, VDD_VCO and VDD_ANA are at 1.8V unless shown otherwise
VDD_PADS, VDD_PIO and VDD_MEM are at 3.0V unless shown otherwise
Current drawn into a pin is defined as positive; current supplied out of a pin is defined as negative.
(1)
Internal USB pull-up disabled

BC212015-ds-001f Production Information Page 10 of 36

 Electrical Characteristics

Input/Output Terminal Characteristics (Continued)

Auxiliary DAC, 8-Bit Resolution Min Typ Max Unit

Resolution - - 8 Bits
Average output step size(1) 12.5 14.5 17 mV
Output Voltage monotonic(1)
Voltage range (IO=0) VSS_PIO - VDD_PIO V
Current range -10 - +0.1 mA
Minimum output voltage (IO=100µA) 0 - 0.2 V
Maximum output voltage (IO=10mA) VDD_PIO-0.3 - VDD_PIO V
High Impedance leakage current -1 - +1 µA

_äìÉ`çêÉOJbñíÉêå~ä Product Data Sheet

Offset -220 - +120 mV
Integral non-linearity(1) -2 - +2 LSB
Starting time (50pF load) - - 10 µs
Settling time (50pF load) - - 5 µs

Input/Output Terminal Characteristics (Continued)

Crystal Oscillator Min Typ Max Unit

Crystal frequency (2) 8.0 - 32.0 MHz
(3)
Digital trim range 5 6.2 8 pF
Trim step size (3) - 0.1 - pF
Transconductance 2.0 - - mS
Negative resistance (4)
870 1500 2400 Ω

Input/Output Terminal Characteristics (Continued)

Power-on reset Min Typ Max Unit

VDD falling threshold 1.40 1.50 1.60 V
VDD rising threshold 1.50 1.60 1.70 V
Hysteresis 0.05 0.10 0.15 V

Notes:
VDD_CORE, VDD_RADIO, VDD_VCO and VDD_ANA are at 1.8V unless shown otherwise
VDD_PADS, VDD_PIO and VDD_MEM are at 3.0V unless shown otherwise
The same setting of the digital trim is applied to both XTAL_IN and XTAL_OUT.
Current drawn into a pin is defined as positive, current supplied out of a pin is defined as negative.
(1)
Specified for an output voltage between 0.2V and VDD_PIO -0.2V
(2)
Integer multiple of 250kHz.
(3)
The difference between the internal capacitance at minimum and maximum settings of the internal digital
trim.
(4)
XTAL frequency = 16MHz; XTAL C0 = 0.75pF; XTAL load capacitance = 8.5pF

BC212015-ds-001f Production Information Page 11 of 36

 Electrical Characteristics

Radio Characteristics, VDD = 1.8V Temperature = +20°C

Frequency Bluetooth
Min Typ Max Unit
(GHz) Specification
2.402 - -83 - dBm
Sensitivity at 0.1% BER 2.441 - -85 - ≤-70 dBm
2.480 - -85 - dBm
2.402 - - - dBm
Maximum received signal at 0.1%
2.441 - - - ≥-20 dBm
BER
2.480 - - - dBm

_äìÉ`çêÉOJbñíÉêå~ä Product Data Sheet

2.402 - 6.0 - dBm
RF transmit power (1) 2.441 - 6.0 - -6 to +4 (2)
dBm
2.480 - 6.0 - dBm
2.402 - 12 - kHz
Initial carrier frequency tolerance 2.441 - 10 - ±75 kHz
2.480 - 9 - kHz
2.402 - 879 - kHz
20dB bandwidth for modulated
carrier
2.441 - 816 - ≤1000 kHz
2.480 - 819 - kHz
RF power control range - 35 - ≥16 dB
RF power range control resolution - 1.8 - - dB

Notes:
(1)
BlueCore2-External firmware maintains the transmit power to be within the Bluetooth specification v1.1 limits.
(2)
Class 2 RF transmit power range, Bluetooth specification v1.1

BC212015-ds-001f Production Information Page 12 of 36

 Electrical Characteristics

Average Current Consumption (1)

VDD=1.8V Temperature = 20°C

Mode Avg Unit

SCO connection HV3 (40ms interval Sniff Mode) (Slave) 26.0 mA
SCO connection HV3 (40ms interval Sniff Mode) (Master) 26.0 mA
SCO connection HV1 (Slave) 53.0 mA
SCO connection HV1 (Master) 53.0 mA
ACL data transfer 115.2kbps UART (Master) 15.5 mA
ACL data transfer 720kbps USB (Slave) 53.0 mA

_äìÉ`çêÉOJbñíÉêå~ä Product Data Sheet

ACL data transfer 720kbps USB (Master) 53.0 mA
ACL connection, Sniff Mode 40ms interval, 38.4kbps UART 4.0 mA
ACL connection, Sniff Mode 1.28s interval, 38.4kbps UART 0.5 mA
Parked Slave, 1.28s beacon interval, 38.4kbps UART 0.6 mA
Standby Mode (Connected to host, no RF activity) 0.047 mA
(2)
Deep Sleep Mode 20.0 µA
Notes:
(1)
Current consumption is the sum of both BC212013B or BC212015B and the flash.
(2)
Current consumption is for the BC212013B and BC212015B devices only.

3.0V 1.8V
A VREG

Flash BlueCore2

Figure 4.1: Current Measurement Circuit

BC212015-ds-001f Production Information Page 13 of 36

 5

BC212015-ds-001f
XTAL_IN
VDD_ANA

VDD_RADIO
TEST_EN

XTAL_OUT
RESET

VDD_CORE
VDD_PADS

VDD_MEM
Memory
mapped USB_D+
USB
RAM control/ USB_D-
PIO[0]/RXEN Clock status
generation
SPI_CSB
Synchronous SPI_CLK
Serial
SPI_MOSI
Device Diagram

Interface
SPI_MISO
RF_IN
LNA UART_TX
Demodulator
Physical UART_RX
UART
layer UART_RTS
IQ DEMOD
hardware Burst Memory UART_CTS
engine mode management
RSSI DSP controller PCM_OUT
ADC unit Audio PCM_IN
PCM
Interface PCM_SYNC
RF Receiver
PCM_CLK
WEB
REB
RF Transmitter CSB
External
Memory 19
TX_A Driver A[18:0]
PA DAC
16
TX_B Baseband and Logic D[15:0]

IQ MOD

Production Information
VDD_PIO

Interrupt PIO[2]/USB_PULL_UP
controller PIO[3]/USB_WAKE_UP/RAM_CSB
PIO[4]/USB_ON
+45 RF Synthesiser PIO[5]/USB_DETACH
AUX -45 RISC PIO[6]/CLK_REQ
AUX_DAC Microcontroller micro-controller Programmable
PIO[7]

Figure 5.1: BlueCore2-External Device Diagram

DAC /N/N+1 RF I/O PIO[8]
synthesiser
Fref PIO[9]
Event PIO[10]
PIO[1]/TXEN
timer PIO[11]
VCO

VSS
AIO[2]
AIO[1]
AIO[0]
VSS_PIO

VSS_ANA

VSS_VCO

VDD_VCO
VSS_MEM
VSS_PADS

VSS_CORE

VSS_RADIO
LOOP_FILTER

Page 14 of 36
Device Diagram

_äìÉ`çêÉOJbñíÉêå~ä Product Data Sheet

 Functional Blocks

6 Description of Functional Blocks

6.1 RF Receiver
The receiver features a near-zero Intermediate Frequency (IF) architecture that allows the channel filters to be
integrated on to the die. Sufficient out-of-band blocking specification at the Low Noise Amplifier (LNA) input
allows the radio to be used in close proximity to Global System for Mobile Communications (GSM) and Wideband
Code Division Multiple Access (W-CDMA) cellular phone transmitters without being desensitised. The use of a
digital Frequency Shift Keying (FSK) discriminator means that no discriminator tank is needed and its excellent
performance in the presence of noise allows BlueCore2-External to exceed the Bluetooth requirements for
co-channel and adjacent channel rejection.

6.1.1 Low Noise Amplifier

_äìÉ`çêÉOJbñíÉêå~ä Product Data Sheet

The LNA can be configured to operate in single-ended or differential mode. Single-ended mode is used for
Class 1 Bluetooth operation; differential mode is used for Class 2 operation.

6.1.2 Analogue to Digital Converter

The Analogue to Digital Converter (ADC) is used to implement fast Automatic Gain Control (AGC). The ADC
samples the Received Signal Strength Indicator (RSSI) voltage on a slot-by-slot basis. The front-end LNA gain is
changed according to the measured RSSI value, keeping the first mixer input signal within a limited range. This
improves the dynamic range of the receiver, improving performance in interference limited environments.

6.2 RF Transmitter
6.2.1 IQ Modulator
The transmitter features a direct IQ modulator to minimise the frequency drift during a transmit timeslot which
results in a controlled modulation index. A digital baseband transmit filter provides the required spectral shaping.

6.2.2 Power Amplifier

The internal Power Amplifier (PA) has a maximum output power of +6dBm allowing BlueCore2-External to be
used in Class 2 and Class 3 radios without an external RF PA. Support for transmit power control allows a simple
implementation for Class 1 with an external RF PA.

6.3 RF Synthesiser
The radio synthesiser is fully integrated onto the die with no requirement for an external Voltage Controlled
Oscillator (VCO) screening can, varactor tuning diodes or LC resonators.

6.4 Baseband and Logic

6.4.1 Memory Management Unit
The Memory Management Unit (MMU) provides a number of dynamically allocated ring buffers that hold the data
which is in transit between the host and the air or vice versa. The dynamic allocation of memory ensures efficient
use of the available Random Access Memory (RAM) and is performed by a hardware MMU to minimise the
overheads on the processor during data/voice transfers.

6.4.2 Burst Mode Controller

During radio transmission the Burst Mode Controller (BMC) constructs a packet from header information
previously loaded into memory-mapped registers by the software and payload data/voice taken from the
appropriate ring buffer in the RAM. During radio reception, the BMC stores the packet header in memory-mapped
registers and the payload data in the appropriate ring buffer in RAM. This architecture minimises the intervention
required by the processor during transmission and reception.

BC212015-ds-001f Production Information Page 15 of 36

 Functional Blocks

6.4.3 Physical Layer Hardware Engine DSP

Dedicated logic is used to perform the following:

ƒ Forward error correction

ƒ Header error control
ƒ Cyclic redundancy check
ƒ Encryption
ƒ Data whitening
ƒ Access code correlation
ƒ Audio transcoding

_äìÉ`çêÉOJbñíÉêå~ä Product Data Sheet

The following voice data translations and operations are performed by firmware:

ƒ A-law/µ-law/linear voice data (from host)

ƒ A-law/µ-law/Continuously Variable Slope Delta (CVSD) (over the air)
ƒ Voice interpolation for lost packets
ƒ Rate mismatches

6.4.4 RAM
32Kbytes of on-chip RAM is provided and is shared between the ring buffers used to hold voice/data for each
active connection and the general purpose memory required by the Bluetooth stack.

6.4.5 External Memory Driver

The External Memory Driver interface can be used to connect to the external Flash memory and also to the
optional external RAM for memory intensive applications.

6.4.6 USB
This is a full speed Universal Serial Bus interface for communicating with other compatible digital devices.
BlueCore2-External acts as a USB peripheral, responding to requests from a Master host controller such as a
PC.

6.4.7 Synchronous Serial Interface

This is a synchronous serial port interface for interfacing with other digital devices. The SPI port can be used for
software debugging and for programming the external Flash memory.

6.4.8 UART
This is a standard Universal Asynchronous Receiver Transmitter (UART) interface for communicating with other
serial devices.

6.4.9 Audio PCM Interface

The Audio Pulse Code Modulation (PCM) Interface supports continuous transmission and reception of PCM
encoded audio data over Bluetooth.

BC212015-ds-001f Production Information Page 16 of 36

 Functional Blocks

6.5 Microcontroller
The microcontroller, interrupt controller and event timer run the Bluetooth software stack and control the radio
and host interfaces. A 16-bit Reduced Instruction Set Computer (RISC) microcontroller is used for low power
consumption and efficient use of memory.

6.5.1 Programmable I/O

BlueCore2-External has a total of 15 (12 digital and 3 analogue) programmable I/O terminals. These are
controlled by firmware running on the device.

_äìÉ`çêÉOJbñíÉêå~ä Product Data Sheet

BC212015-ds-001f Production Information Page 17 of 36

 CSR Bluetooth Software Stacks

7 CSR Bluetooth Software Stacks

BlueCore2-External is supplied with Bluetooth stack firmware which runs on the internal RISC microcontroller.
This is compliant with the Bluetooth specification v1.1.

The BlueCore2-External software architecture allows Bluetooth processing overheads to be shared in different
ways between the internal RISC microcontroller and the host processor. The upper layers of the Bluetooth stack
(above HCI) can be run either on-chip or on the host processor.

Running the upper stack on BlueCore2-External reduces (or eliminates, in the case of a virtual machine (VM)
application) the need for host-side software and processing time. Running the upper layers on the host processor
allows greater flexibility.

_äìÉ`çêÉOJbñíÉêå~ä Product Data Sheet

7.1 BlueCore HCI Stack

HCI
External Flash

LM

LC

32KB RAM Baseband Micro

UART

Host I/O
Host
USB
Radio

PCM I/O

Figure 7.1: BlueCore HCI Stack

In this implementation the internal processor runs the Bluetooth stack up to the Host Controller Interface (HCI).
All upper layers must be provided by the Host processor.

BC212015-ds-001f Production Information Page 18 of 36

 CSR Bluetooth Software Stacks

7.1.1 Key Features of the HCI Stack

Standard Bluetooth Functionality

The firmware has been written against the Bluetooth Core Specification v1.1.

ƒ Bluetooth components: Baseband (including LC), LM and HCI

ƒ Standard USB v1.1 and UART (H4) HCI Transport Layers
ƒ All standard radio packet types
ƒ Full Bluetooth data rate, up to 723.2kb/s asymmetric(1)
ƒ Operation with up to 7 active slaves (1)
ƒ Maximum number of simultaneous active ACL connections: 7(2)

_äìÉ`çêÉOJbñíÉêå~ä Product Data Sheet

ƒ Maximum number of simultaneous active SCO connections: 3(2)
ƒ Operation with up to 3 SCO links, routed to one or more slaves
ƒ Role switch: can reverse Master/Slave relationship
ƒ All standard SCO voice codings, plus “transparent SCO”
ƒ Standard operating modes: page, inquiry, page-scan and inquiry-scan
ƒ All standard pairing, authentication, link key and encryption operations
ƒ Standard Bluetooth power saving mechanisms: Hold, Sniff and Park modes, including “Forced Hold”
ƒ Dynamic control of peers’ transmit power via LMP
ƒ Master/Slave switch
ƒ Broadcast
ƒ Channel quality driven data rate
ƒ All standard Bluetooth Test Modes
ƒ Standard firmware upgrade via USB (DFU)

The firmware’s supported Bluetooth features are detailed in the standard PICS documents, available from
www.csr.com.

Note:
(1)
Maximum allowed by Bluetooth specification v1.1.
(2)
BlueCore2-External supports all combinations of active ACL and SCO channels for both Master and Slave
operation, as specified by the Bluetooth specification v1.1.

BC212015-ds-001f Production Information Page 19 of 36

 CSR Bluetooth Software Stacks

Extra Functionality

The firmware extends the standard Bluetooth functionality with the following features:

ƒ Supports BlueCore Serial Protocol (BCSP) – a proprietary, reliable alternative to the standard Bluetooth
H4 UART Host Transport.
ƒ Provides a set of approximately 50 manufacturer-specific HCI extension commands. This command set
(called BCCMD – “BlueCore Command”), provides:
ƒ Access to the chip’s general-purpose PIO port
ƒ Access to the chip’s Bluetooth clock – this can help transfer connections to other Bluetooth devices
ƒ The negotiated effective encryption key length on established Bluetooth links
ƒ Access to the firmware’s random number generator

_äìÉ`çêÉOJbñíÉêå~ä Product Data Sheet

ƒ Controls to set the default and maximum transmit powers – these can help minimise interference
between overlapping, fixed-location piconets
ƒ Dynamic UART configuration
ƒ Radio transmitter enable/disable – a simple command connects to a dedicated hardware switch that
determines whether the radio can transmit
ƒ The firmware can read the voltage on a pair of the chip’s external pins. This is normally used to build a
battery monitor, using either VM or host code.
ƒ A block of BCCMD commands provides access to the chip’s “persistent store” configuration database
(PS). The database sets the device’s Bluetooth address, Class of Device, radio (transmit class)
configuration, SCO routing, LM, USB and DFU constants, etc.
ƒ A UART “break” condition can be used in three ways:
ƒ Presenting a UART break condition to the chip can force the chip to perform a hardware reboot
ƒ Presenting a break condition at boot time can hold the chip in a low power state, preventing normal
initialisation while the condition exists
ƒ With BCSP, the firmware can be configured to send a break to the host before sending data –
normally used to wake the host from a deep sleep state
ƒ The DFU standard has been extended with public/private key authentication, allowing manufacturers to
control the firmware that can be loaded onto their Bluetooth modules.
ƒ A modified version of the DFU protocol allows firmware upgrade via the chip’s UART.
ƒ A block of “radio test” or BIST commands allows direct control of the chip’s radio. This aids the
development of modules’ radio designs, and can be used to support Bluetooth qualification.
ƒ Virtual Machine (VM). The firmware provides the VM environment in which to run application-specific
code. Although the VM is mainly used with BlueLab and “RFCOMM builds” (alternative firmware builds
providing L2CAP, SDP and RFCOMM), the VM can be used with this build to perform simple tasks such
as flashing LED’s via the chip’s PIO port.
ƒ Hardware low power modes: shallow sleep and deep sleep. The chip drops into modes that significantly
reduce power consumption when the software goes idle.
ƒ SCO channels are normally routed over HCI (over BCSP). However, a single SCO channel can be
routed over the chip’s single PCM port (at the same time as routing up to two other SCO channels over
HCI). [Future versions of the BC02x firmware will be able to exploit the hardware's ability to route up to
three SCO channels through the single PCM port.]

BC212015-ds-001f Production Information Page 20 of 36

 CSR Bluetooth Software Stacks

7.2 BlueCore RFCOMM Stack

RFCOMM SDP

L2CAP

External Flash
LM

LC

32KB RAM Baseband Micro

UART

_äìÉ`çêÉOJbñíÉêå~ä Product Data Sheet

Host Host I/O
USB
Radio

PCM I/O

Figure 7.2: BlueCore RFCOMM Stack

In this version of the firmware the upper layers of the Bluetooth stack up to RFCOMM are run on-chip. This
reduces host-side software and hardware requirements at the expense of some of the power and flexibility of the
HCI only stack.

7.2.1 Key Features of the BlueCore2-External RFCOMM Stack

Interfaces to Host

ƒ RFCOMM, an RS-232 serial cable emulation protocol

ƒ SDP, a service database look-up protocol

Connectivity

ƒ Maximum number of active slaves: 3

ƒ Maximum number of simultaneous active ACL connections: 3
ƒ Maximum number of simultaneous active SCO connections: 3
ƒ Data Rate: up to 350 Kb/s

Security

ƒ Full support for all Bluetooth security features up to and including strong (128-bit) encryption.

Power Saving

ƒ Full support for all Bluetooth power saving modes (Park, Sniff and Hold).

Data Integrity

ƒ CQDDR increases the effective data rate in noisy environments.

ƒ RSSI used to minimise interference to other radio devices using the ISM band.

BC212015-ds-001f Production Information Page 21 of 36

 CSR Bluetooth Software Stacks

7.3 BlueCore Virtual Machine Stack

VM Application Software

RFCOMM SDP

External Flash
L2CAP

LM

LC

32KB RAM Baseband Micro

_äìÉ`çêÉOJbñíÉêå~ä Product Data Sheet

UART

Host Host I/O

Radio

PCM I/O

Figure 7.3: Virtual Machine

This version of the stack firmware requires no host processor. All software layers, including application software,
run on the internal RISC processor in a protected user software execution environment known as a Virtual
Machine (VM).

The user may write custom application code to run on the BlueCore VM using BlueLabTM software development
kit (SDK) supplied with the BlueLab and Casira development kits, available separately from CSR. This code will
then execute alongside the main BlueCore firmware. The user is able to make calls to the BlueCore firmware for
various operations.

The execution environment is structured so the user application does not adversely affect the main software
routines, thus ensuring that the Bluetooth stack software component does not need re-qualification when the
application is changed.

Using the VM and the BlueLab SDK the user is able to develop applications such as a cordless headset or other
profiles without the requirement of a host controller. BlueLab is supplied with example code including a full
implementation of the headset profile.

Note:
Sample applications to control PIO lines can also be written with BlueLab SDK and the VM for the HCI stack.

BC212015-ds-001f Production Information Page 22 of 36

 CSR Bluetooth Software Stacks

7.4 Host-Side Software

BlueCore2-External can be ordered with companion host-side software:

BlueCore2-PC includes software for a full Windows 98/ME, Windows 2000 or Windows XP Bluetooth host-side
stack together with IC hardware described in this document.

BlueCore2-Mobile includes software for a full host-side stack designed for modern ARM based mobile handsets
together with IC hardware described in this document.

7.5 Device Firmware Upgrade

BlueCore2-External is supplied with boot loader software which implements a Device Firmware Upgrade (DFU)
capability. This allows new firmware to be uploaded to the external Flash memory through BlueCore2-External's
UART or USB ports.

_äìÉ`çêÉOJbñíÉêå~ä Product Data Sheet

7.6 Additional Software for Other Embedded Applications
When the upper layers of the Bluetooth protocol stack are run as firmware on BlueCore2-External, a UART
software driver is supplied that presents the L2CAP, RFCOMM and Service Discovery (SDP) APIs to higher
Bluetooth stack layers running on the host. The code is provided as ‘C’ source or object code.

7.7 CSR Development Systems

CSR’s BlueLab, Casira and MicroSira development kits are available to allow the evaluation of the
BlueCore2-External hardware and software, and as toolkits for developing on-chip and host software.

BC212015-ds-001f Production Information Page 23 of 36

 External Interfaces

8 External Interfaces
8.1 Transmitter/Receiver Inputs and Outputs
Terminals TX_A and TX_B form a balanced current output. They require a DC path to VDD and should be
connected through a balun to the antenna. The output impedance is capacitive and remains constant,
irrespective of whether the transmitter is enabled or disabled. For Class 2 operation these terminals also act as
differential receive input terminals with an internal TX/RX switch.

For Class 1 operation the RF_IN ball is provided which is single-ended. A swing of up to 0.5V root mean squared
(rms) can be tolerated at this terminal. An external antenna switch can be connected to RF_IN.

8.2 Asynchronous Serial Data Port (UART) and USB Port

_äìÉ`çêÉOJbñíÉêå~ä Product Data Sheet

UART_TX, UART_RX, UART_RTS and UART_CTS form a conventional asynchronous serial data port. The
interface is designed to operate correctly when connected to other UART devices such as the 16550A. The
signalling levels are 0V and VDD_PADS and are inverted with respect to the signaling on an RS232 cable. The
interface is programmable over a variety of bit rates; no, even or odd parity; one or two stop bits and hardware
flow control on or off. The default condition on power-up is pre-assigned in the external Flash.

The maximum UART data rate is 1.5 MBaud. Two-way hardware flow control is implemented by UART_RTS and
UART_CTS. UART_RTS is an output and is active low. UART_CTS is an input and is active low. These signals
operate according to normal industry convention.

The port carries a number of logical channels: HCI data (both SCO and ACL), HCI commands and events,
L2CAP API, RFCOMM API, SDP and device management. For the UART, these are combined into a robust
tunnelling protocol, BlueCore Serial Protocol (BCSP), where each channel has its own software flow control and
cannot block other data channels. In addition, the Bluetooth specification v1.1, HCI UART Transport Layer (part
H4) format is supported.

Full speed USB (12Mbit/s) is supported in accordance with the Bluetooth specification v1.1, HCI USB Transport
Layer (H2). USB_D+ and USB_D- are available on dedicated terminals. Both Open Host Controller Interface
(OHCI) and Universal Host Controller Interfaces (UHCI) are supported.

The firmware in Flash can be downloaded through the USB or UART ports by DFU if the CSR supplied boot
loader is first programmed. Firmware shipped with BlueCore2-External includes security features to prevent
misuse of this upgrade facility.

8.3 PCM CODEC Interface

PCM_OUT, PCM_IN, PCM_CLK and PCM_SYNC carry up to three bi-directional channels of voice data, each at
8ksamples/s. The format of the PCM samples can be 8-bit A-law, 8-bit µ-law, 13-bit linear or 16-bit linear. The
PCM_CLK and PCM_SYNC terminals can be configured as inputs or outputs, depending on whether
BlueCore2-External is the Master or Slave of the PCM interface.

BlueCore2-External interfaces directly to PCM audio devices includes the following:

ƒ Qualcomm MSM 3000 series and MSM 5000 series CDMA baseband devices
ƒ OKI MSM7705 four channel A-law and µ-law CODEC
ƒ Motorola MC145481 8-bit A-law and µ-law CODEC
ƒ Motorola MC145483 13-bit linear CODEC
ƒ BlueCore2-External is also compatible with the Motorola SSITM interface

BC212015-ds-001f Production Information Page 24 of 36

 External Interfaces

8.4 Serial Peripheral Interface

BlueCore2-External is a slave device that uses terminals SPI_MOSI, SPI_MISO, SPI_CLK and SPI_CSB. This
interface is used for program emulation/debug and IC test. It is also the means by which the external Flash may
be programmed ‘in situ’ before any 'boot' program is loaded.

Note:
The designer should be aware that no security protection is built into the hardware or firmware associated with
this port, so the terminals should not be permanently connected in a PC application.

8.5 Parallel PIO Port

Fifteen lines of programmable bi-directional input/outputs (I/O) are provided. PIO[11:0] are powered from
VDD_PIO and AIO[2:0] are powered from VDD_MEM. PIO[0] and PIO[1] are normally dedicated to RXEN and

_äìÉ`çêÉOJbñíÉêå~ä Product Data Sheet

TXEN respectively, but they are available for general use. Any of the PIO lines can be configured as interrupt
request lines or as wake-up lines from sleep modes. PIO[6] can be configured as a request line for an external
clock source. This is useful when the clock to BlueCore2-External is provided from a system application specific
integrated circuit (ASIC). PIO[2] can be configured as a chip select for additional external RAM.

BlueCore2-External has three general purpose analogue interface pins, AIO[0], AIO[1] and AIO[2]. These are
used to access internal circuitry and control signals. One pin is allocated to decoupling for the on-chip bandgap
reference voltage, the other two may be configured to provide additional functionality.

Auxiliary functions available via these pins include an 8-bit ADC and an 8-bit DAC. Typically the ADC is used for
battery voltage measurement. Signals selectable at these pins include the bandgap reference voltage and a
variety of clock signals; 48, 24, 16, 8 MHz and the Xtal clock frequency. When used with analogue signals the
voltage range is constrained by the analogue supply voltage (1.8V).

These pins may also be configured to drive out digital level signals (clocks) generated from within the analogue
part of the device, the output voltage levels are determined by VDD_MEM which may be either 1.8V or 3.0V,
dependant upon the external flash.

8.6 I2C Interface

PIO[3] and PIO[2] can be used to form a Master I2C interface. The interface is formed using software to drive
these lines. Therefore it is suited only to relatively slow functions such as driving a dot matrix liquid crystal display
(LCD), keyboard scanner or EEPROM.

BC212015-ds-001f Production Information Page 25 of 36

 9

Note:
XT1

BC212015-ds-001f
1V8 1V8 16MHz TSX-10

R1 R2
1V8 1V8 0R 3V3 2R2 3V3
C11 C12
3p3 10p

C4 C5 C10 C6 C7 C8
15p 10n 47p 10n 10n 10n
Schematic

H3
D1
K1
H1
A1
A10
A8
D11
L1
K2
L2
C6
PIO[11]
C5
PIO[10]
E1 C4

VDD_PIO
XTAL_IN
RF_IN PIO[9]

VSS_ANA

VDD_ANA
VDD_VCO
D3

VDD_MEM

VDD_PADS
XTAL_OUT

VDD_CORE
PIO[8]

VDD_RADIO
VDD_RADIO
E3
PIO[7]
C3
PIO[6]
D2 A3 USER ASSIGNABLE
AUX_DAC PIO[5]
B1 GENERAL PURPOSE I/O
PIO[4]
B2
PIO[3]
B3
PIO[2]
C2
1V8 PIO[1]
C1
C1 PIO[0]
L1
C9
UART_RX
3n9 C8
15p UART_TX UART CONNECTION
B6
UART_CTS (BCSP, H4 or USER DATA)
B7
G1 UART_RTS
TX_A

2
3
L2 B5
BlueCore2 External SPI_CLK
3n9 B4
SPI_MISO BRING OUT TO TEST PADS
C2 A5
SPI_MOSI FOR PROGRAMMING
1p8 A4
F1 SPI_CSB
RF IN/OUT 4 1 1 5
T1 T2 A6
Z=50 USB_D-
A7 12 MBIT/S USB TO PC
C3 USB_D+
1p8 B11
2 3 PCM_SYNC
GND GND B8

6
4
F1 PCM_CLK
TX_B B10 TO EXTERNAL CODEC
MDR741F PCM_IN
L3 B9 3V3
T1 PCM_OUT
3n9
HHM-1517
G3
TEST_EN C17
K3
AIO[0] 1u
L4
AIO[1] R4
F3
RST
J3 22k
AIO[2]

LOOP_FILTER
VSS_VCO
VSS_VCO
VSS
VSS_ANA
VSS_RADIO
VSS_RADIO
VSS_RADIO
VSS_CORE
VSS_PADS
VSS_PIO
VSS_MEM
A[18]
A[17]
A[16]
A[15]
A[14]
A[13]
A[12]
A[11]
A[10]
A[9]
A[8]
A[7]
A[6]
A[5]
A[4]
A[3]
A[2]
A[1]
A[0]
D[15]
D[14]
D[13]
D[12]
D[11]
D[10]
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
CSB
REB
WEB

R5
C9

J1
J2
J9
J8
J4
J5
J6
J7

U1 470k

F2
F9

C7
L3
E2
E9
L5
L6
L7
L8
L9

H2
G2
A9
A2
K9
H9
G9
D9
K4
K5
K6
K7
K8

J11
J10
F11
F10
E11
L11
L10
E10

A11
C11
K11
K10
H11
H10
G11
G10
C10
D10

10n

U3

Production Information
3V3 XC6209B182MR
1V8 R3
1 180k
VIN
5
VOUT

C3
B2
E6
D6
C6
A6
B6
D5
C5
A5
B5
A2
C2
D2
B1
A1
C1
D1
E1
G6
F5
G5
F4
G3
F3
G2
F2
E5
H5
E4
H4
H3
E3
H2
E2
F1
G1
A4

3
CE C15

Figure 9.1: Example Application Circuit

GND
BYP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

220p (COG)

A18
A17
A16
A15
A14
A13
A12
A11
A10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
CEB
OEB

2
4
WEB

DQ14
DQ13
DQ12
DQ11
DQ10

C13 C14
2u2 2u2 3V3
DQ15/A-1

G4
VCC
F6
BYTEB
FLASH MEMORY B4
RESETB

C16

For a full BlueCore2-External reference design contact your local CSR representative.
47n
VSS
VSS
NC
NC
NC
NC
RY/BYB

MBM29LV800BA-90PBT
B3
C4

H6
H1
D4
D3
A3

U2

NOTES
NOTE: R1 MAY BE A SMALL INDUCTOR (e.g. 3.9nH, 6.8nH)
GROUND USB_D+, USB_D- IF UNUSED

Page 26 of 36
Schematic

_äìÉ`çêÉOJbñíÉêå~ä Product Data Sheet

 Package Dimensions

10 Package Dimensions
10.1 96-Ball VFBGA

Top View Bottom View

D D1

PIN A1 PIN 1
CORNER

A A

B B
C C

D D 10X e

_äìÉ`çêÉOJbñíÉêå~ä Product Data Sheet

E E

E1
F

E
F

G G
H H

J J

K K
L L

1 2 3 4 5 6 7 8 9 10 11 11 10 9 8 7 6 5 4 3 2 1
Øb 1

DETAIL K
3
0.1 Z
(A3)
A
(A2)
SEE DETAIL K A1

0.08 Z
Z 2
SEATING
PLANE

BC212015DN and BC212013DN 8x8x1mm VFBGA

DIM MIN MAX NOTES

A 0.8 1
1 DIMENSION b IS MEASURED AT THE MAXIMUM
A1 0.2 0.3 SOLDER BALL DIAMETER PARALLEL TO DATUM
PLANE Z.
A2 0.22 REF

A3 0.45 REF 2 DATUM Z IS DEFINED BY THE SPHERICAL

CROWNS OF THE SOLDER BALLS.
b 0.25 0.35

D 8 BSC
3 PARALLELISM MEASUREMENT SHALL EXCLUDE
E 8 BSC ANY EFFECT OF MARK ON TOP SURFACE OF
e 0.65 BSC PACKAGE.

D1 6.5 BSC

E1 6.5 BSC

VFBGA 96 BALLS UNIT

8X8X1mm
MM
(JEDEC MO-225)

BC212015EN and BC212013EN 6x6x1mm VFBGA

DIM MIN MAX NOTES

A 0.8 1
1 DIMENSION b IS MEASURED AT THE MAXIMUM
A1 0.2 0.3 SOLDER BALL DIAMETER PARALLEL TO DATUM
PLANE Z.
A2 0.22 REF

A3 0.45 REF 2 DATUM Z IS DEFINED BY THE SPHERICAL

CROWNS OF THE SOLDER BALLS.
b 0.25 0.35

D 6 BSC
3 PARALLELISM MEASUREMENT SHALL EXCLUDE
E 6 BSC ANY EFFECT OF MARK ON TOP SURFACE OF
e 0.5 BSC PACKAGE.

D1 5 BSC

E1 5 BSC

VFBGA 96 BALLS UNIT

6X6X1mm
MM
(JEDEC MO-225)

Figure 10.1: BlueCore2-External VFBGA Package Dimensions

BC212015-ds-001f Production Information Page 27 of 36

 Package Dimensions

10.2 96-Ball LGA

Top View D
Bottom View

PIN A1 PIN 1
CORNER

A A

B B
C C

D D 10X e
E E

E1
F F

E
G G
H H

_äìÉ`çêÉOJbñíÉêå~ä Product Data Sheet

J J

K K
L L

1 2 3 4 5 6 7 8 9 10 11 11 10 9 8 7 6 5 4 3 2 1
Øb 1

DETAIL K
1
0.1 Z
(A2)
A

(A1)
SEE DETAIL K
0.08 Z
METAL Z
LEAD SEATING
PLANE

BC212015LN and BC212013LN 6x6x0.6mm LGA

DIM MIN TYP MAX NOTES

A 0.6 0.65
1 PARALLELISM MEASUREMENT SHALL EXCLUDE
A1 0.22 REF ANY EFFECT OF MARK ON TOP SURFACE OF
PACKAGE.
A2 0.32 0.37 0.42

b 0.15 0.25

D 6 BSC

E 6 BSC
e 0.5 BSC

D1 5 BSC

E1 5 BSC

LGA 96 BALLS UNIT

6X6X0.6mm
MM
(JEDEC MO-222)

Figure 10.2: BlueCore2-External LGA Package Dimensions

BC212015-ds-001f Production Information Page 28 of 36

 Package Dimensions

10.3 96-Ball LFBGA

Top View Bottom View

D

PIN A1 PIN 1
CORNER

A A

B B
C C

D D 10X e
E E

E1
F F

_äìÉ`çêÉOJbñíÉêå~ä Product Data Sheet

G G
H H

J J

K K
L L

1 2 3 4 5 6 7 8 9 10 11 11 10 9 8 7 6 5 4 3 2 1
Øb 1

DETAIL K
3
0.1 Z
(A3)
A
(A2)
SEE DETAIL K A1

0.08 Z
Z 2
SEATING
PLANE

BC212015BN 10x10x1.4mm LFBGA

DIM MIN MAX NOTES

A --- 1.4
1 DIMENSION b IS MEASURED AT THE MAXIMUM
A1 0.3 0.4 SOLDER BALL DIAMETER PARALLEL TO DATUM
PLANE Z.
A2 0.26 REF

A3 0.8 REF 2 DATUM Z IS DEFINED BY THE SPHERICAL

CROWNS OF THE SOLDER BALLS.
b 0.35 0.45

D 10 BSC
3 PARALLELISM MEASUREMENT SHALL EXCLUDE
E 10 BSC ANY EFFECT OF MARK ON TOP SURFACE OF
e 0.8 BSC PACKAGE.

D1 8 BSC

E1 8 BSC

LFBGA 96 BALLS UNIT

10X10X1.4mm
MM
(JEDEC MO-210)

Figure 10.3: BlueCore2-External LFBGA Package Dimensions

BC212015-ds-001f Production Information Page 29 of 36

 Ordering Information

11 Ordering Information
BlueCore2-External Standard Packaging Options

Firmware: HCI/on-chip RFCOMM

Package
Interface Version Order Number
Size Shipment
Type
(mm) Method

96-ball VFBGA 6x6x1 Tape and reel BC212013BEN-E4

_äìÉ`çêÉOJbñíÉêå~ä Product Data Sheet

96-ball VFBGA
UART 6x6x1 Tape and reel BC212013BRN-E4
Lead Free

96-ball LGA 6x6x0.65 Tape and reel BC212013BLN-E4

96-ball LFBGA 10x10x1.4 Tape and reel BC212015BBN-E4

96-ball VFBGA 8x8x1 Tape and reel BC212015BDN-E4

UART and USB 96-ball VFBGA 6x6x1 Tape and reel BC212015BEN-E4

96-ball VFBGA
6x6x1 Tape and reel BC212015BRN-E4
Lead Free

96-ball LGA 6x6x0.65 Tape and reel BC212015BLN-E4

Additional Software Options: BlueCore2-External is available with additional software options. These are shown
in table below. To order these versions attach the appropriate order code to the main packaging order number,
e.g., BC212013BDN-E4-0112.

Additional Software Options

Product Family Description Order Code

BlueCore2-Ext-PC Bluetooth for Windows v1.2 English -0112
BlueCore2-Ext-Embedded Bluetooth Embedded v1.2 -4012
BlueCore2-Ext-BCHS(1) BlueCore Host Software -8010

Note:
(1)
Only available for UART interface versions.

Packaging Option
2kpcs Taped and Reeled

BC212015-ds-001f Production Information Page 30 of 36

 Contact Information

12 Contact Information

CSR U.S. CSR UK CSR Denmark _äìÉ`çêÉOJbñíÉêå~ä Product Data Sheet

1651 N. Collins Blvd. Cambridge Science Park Novi Science Park
Suite 210 Milton Road Niels Jernes Vej 10
Richardson Cambridge, CB4 0WH 9220 Aalborg East
TX75080 United Kingdom Denmark
Tel: +1 (972) 238 2300 Tel: +44 (0) 1223 692 000 Tel: +45 72 200 380
Fax: +1 (972) 231 1440 Fax: +44 (0) 1223 692 001 Fax: +45 96 354 599
e-mail: sales@csr.com e-mail: sales@csr.com e-mail: sales@csr.com

CSR Japan CSR Singapore CSR Korea

CSR KK Blk 5, Ang Mo Kio Room 1111 Keumgang Venturetel,
Miyasaka LK Bld. 3F Industrial Park 2A, #1108, Beesan-dong, DongAn-ku,
43-23, 3 Chome Shimorenjaku AMK Tech II, #07-08 Anyang-city,
Mitaka-shi, Tokyo Japan Singapore 567760 Kyunggi-do 431-050,
181-0013 Tel: +65 6484 2212 Korea
Tel: +81 0422 40 4760 Fax: +65 6484 2219 Tel: +82 31 389 0541
Fax: +81 0422 40 4765 e-mail: sales@csr.com Fax: +82 31 389 0545
e-mail: sales@csr.com e-mail: sales@csr.com

To contact a CSR representative, go to www.csr.com/contacts.htm

BC212015-ds-001f Production Information Page 31 of 36

 Document References

13 Document References
Document References Version
Specification of the Bluetooth system v1.1, 22 February 2001
Universal Serial Bus Specification v1.1, 23 September 1998

_äìÉ`çêÉOJbñíÉêå~ä Product Data Sheet

BC212015-ds-001f Production Information Page 32 of 36

 Acronyms and Definitions

14 Acronyms and Definitions

Term: Definition:
BlueCore Group term for CSR’s range of Bluetooth chips.
Bluetooth A set of technologies providing audio and data transfer over short-range radio
connections
ACL Asynchronous Connection-Less. A Bluetooth data packet.
AC Alternating Current
ADC Analogue to Digital Converter
AGC Automatic Gain Control
A-law Audio encoding standard
API Application Programming Interface

_äìÉ`çêÉOJbñíÉêå~ä Product Data Sheet

ASIC Application Specific Integrated Circuit
BCSP BlueCore™ Serial Protocol
BER Bit Error Rate. Used to measure the quality of a link
BGA Ball Grid Array
BIST Built-In Self-Test
BOM Bill of Materials. Component part list
BMC Burst Mode Controller
BSC Basic. Represents theoretical exact dimension or dimension target.
C/I Carrier Over Interferer
CMOS Complementary Metal Oxide Semiconductor
CODEC Coder Decoder
CPU Central Processing Unit
CQDDR Channel Quality Driven Data Rate
CSB Chip Select
CSR Cambridge Silicon Radio
CTS Clear to Send
CVSD Continuous Variable Slope Delta Modulation
DAC Digital to Analogue Converter
dBm Decibels relative to 1mW
DC Direct Current
DFU Device Firmware Upgrade
FSK Frequency Shift Keying
GCI General Circuit Interface. Standard synchronous 2B+D ISDN timing interface
GSM Global System for Mobile communications
HCI Host Controller Interface
Host Application’s microcontroller
Host Controller Bluetooth integrated chip
HV Header Value
IQ Modulation In-Phase and Quadrature Modulation
IAC Inquiry Access Code
IF Intermediate Frequency
ISDN Integrated Services Digital Network
ISM Industrial, Scientific and Medical
ksamples/s kilosamples per second
L2CAP Logical Link Control and Adaptation Protocol (protocol layer)
LC Link Controller
LCD Liquid Crystal Display
LGA Land Grid Array
LNA Low Noise Amplifier
LSB Least-Significant Bit
µ-law Encoding standard
MMU Memory Management Unit
MISO Master In Serial Out
OHCI Open Host Controller Interface

BC212015-ds-001f Production Information Page 33 of 36

 Acronyms and Definitions

PA Power Amplifier
PCB Printed Circuit Board
PCM Pulse Code Modulation. Refers to digital voice data
PDA Personal Digital Assistant
PIO Parallel Input Output
PLL Phase Lock Loop
ppm parts per million
PS Key Persistent Store Key
RAM Random Access Memory
REB Not Read enable
REF Reference. Represents dimension for reference use only.
RF Radio Frequency
RFCOMM Protocol layer providing serial port emulation over L2CAP
RISC Reduced Instruction Set Computer
rms root mean squared

_äìÉ`çêÉOJbñíÉêå~ä Product Data Sheet

ROM Read Only Memory
RSSI Receive Signal Strength Indication
RTS Ready To Send
RX Receive or Receiver
SCO Synchronous Connection-Oriented. Voice oriented Bluetooth packet
SD Secure Digital
SDK Software Development Kit
SDP Service Discovery Protocol
SIG Special Interest Group
SMS Short Message Service
SOC System On Chip
SPI Serial Peripheral Interface
SPP Serial Port Profile
SRAM Static Random Access Memory
SS Supplementary Services
SSI Signal Strength Indication
SSL Secure Sockets Layer
SUT System Under Test
SW Software
SWAP Shared Wireless Access Protocol
TA Terminal Adaptor
TAE Terminal Adaptor Equipment
TBD To Be Defined
TX Transmit or Transmitter
UART Universal Asynchronous Receiver Transmitter
USB Universal Serial Bus or Upper Side Band (depending on context)
VCO Voltage Controlled Oscillator
VFBGA Very Fine Ball Grid Array
VM Virtual Machine
W-CDMA Wideband Code Division Multiple Access
WEB Write Enable
www world wide web

BC212015-ds-001f Production Information Page 34 of 36

 Status of Information

Status of Information

The progression of CSR Product Data Sheets follows the following format:

Advance Information

Information for designers on the target specification for a CSR product in development.

All detailed specifications including pinouts and electrical specifications may be changed by CSR without notice.

Pre-Production Information

_äìÉ`çêÉOJbñíÉêå~ä Product Data Sheet

Final pinout and mechanical dimensions. All electrical specifications may be changed by CSR without notice.

Production Information

Final Data Sheet including the guaranteed minimum and maximum limits for the electrical specifications.

Production Data Sheets supersede all previous document versions.

The status of this Data Sheet is Production Information.

Life Support Policy and Use in Safety-Critical Applications

CSR’s products are not authorised for use in life-support or safety-critical applications.

Trademarks, Patents and Licenses

BlueCoreTM, BlueLabTM, CasiraTM, CompactSiraTM and MicroSiraTM are trademarks of CSR Ltd.

BluetoothTM and the Bluetooth logos are trademarks owned by Bluetooth SIG Inc, USA and licensed to CSR.

Windows, Windows 98, Windows 2000, Windows XP and Windows NT are registered trademarks of the Microsoft
Corporation.
2
I CTM is a trademark of Philips Corporation.
All other product, service and company names are trademarks, registered trademarks or service marks of their
respective owners.

The publication of this information does not imply that any license is granted under any patent or other rights
owned by CSR Ltd.

CSR Ltd reserves the right to make technical changes to its products as part of its development programme.

While every care has been taken to ensure the accuracy of the contents of this document, CSR cannot accept
responsibility for any errors.

BC212015-ds-001f Production Information Page 35 of 36

 Record of Changes

15 Record of Changes

Date: Revision: Reason for Change:

12 SEPT 2001 a Original publication of document.

20 OCT 2001 b Application information added.

27 MAR 2002 c Amendments made to ordering codes.

5 MAY 2002 d Production information added.

_äìÉ`çêÉOJbñíÉêå~ä Product Data Sheet

28 JUNE 2002 e RF characteristics, current consumption and 10x10
packaging information added in line with
BlueCore2-External Data Book.

28 MARCH 2003 f Changes made to 10 x 10 package order code

_äìÉ`çêÉ OJbñíÉêå~ä=mêçÇìÅí=a~í~=pÜÉÉí
qj

BC212015-ds-001f

March 2003

BC212015-ds-001f Production Information Page 36 of 36