CIRCUITS LABORATORY

EXPERIMENT 7

Design of a Single Transistor Amplifier

7.1 OBJECTIVES

The objectives of this laboratory are to:

(a) Gain experience in the analysis and design of an elementary, single transistor

amplifier,

(b) Build and thoroughly test the amplifier,

(c) Make a careful comparison between the amplifier's design specifications and the

experimental measurements with corrective action being taken for any results

that do not agree with theory.

7.2 INTRODUCTION

The single transistor amplifier is one of the major keys to understanding the

analysis and design of all analog electronic systems. Stereos, television sets, radios, long

distance telephone communication circuits, and many other practical systems employ

principles that we will explore in this experiment.

An elementary common emitter (CE) transistor amplifier will be designed from

principles reviewed here. The amplifier will be constructed during the laboratory period

and measurements carefully taken to verify that the design is correct and that all results

agree with theoretical predictions. Extensive calculations must be made to insure that the

amplifier data agrees accurately with theory before leaving the laboratory.

7-1
7.3. THEORY

7.3.1 THE BASIC CE EQUATIONS

The common emitter (CE) emitter amplifier configuration will be employed in

this experiment. The basic CE circuit is shown in Figure 7.1.

T4

50Ω T1

Function Generator

Figure 7.1. The Basic Common Emitter Amplifier

Figure 7.2 below is the small signal, midfrequency, incremental model

corresponding to our CE circuit. Note that the midfrequency model assumes that the
B C

vo RL
roc

E
Figure 7.2 Small signal mid-frequency model for a CE amplifier

impedances due to C1 and C2 are negligible compared to the impedance of related

components in the circuit. Using the Voltage Amplifier model shown in Section 7.6.1,

7-2
the various relations shown in Table 1 can be derived from the circuit of Figure 7.2. The

"Remarks" column gives further insight relative to each equation.

Table I. Fundamental Design Equations for the Common Emitter Amplifier

Quantity Equation Eq. No. Remarks

( β AC )
Theoretical BJT rπ = V T (7.1) VT = Thermal Voltage,
input resistance I CQ rπ is in ohms.

Input resistance ri = rπ//RB (7.2) ri ≈ rπ if RB >> rπ.

(T1 to common)

Output resistance ro = RC//roc (7.3) ro ≈ RC if roc >>RC.

(T4 to common)

No load incremental a = vOC = − β AC ro (7.4) Derived from Figure 7.2 with

VO
voltage gain vin rπ RL = ∞ (Open Circuit.)

Collector bias VCC − VCEQ (7.5) VCEQ ≡ vCE at transistor Q pt.

I CQ =
Current RC See Fig. 7.4

Base bias resistor (VCC − vbe (on))( β DC ) (7.6) vbe(on) ≈ 0.7 volt for Silicon
value RB = BJT transistors
I CQ
Input coupling C1 = 1/[ω1i(RS + ri)] (7.7) C1 = ≈ 1/(ω1iri) if ri >>RS
capacitor value ω1i = half power frequency

Output coupling C2 = 1/[ω1o(ro + RL)] (7.8) C2 ≈ 1/(ω1oRL) if RL >> ro

capacitor value ω1o = half power frequency

Notes: (a) See Appendix 7.6.1 on page 7-17 for a standard Voltage Amplifier model.

(b) Equation (7.4) negative sign represents inversion, i.e., a 180° phase shift.

(c) Upper case letters represent quiescent or DC values, e.g., VCEQ.

(d) Lower case letters represent incremental or AC values, e.g., vin and vo.

(e) βDC ≡ Common emitter quiescent current gain = ICQ / IBQ.

(f) βAC ≡ Common emitter incremental current gain = ΔiC / ΔiB for VCEQ constant.

(g) roc = output resistance = ΔvCE/ΔiC at constant IBQ.

7-3
This table contains many of the fundamental relations for the design of the CE amplifier.

For example, if ri, ro, and av were given in a set of specifications, Equations (7.1) through

(7.4) could be employed to find the βAC required of the transistor for a satisfactory

design. All of these equations will be employed later in our work.

7.3.2 THE INPUT COUPLING CAPACITOR

Figure 7.3 is a basic model for determining the lower cutoff frequency, f1i, for the

amplifier input coupling capacitor, Cl, but the form of the equation is the same for

determining C2. Note that vs is the source voltage, vin is the input voltage to the coupling

capacitor, ri is the input resistance of the amplifier, and vr is the voltage across ri.

Rs
+

Vs vin

Figure 7.3: Equivalent circuit for coupling capacitor

Using phasors and applying the voltage divider rule we find that
Vr = ri
(7.8)
V s Rs + 1 + r i
jωC1

where ω is the radian frequency of vs. Equation (7.8) yields

Vr ri ri
= =
Vs 1 2 (7.9)
( R S + ri ) + ⎛ 1 ⎞
( R S + r i ) + ⎜⎜
jω C1
2
⎟⎟
⎝ ω C1 ⎠
At radian frequencies well above cutoff, Equation (7.9) reduces to
Vr ri
= (7.10)
Vs (R S + r i )

7-4
From Equation (7.10), it is clear that the lower cutoff frequency or the lower -3dB
Vr ri
frequency occurs when = . Denoting the lower cutoff frequency by
Vs 2 (R S + r i )
ω1i, we get
2
⎛ ⎞
2 2
Vr ri ri
= ⎜⎜ ⎟ =
⎟
⎝ 2 (R S + r i ) ⎠
2
Vs ⎛ 1 ⎞
⎜⎜ ⎟⎟ + (R S + r i )2 (7.11)
⎝ ω 1i C ⎠
1
From Equation (7.11), we see that ω1i = 2π f 1i = or, alternatively,
(R S + r i )C1
1 1
C1 = =. (7.12)
ω 1i (R S + r i ) 2πf 1i (R S + r i )

1 1
Note that C1 ≈ = if ri >> RS. See Equation (7.7) in Table I.
ω i1 r i 2πf 1i r i
As an example, if an amplifier has an input resistance ri of 1 kΩ and it is desired

to capacitively couple a low impedance input signal vs to it so that the cutoff frequency,

f1, is 200 Hz, we substitute into Equation (7.7) and find

1 10 −5
C1 = = = 7.96(10) −7 = 0.796 μ F . (7.13)
2π (200)(1000) 4π

7.3.3. THE LOAD LINE

The load line is a valuable design tool, particularly in determining the effect of large

signals on transistor circuit performance. In Experiment 6, the emphasis was on the static

load line with a slope = -1/RC and there was no capacitively coupled load. Equivalently,

load was RL = ∞. When RL ≠ ∞ , the AC signal "sees" the dynamic load line described

below.

Figure 7.4 shows idealized transistor characteristics with both static and dynamic

of load lines. First, the static line is constructed in the usual way and the quiescent point

established. Then, the dynamic line having a slope of -1/(RL||RC) is placed on the graph

with the new line also passing through the same Q point.

7-5
 VCE(Sat) VCEQ' VCEQ VCED' VCED VCC

Figure 7.4: Static and Dynamic Load Lines

From the static line it is seen that vo = vCE has a positive swing of S+ = (VCC - VCEQ)

before the transistor is cutoff and a negative swing of S- = (VCE(Sat) - VCEQ) ≈ -VCEQ

before saturation. To get the maximum positive and negative voltage swings with a static

line, the operating point is frequently placed near the center, i.e., VCEQ = 0.5 VCC, which

is termed midpoint biasing. In this case, the total peak-to-peak output voltage vopp = (S+ -

S-) ≈ 2 VCEQ = VCC. On the other hand, the dynamic line produces cutoff at a lower

voltage and has a smaller positive swing of S+ = (VCED - VCEQ) so that the maximum

unclipped vopp = 2 (VCED - VCEQ). The positive swing S+ for the dynamic line may be

increased by establishing a new quiescent point called Q' at VCEQ' as shown in Figure 7.4.

Observe that the slopes of both dynamic lines are the same, but the Q' point is moved to

the left along the static line. This process can be done either analytically or by inspection

of the graph. Usually, Q' is moved to a new point where a symmetric swing is

established for both positive and negative going signals. The result is that vopp = 2 VCEQ'

where VCEQ' = [RL/(RC + 2 RL)] VCC.

7-6
 7.3.4 Nonlinear Response and Distortion

From the actual characteristic for the 2N718A transistor shown in Figure 7.5, it is

seen that an actual transistor has a non-ideal family of curves. Equal increments in IB are

not uniformly spaced on the graph.

Figure 7.5: A brief data sheet for the 2N718A transistor.

Moreover, the pattern of the IB curves changes with both VCE and IC. Thus, a load line on

the graph with a Q point near the center presents a different effective βAC to parts of a

sinewave input signal falling some distance on either side of Q. The result is distortion in

the output signal, i.e., it is no longer a pure sinewave.

7-7
7.3.5 Design Specifications
Specifications may occur in one of several classes. At one extreme is the situation

where the amplifier is over specified; i.e., too many variables are constrained. Consider

the following elementary set as a case of over specification: avo = -200, βAC = 50, RC =

2kΩ and rπ = 1kΩ. Substitute into Equation (7.4) to obtain

(−50)(2kΩ)
aVo = = 100 ≠ 200 (7.14)
1kΩ
The above is a trivial example of an invalid specification, but the designer must be alert

to more subtle conflicting specifications. At the other extreme is a very common situation

where the amplifier is under specified, e.g., avo = -200 and βAC = 10 are the only

constraints. Here the designer has a infinite number of satisfactory values for RC and rπ

for Equation (7.4). Nevertheless, the values selected for the free parameter(s) must first

be consistent with good electronic engineering practices, and, beyond that, they must be

the best possible fit within the context of the application as it is understood by the

engineer. A common variation of under specification happens when one or more

parameters are specified as "greater than or equal to". Since components have tolerances

and values that often change with age, it is good practice to take advantage of the

"inequality" specifications, but by "how much" involves judgment and knowledge of the

application. For simplicity we do not consider cost here, but be aware that in practice it

frequently is one of the most critical parameters.

7-8
7.3.6 A Design Example

6.1 Specifications. The desired design is a CE amplifier with the following

specified parameters:

RC = 2 kΩ, VCEQ = 3 V, | avo | > 250, and f1i ≤ 200 Hz.

The load resistance is to also be the collector resistor of the transistor circuit, i.e., C2 is

omitted and RL = ∞. Characteristics given for the transistor are βAC = βDC = 50 and ICmax

= 9 mA. Standard 5% resistors are to be employed. See Appendix II in Section 7.6.2.

6.2 The Design Process. The equations needed for our work are numbered

sequentially and found in Table 1. From the above specification that RC = 2 kΩ, which is

a standard 5% resistor, and assuming that roc is very large, we get from Eq. (7.3) that ro =

2 kΩ. Since VCEQ = 3 V, then VCC >> 6 V. Arbitrarily, try VCC = 9 V. Then from

Equations (7.5) and (7.1) we get

VCC − VCEQ 9−3
I CQ = = = 3mA .
RC 2000 (7.15)
and
(26) β AC (26)(50)
rπ = = = 433.3Ω . (7.16)
I CQ 3
From Equation (7.4),

β AC RC (50)(2)
aVo = − =− = −231 (7.17)
rπ 0.433

which does not satisfy the specification. Thus, we must modify some of the previous

values to get a satisfactory avo.

From the previous work, we observe that a larger VCC will lead to a larger IC,

leading to a smaller rπ and finally to a larger avo. So, as a first iteration in the design, we

will increase VCC to 20 V.

7–9
Recomputing, from Equation (7.5),

20 V − 3 V
I CQ = = 8.5 mA ; (7.18)
2 kΩ
and from Equation (7.1),
(26)(50)
rπ = = 153 Ω ; (7.19)
8.5
and from Equation (7.4),

(50)(2 kΩ) (7.20)

aVo = − = − 654 .
.153 kΩ

Since avo is so much larger than the specification requires and since ICQ is close to

the specification limit, a reasonable approach is to select VCC about midway between 9 V

and 20 V, say at VCC = 15 V. Trying this value and using the same set of equations, we

find:

ICQ = 6 mA, which is significantly less than the maximum.

rπ = 217 Ω, which is acceptable since its value is unspecified, and

avo = 461 V/V, which is well above the specified minimum.

The design is completed by finding RB and C1 . From Equation (7.6),

(VCC − 0.7) (15 V − 0.7 V )(50) (7.21)

RB = ( β DC ) = = 119 kΩ ≈ 120 kΩ ,
I CQ 6

which is a standard 5% resistor. Note that 120kΩ >> ri = 0.217kΩ; therefore, our

original assumption of RB >> rπ is satisfied for Equation (7.2). The change to RB = 120

kΩ has negligible effect on several previous parameters, e.g., ICQ = 5.96 mA instead of 6

mA, but these are of no practical consequence for the design. Finally, from Equation

(7.7),
1 1
C1 = = = 3.7 μF .
ω 1i ri 2π (200)(217) (7.22)

The next largest standard sized capacitor would be suitable.

7 – 10
7.4 Experiment

7.4.1 Design Problem

[Link] Design Specifications

Design an open circuit (RL = ∞) common emitter transistor amplifier to meet the

following characteristics: ri ≥ 1 kΩ , ro < 2 kΩ, 160 ≤ | avo | ≤ 240, f1i ≤ 400 Hz, vop-p ≥ 10

V where vop-p is the unclipped peak-to-peak output voltage. Select an integer value for

supply voltage VCC and assume VCC has an accuracy of ±2 %. A 2N2222A transistor with

βDC = βAC = 175 ± 25 and roc > 25 kΩ is to be used. The base and/or collector resistances

may each use two standard ± 5% resistors combined in series

[Link] Initial Design

As a laboratory team, you are to design a capacitor coupled transistor amplifier that

satisfies the design specifications based on the nominal transistor characteristics given in

Section [Link]. The design must include a circuit diagram of the transistor amplifier and

values must be defined for all components shown on the diagram. These may be shown

directly on the circuit diagram or in a table. As a team, you must present the initial

design to the instructor for approval prior to obtaining a 2N2222A transistor.

[Link] Revised Design

Obtain a 2N2222A transistor and use the Tektronix 571 Curve Tracer to obtain its

characteristics. Draw the load line for your initial design on the transistor characteristics

and mark the design Q point. For this Q point, calculate the βDC, βAC, and roc for the

transistor. If the transistor meets the requirements, complete a revised design by

modifying the base resistance and present it to the instructor. If the transistor does not

meet requirements, obtain a different transistor and repeat the above steps.

7 - 11
[Link] Final Design

Your final design must operate at the initial design Q point, i.e., the initial design VCEQ

and ICQ. Once you have assembled your amplifier per Section 7.4.4, turn on power, allow

it to stabilize at operating temperature, and measure VCEQ and ICQ. If necessary, change

the base resistance to obtain the correct Q point. Record any design changes made.

7.4.2 Warning

The transistor is a small device with little thermal capacity. Even an extremely

brief over-voltage or over-current fault will destroy the device or permanently alter its

properties. Therefore, you must not attempt to build a transistor circuit or alter any

connections while the power is on. Also, you must not apply any input signal voltage

directly to the base of the transistor without a series resistor or capacitor.

7.4.3 Equipment List

1 Transistor curve tracer

1 Motorola 2N2222A transistor (150 mA, 60 V) with βDC = βAC = 175 ± 25
2 Capacitors – values determined by design calculations
4 Quarter watt, 5% resistors (Values selected from 10% list in Sect. 7.6.2.)
1 0 – 40 V DC power supply
2 10x Probes
1 Digital Oscilloscope
1 HP 33120A Function Generator
1 50Ω, 20dB signal attenuator
1 Decade resistor box
3 Digital multimeters (DMMs)

7.4.4 Experimental Procedure

[Link] General Guidelines

(a) A digital oscilloscope, with its sensitive measurement capability, high input

resistance, and low input capacitance, can be used to make accurate signal voltage

measurements and should be used in preference to the DMM for this purpose. To

7 – 12
accurately measure power supply or bias voltages, the DMM is preferable.

(b) Since the amplifier that is to be designed is relatively high gain, the LOW output

of the HP33120A function generator and a 50Ω, 20dB signal attenuator must be used

for the signal source. Since the attenuator output impedance is 50Ω, its value can often

be neglected in gain measurements, but should be taken into account in measuring ri.

(c) Frequency can most conveniently be measured with the oscilloscope. Do not

depend on the accuracy of the dial reading of the HP 33120A function generator.

[Link] Detailed Laboratory Steps

(a) Perform the initial and revised designs per paragraphs [Link] and [Link].

(b) Construct your amplifier circuit using 1 or 2 standard resistors for collector

resistance (RC) and a 1 kΩ shunt resistor and the decade box in series for the base

resistance (RB). See the circuit shown in Figure 7.1. Adjust the power supply voltage to

the design VCC value ± 2% before connecting the amplifier.

(c) With vs = 0, measure the bias voltages and currents, e.g., VCEQ, ICQ, VBEQ, and IBQ.

Refer to Experiment 6 for the best ways to measure ICQ and IBQ. If during this step the

measured values of VCEQ and ICQ fail to agree with the design values, adjust the decade

box resistance to change the base resistance as needed to achieve the Q point values. Be

sure to record any changes made for this amplifier final design.

(d) Replace the base resistance with 1 or 2 standard resistors in series and verify that

the correct Q point is obtained.

(e) With vs set at mid-frequency value (40 kHz) and an output voltage vo = 2 V RMS:

(1) Determine avo using the digital oscilloscope. Note RL = ∞, and vin is

measured just to the source side of C1. See Figure 7.1.

7 – 13
 (2) Place a decade box with resistance RDB = 0 Ω between the Function Generator

and the coupling capacitor (See Figure 7.1) and measure vo with the scope.

Increase RDB until vo drops to one-half its original value, which is the "half

voltage method" for determining ri. (The decade box should yield at least

three significant figures.) Now remove the decade box from the circuit and

measure and record its value.

(3) Similar to step (e.2) directly above, measure ro by placing a decade box in the

RL position with RDB = 999,999 Ω. Be sure C2 = C1 is large enough so that

its impedance has a negligible effect on the ro measurement. Measure vo with

the scope while adjusting RDB until vo drops to one-half its original value,

yielding the measured ro value. Record ro and return the circuit to RL = ∞.

If any of the measured values fall outside the specification limits of paragraph [Link],

you must note this and check with the instructor before proceeding any further.

(f) Ranging from about 2 octaves below the lower cutoff up to 2 octaves above the

upper cutoff, take appropriate frequency response data with the oscilloscope. For this

run, RL = ∞ and RS ≈ 50 Ω. Note that vin should be measured and recorded to be sure

it stays essentially constant. Use the scope's frequency measuring feature to set

accurate frequency values, but check them using the function generator's frequency scale.

Frequency response testing can best be accomplished as follows. First, with vin at

a mid-frequency value, set vo to 5.66 V peak-to-peak (2 V RMS) by observing vo on the

scope and adjusting the magnitude of vin. Next, increase and decrease the frequency of vs

in order to determine the lower cut-off frequency (fl) and the upper cut-off fequency (f2),

respectively. Since the cut-off frequency is defined as the half-power point, then it

follows that vo = 0.707 (5.66 V) = 4 V peak-to-peak at the respective cut-off frequencies.

7 - 14
 To obtain adequate data points near the two cut-off frequencies, record the peak-

to-peak values of vo and vin at the following frequencies without adjusting vs:

f1 / 4 two octaves down from the lower cut-off frequency

f1 / 2 one octave down from the lower cut-off frequency
f1 lower cut-off frequency
2 f1 one octave up from the lower cut-off frequency
4 f1 two octaves up from the lower cut-off frequency
10 f1 one decade up from the lower cut-off frequency
fo/4 two octaves down from the mid-range frequency
fo mid-range frequency where fo = √f1f2
4 f0 two octaves up from the mid-range frequency
f2 /10 one decade down from the upper cut-off frequency
f2 / 4 two octaves down from the upper cut-off frequency
f2 / 2 one octave down from the upper cut-off frequency
f2 upper cut-off frequency
2 f2 one octave up from the upper cut-off frequency
4 f2 two octaves up from the upper cut-off frequency

(g) Return to a mid-frequency value, i.e., fo, and take data, vo vs. vin with the scope to

determine the linearity of the amplifier from vo = 0.5 V RMS until obvious clipping

occurs. When clipping occurs, instead of being a pure sinusoid, vo will have a significant

flattening, either on the top due to cutoff or on the bottom due to saturation or both.

Monitor vin and vo with separate oscilloscope channels. Record where distortion starts by

noting the value of vo where the gain (avo = |vo/vin|) begins to noticeably decrease. Also,

record the value of vo where clipping occurs.

(h) Connect a load resistor RL = 2RC using a coupling capacitor C2 = C1. Now record

the value of vo where clipping occurs. This value should be noticeably smaller than that

of Section (g). Also, draw the dynamic load line on the transistor characteristics and

compare measured and predicted results.

7 - 15
(i) Graphically determine a new Q' point that will lead to the largest total possible

output voltage swing with RL = 2RC. Plot the dynamic load lines through Q and Q'. Note

that it will be necessary to change the value of base resistance RB when implementing the

new operating point, Q'. Now repeat part (h) for a new dynamic quiescent point Q'.

7.5. Report

7.5.1 Present the curve tracer characteristics for your 2N2222A transistor and show the

construction of your static load line. Be sure to label your Q point including IBQ, VCEQ,

and ICQ. Show all the data points used to determine βDC, βAC, and roc on the characteristics

and also show your calculations for βDC, βAC, and roc.

7.5.2 Present the initial and revised designs that were approved by the instructor.

Present all pertinent information, e.g., ri, ro, avo, vop-p (output voltage swing), f1i, RB, RC,

C1, VCC, VCEQ, ICQ, IBQ, βDC, βAC, rπ, roc, etc., on the table provided.

7.5.3 Present a comparison showing your approved amplifier initial, revised, and final

design values and the actual measurements made during test. Include all pertinent

information, e.g., ri, ro, av, vop-p (output voltage swing), f1i, RB, RC, C1, VCC, VCEQ, ICQ,

IBQ, βDC, βAC, rπ, roc, etc., on the table provided.

7.5.4 Make a graph showing the measured frequency response of your amplifier by

plotting |avo| = |vo|/|vin| versus frequency. Use a log scale for frequency. Indicate the half

power points and the amplifier bandwidth.

7.5.5 Make a graph for the linearity measurements made at mid-frequency by plotting

vo versus vin. Indicate on your graph where distortion and clipping each begin.

7.5.6 Show the construction of your dynamic load lines with the Q & Q' point(s)

included as related to Sect [Link] (h) and (i) and calculate vopp for each case.

7 - 16
7.5.7 The vopp is described on page 7-6 and measurements are taken in experiment steps

(g), (h), and (i) of Section.[Link]. Make a table presenting the calculated and measured

data for vopp (1) without RL and (2) with RL using both the Q and Q' operating points.

7.5.8 Derive Equation (7.4) in Table I on page 7-3 from basic principles.

7.6 Appendices

7.6.1 Appendix I - Standard Amplifier Models

There are four standard amplifier models as shown in the table below. Even though the

transistor is a current controlled device, we will make use of the Voltage Amplifier for

this experiment since it is the most often used model.

7 - 17
 7.6.2 Appendix II - Resistor Value Multipliers

These values all apply to ± 5% tolerance resistors. Resistors with ± 10% tolerance are

only available in values marked by a *. The multipliers are:

*
1.0* 1.5* 2.2 3.3* 4.7* 6.8*

1.1 1.6 2.4 3.6 5.1 7.5

1.2* 1.8* 2.7* 3.9* 5.6* 8.2*

1.3 2.0 3.0 4.3 6.2 9.1

7.7 References

1. Sedra, Adel S. and Smith, Kenneth C., Microelectronic Circuits, 5th Edition,

Oxford University Press, New York, 2004

2. Boylestead, Robert and L. Nashelsby, Electronic Devices and Circuit Theory (4th

ed.), Prentice-Hall, Englewood Cliffs NJ, 1987.

3. Chirlian, Paul M., Analysis and Design of Integrated Electronic Circuits, Harper

and Row, Cambridge MA, 1981.

4. Grinich, Victor H., and H. G. Jackson, Introduction to Integrated Circuits,

McGraw-Hill, New York NY, 1970.

5. Millman, Jacob, Microelectronics - Digital and Analog Circuits and Systems,

McGraw-Hill, New York NY, 1979.

6. Mitchell, Jr., F. H., and F. H. Mitchell, Introduction to Electronics Design,

Prentice-Hall, Englewood Cliffs NJ, 1988.

7 - 18