SHRI RAMDEOBABA COLLEGE OF ENGINEERING & MANAGEMENT,
NAGPUR
DEPARTMENT OF ELECTRONICS ENGINEERING
M. TECH (VLSI DESIGN)
COURSE NAME : CMOS DIGITAL CIRCUIT DESIGN LAB (ENP551)
SESSION 2016-17
List of Experiments
1) Design a CMOS inverter.
a) for equal rise/fall times of the output and for rise time of the output is greater than fall
time of the output. State the parameters involved in getting the difference in rise time and
fall time.
b) Obtain different values of power consumed on varying the load and rise and fall time of
the pulse? Compare and analyze your results. Support your comments with proper
mathematical expression.
c) Observe the effect of ratio βn/βp and temperature on the transfer characteristics of an
inverter.
2) To plot the effect of variation of following parameters on the working of NMOS and PMOS
transistor for Level1, Level3 and BSIM MOS transistor Models.
a) Variation in Threshold voltage
b) Variation in mobility
c) Variation in oxide thickness
d) Variation in gate voltage
3) Draw the Layout of CMOS inverter for equal rise and fall times. Extract the layout and
simulate the netlist in SPICE.
4) Sketch a 3-input NAND gate (in static CMOS) and 3-input NOR gate (in static CMOS) with
transistor widths chosen to achieve equal rise and fall resistance as a unit inverter. What is
the value for Logical Effort? Compare these two universal gates.
5) Draw schematic of D flip flop using DSCH tool and observe its transient response. Extract
the Verilog code and generate the layout in microwind. Observe DRC and verify LVS.
6) Draw the layout of 6 Transistor SRAM cell. Extract the netlist and simulate for read and
write operations.
7) Mini Project.
ENP 551: CMOS Digital Circuit Design Lab
LAB 1a & b)
Objective: Design a CMOS inverter.
a) for equal rise/fall times of the output and for rise time of the output is greater than fall
time of the output. State the parameters involved in getting the difference in rise time and
fall time.
b) Obtain different values of power consumed on varying the load and rise and fall time of
the pulse? Compare and analyze your results. Support your comments with proper
mathematical expression.
Tool Used : Tanner Tool for simulation
Shematic:
For Equal Rise and Fall Times
Spice Netlist For Equal Rise And Fall Time
* SPICE export by: SEDIT 13.00
* Export time: Fri Aug 05 11:33:00 2016
* Design: inv
* Cell: Cell0
* View: view0
* Export as: top-level cell
* Export mode: hierarchical
* Exclude .model: no
* Exclude .end: no
* Expand paths: yes
* Wrap lines: no
* Root path: C:\Suma\inv
* Exclude global pins: no
* Control property name: SPICE
********* Simulation Settings - General section *********
.lib "C:\Documents and Settings\admin\My Documents\Tanner EDA\Tanner Tools
v13.0\Libraries\Models\Generic_025.lib" TT
********* Simulation Settings - Parameters and SPICE Options *********
*-------- Devices: SPICE.ORDER > 0 --------
MNMOS_1 N_1 N_2 Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MPMOS_1 N_1 N_2 N_3 N_3 PMOS W=5.25u L=250n AS=4.725p PS=12.3u AD=4.725p
PD=12.3u
VVoltageSource_1 N_3 Gnd DC 5
VVoltageSource_2 N_2 Gnd PULSE(0 5 0 5n 5n 95n 200n)
.PRINT TRAN V(N_1)
.PRINT TRAN V(N_2)
********* Simulation Settings - Analysis section *********
.tran 1n 400n
********* Simulation Settings - Additional SPICE commands *********
.end
Schematic For Transfer Characteristics With Equal Rise And Fall Time
Spice Netlist For Transfer Characteristics For Equal Rise And Fall Time
* SPICE export by: SEDIT 13.00
* Export time: Fri Aug 05 11:46:45 2016
* Design: inv
* Cell: Cell1
* View: view0
* Export as: top-level cell
* Export mode: hierarchical
* Exclude .model: no
* Exclude .end: no
* Expand paths: yes
* Wrap lines: no
* Root path: C:\Suma\inv
* Exclude global pins: no
* Control property name: SPICE
********* Simulation Settings - General section *********
.lib "C:\Documents and Settings\admin\My Documents\Tanner EDA\Tanner Tools
v13.0\Libraries\Models\Generic_025.lib" TT
********* Simulation Settings - Parameters and SPICE Options *********
*-------- Devices: SPICE.ORDER > 0 --------
MNMOS_1 N_1 N_2 Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MPMOS_1 N_1 N_2 N_3 N_3 PMOS W=5.25u L=250n AS=4.725p PS=12.3u AD=4.725p
PD=12.3u
VVoltageSource_1 N_3 Gnd DC 5
VVoltageSource_2 N_2 Gnd DC 5
.PRINT DC output='V(N_1)'
.PRINT DC input ='V(N_2)'
********* Simulation Settings - Analysis section *********
.dc lin VVoltageSource_2 0 5 .1
********* Simulation Settings - Additional SPICE commands *********
.end
For Current And Power Waveforms With load capacitor 1pf
SPICE NETLIST FOR CURRENT POWR RELATIONSHIP With load capacitor 1pf
* SPICE export by: SEDIT 13.00
* Export time: Fri Aug 05 11:53:28 2016
* Design: inv
* Cell: Cell2
* View: view0
* Export as: top-level cell
* Export mode: hierarchical
* Exclude .model: no
* Exclude .end: no
* Expand paths: yes
* Wrap lines: no
* Root path: C:\Suma\inv
* Exclude global pins: no
* Control property name: SPICE
********* Simulation Settings - General section *********
.lib "C:\Documents and Settings\admin\My Documents\Tanner EDA\Tanner Tools
v13.0\Libraries\Models\Generic_025.lib" TT
********* Simulation Settings - Parameters and SPICE Options *********
*-------- Devices: SPICE.ORDER > 0 --------
CCapacitor_1 N_4 Gnd 1p
MNMOS_1 N_1 N_2 Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MPMOS_1 N_1 N_2 N_3 N_3 PMOS W=5.25u L=250n AS=4.725p PS=12.3u AD=4.725p
PD=12.3u
VVoltageSource_1 N_3 Gnd DC 5
VVoltageSource_2 N_2 Gnd PULSE(0 5 0 5n 5n 95n 200n)
.PRINT TRAN output='V(N_1)'
.PRINT TRAN input ='V(N_2)'
VAmmeter_1 N_1 N_4 0v
.PRINT TRAN I(VAmmeter_1)
.PRINT TRAN ID(CCapacitor_1)
.PRINT TRAN P(VVoltageSource_1)
********* Simulation Settings - Analysis section *********
.tran 1n 400n
********* Simulation Settings - Additional SPICE commands *********
.end
Results Obtained in the Laboratory Excercise
Transient Waveform of Output
Transfer Characteristics for equal Rise And Fall Time
Currnent and Power Waveforms
With load capacitor 0.1pf
With load capacitor 1pf
With load capacitor 10pf
Conclusion
1) The inverter with equal Rise and Fall time can be done by considering the equation
βn = µn Cox Wn/Ln for nMOS transistor and
βp = µpCox Wp/Lp for pMOS transistor
for constant cox, capacitance of oxide and legth we have
βn/ βp =( µn / µ p) X (Wn/ W p)
Normally ratio of ( µn / µ p) is fixed as 2.78 , so we are taking Wp = 2 to 3 times of Wn
Here in this example Wn = 2.5 and Wp =5.25 and thus rise and fall time is almost equal.
By using vertical cursor from the output waveform measured that the rise time = fall
time = 4.87ns
2) By increasing the load capacitance from the output waveform it is observed that there is
increase in Power Consumption. Width of dynamic power consumption is widens and
static power consumption goes on decreasing. This is because of the fact that dynamic
power consumption is given by the equation
Pd = f Cl Vdd2
Lab 1c)
Objective: Observe the effect of ratio βn/βp and temperature on the transfer characteristics of an
inverter.
Tool Used : Tanner Toll for simulation
Shematic For βn/βp Analysis
Spice Netlist For βn/βp Analysis
* SPICE export by: SEDIT 13.00
* Export time: Sat Aug 06 10:42:01 2016
* Design: inv
* Cell: Cell6
* View: view0
* Export as: top-level cell
* Export mode: hierarchical
* Exclude .model: no
* Exclude .end: no
* Expand paths: yes
* Wrap lines: no
* Root path: C:\Suma\inv
* Exclude global pins: no
* Control property name: SPICE
********* Simulation Settings - General section *********
.lib "C:\Documents and Settings\admin\My Documents\Tanner EDA\Tanner Tools
v13.0\Libraries\Models\Generic_025.lib" TT
.param width=6u
********* Simulation Settings - Parameters and SPICE Options *********
*-------- Devices: SPICE.ORDER > 0 --------
MNMOS_1 N_3 N_1 Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MPMOS_1 N_3 N_1 N_2 N_2 PMOS W=width L=250n AS=4.725p PS=12.3u AD=4.725p
PD=12.3u
VVoltageSource_1 N_2 Gnd DC 5
VVoltageSource_2 N_1 Gnd DC 5
.PRINT DC output='V(N_3)'
********* Simulation Settings - Analysis section *********
.dc lin VVoltageSource_2 0 5 .1
.step lin width .5u 7u 1u
********* Simulation Settings - Additional SPICE commands *********
.end
Schematic forTemperature Analysis
Spice netlist for temperature analysis
* spice export by: sedit 13.00
* export time: sat Aug 06 11:10:04 2016
* design: inv
* cell: cell7
* view: view0
* export as: top-level cell
* export mode: hierarchical
* exclude .model: no
* exclude .end: no
* expand paths: yes
* wrap lines: no
* root path: c:\suma\inv
* exclude global pins: no
* control property name: spice
********* simulation settings - general section *********
.lib "c:\documents and settings\admin\my documents\tanner eda\tanner tools
v13.0\libraries\models\generic_025.lib" tt
*-------- devices: spice.order < 0 --------
.temp 0 10 25 40 55 70 150
********* simulation settings - parameters and spice options *********
*-------- devices: spice.order > 0 --------
Mnmos_1 n_1 n_2 gnd gnd nmos w=2.5u l=250n as=2.25p ps=6.8u ad=2.25p pd=6.8u
Mpmos_1 n_1 n_2 n_3 n_3 pmos w=5.25u l=250n as=4.725p ps=12.3u ad=4.725p pd=12.3u
Vvoltagesource_1 n_3 gnd dc 5
Vvoltagesource_2 n_2 gnd dc 5
.print dc output='v(n_1)'
********* simulation settings - analysis section *********
.dc lin vvoltagesource_2 0 5 .1
********* simulation settings - additional spice commands *********
.end
Results Obtained in the Laboratory Exercise
Waveforms for different value of βn/βp
With pMOS Width 5.5
with pMOS Width 2.5
with pMOS Width 0.5
Waveform for forTemperature Analysis
Conclusion
As we know that for an Inverter if we vary the width of pMOS then VTC curv is varies
according to the relation
βn/ βp =( µn / µ p) X (Wn/ W p)
Normally ratio of ( µn / µ p) is fixed as 2.78 , so here take Wn = 2.5 fixedand vary Wp = 0.5 to 7
got the waveform as shown. From it is clear that to get the equal on and off time make Wp= 2 to
3 times of Wn.
LAB 3)
Objective: Draw the Layout of CMOS inverter for equal rise/fall times in 120nm
technology. Extract the layout and simulate the resulting SPICE net list for proper
operation.
Tool Used : Microwind31
Layout
Netlist
*CIRCUIT C:\Suma\ENP 501\Layout501\INVLAYOUT.MSK
* IC Technology: CMOS 0.12µm - 6 Metal
*
VDD 1 0 DC 1.20
VIP 6 0 DC 0 PULSE(0.00 1.20 0.23N 0.03N 0.03N 0.23N 0.50N)
*
* List of nodes
* "OUTPUT" corresponds to n°3
* "IP" corresponds to n°6
*
* MOS devices
MN1 0 6 3 0 N1 W= 0.24U L= 0.12U
MP1 1 6 3 1 P1 W= 0.60U L= 0.12U
*
C2 1 0 0.475fF
C3 3 0 0.304fF
C4 1 0 0.202fF
C6 6 0 0.153fF
* n-MOS BSIM4 :
* low leakage
.MODEL N1 NMOS LEVEL=14 VTHO=0.40 U0=0.050 TOXE= 2.0E-9 LINT=0.010U
+K1 =0.450 K2=0.100 DVT0=2.300
+DVT1=0.540 LPE0=23.000e-9 ETA0=0.080
+NFACTOR= 1.6 U0=0.050 UA=3.000e-15
+WINT=0.020U LPE0=23.000e-9
+KT1=-0.060 UTE=-1.800 VOFF=0.050
+XJ=0.150U NDEP=170.000e15 PCLM=1.100
+CGSO=100.0p CGDO=100.0p
+CGBO= 60.0p
*
* p-MOS BSIM4:
* low leakage
.MODEL P1 PMOS LEVEL=14 VTHO=-0.45 U0=0.018 TOXE= 2.0E-9 LINT=0.010U
+K1 =0.450 K2=0.100 DVT0=2.300
+DVT1=0.540 LPE0=23.000e-9 ETA0=0.080
+NFACTOR= 1.6 U0=0.018 UA=1.500e-15
+WINT=0.020U LPE0=23.000e-9
+KT1=-0.060 UTE=-1.800 VOFF=0.050
+XJ=0.150U NDEP=170.000e15 PCLM=0.700
+CGSO=100.0p CGDO=100.0p
+CGBO= 60.0p
*
* Transient analysis
*
* (Winspice)
.options temp=27.0
.tran 0.1N 5.00N
.print V(6) V(3) > out.txt
.plot V(6) V(3)
.END
Results Obtained in the Laboratory Excercise
Result From Layout
Result From T Spice
ENP 501: CMOS Digital Circuit Design Lab
LAB 4)
1) Objective: Sketch a 4-input NAND gate (in static CMOS) with transistor widths chosen
to achieve equal rise and fall resistance as a unit inverter. Draw the Layout and show the
simulation results. What is the value for Logical Effort? Comment on your Simulation
Result.
Tool Used : Microwind31,Tanner Tool 13.0
Schematic
Net list
* SPICE export by: SEDIT 13.00
* Export time: Thu Aug 30 07:53:25 2012
* Design: 4nand
* Cell: Cell0
* View: view0
* Export as: top-level cell
* Export mode: hierarchical
* Exclude .model: no
* Exclude .end: no
* Expand paths: yes
* Wrap lines: no
* Root path: C:\Suma\4nand
* Exclude global pins: no
* Control property name: SPICE
********* Simulation Settings - General section *********
.lib "C:\Documents and Settings\admin\My Documents\Tanner EDA\Tanner Tools
v13.0\Libraries\Models\Generic_025.lib" TT
********* Simulation Settings - Parameters and SPICE Options *********
*-------- Devices: SPICE.ORDER > 0 --------
MNMOS_1 N_2 N_1 N_7 Gnd NMOS W=4u L=250n AS=3.6p PS=9.8u AD=3.6p PD=9.8u
MNMOS_2 N_7 N_3 N_9 Gnd NMOS W=4u L=250n AS=3.6p PS=9.8u AD=3.6p PD=9.8u
MNMOS_3 N_9 N_4 N_11 Gnd NMOS W=4u L=250n AS=3.6p PS=9.8u AD=3.6p PD=9.8u
MNMOS_4 N_11 N_5 Gnd Gnd NMOS W=4u L=250n AS=3.6p PS=9.8u AD=3.6p PD=9.8u
MPMOS_1 N_2 N_1 N_6 N_6 PMOS W=2u L=250n AS=1.8p PS=5.8u AD=1.8p PD=5.8u
MPMOS_2 N_2 N_3 N_6 N_6 PMOS W=2u L=250n AS=1.8p PS=5.8u AD=1.8p PD=5.8u
MPMOS_3 N_2 N_4 N_6 N_6 PMOS W=2u L=250n AS=1.8p PS=5.8u AD=1.8p PD=5.8u
MPMOS_4 N_2 N_5 N_6 N_6 PMOS W=2u L=250n AS=1.8p PS=5.8u AD=1.8p PD=5.8u
VVoltageSource_5 N_6 Gnd DC 5
VVoltageSource_1 N_1 Gnd BIT({10001} )
VVoltageSource_2 N_3 Gnd BIT({00101} )
VVoltageSource_3 N_4 Gnd BIT({00011} )
VVoltageSource_4 N_5 Gnd BIT({00001} )
.PRINT TRAN O/P='V(N_2)'
.PRINT TRAN IPB='V(N_3)'
.PRINT TRAN IPC='V(N_4)'
.PRINT TRAN IPD='V(N_5)'
.PRINT TRAN IPA='V(N_1)'
********* Simulation Settings - Analysis section *********
.tran 1n 400n
********* Simulation Settings - Additional SPICE commands *********
.end
Result
Simulation O/P From Schematic
Similar with NOR Gate and Compare the results.
Lab 5
OBJECTIVE: Implement D F/F. Define and estimate setup time for your design through
spice simulation.
SCHEMATIC:
SPICE NETLIST:-
* SPICE export by: SEDIT 13.00
* Export time: Sat Aug 06 21:50:04 2016
* Design: dff
* Cell: Cell3
* View: view0
* Export as: top-level cell
* Export mode: hierarchical
* Exclude .model: no
* Exclude .end: no
* Expand paths: yes
* Wrap lines: no
* Root path: D:\MANISHA_PRAC\CMOS\dff
* Exclude global pins: no
* Control property name: SPICE
********* Simulation Settings - General section *********
.lib "C:\Users\Administrator\Documents\Tanner EDA\Tanner Tools
v13.0\Libraries\Models\Generic_025.lib" TT
********* Simulation Settings - Parameters and SPICE Options *********
*-------- Devices: SPICE.ORDER > 0 --------
MNMOS_1 N_7 N_3 Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MNMOS_2 N_5 N_9 Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MNMOS_3 N_6 N_8 Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MNMOS_4 N_7 N_8 N_4 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MNMOS_5 N_5 N_6 N_4 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MNMOS_6 N_3 N_4 Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MNMOS_10 N_13 N_6 N_12 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MNMOS_11 N_15 N_12 Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MNMOS_7 N_16 N_15 Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MNMOS_8 N_13 N_3 Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MNMOS_9 N_16 N_8 N_12 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MPMOS_1 N_5 N_9 N_1 Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MPMOS_2 N_7 N_3 N_2 Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MPMOS_3 N_6 N_8 N_11 Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MPMOS_4 N_7 N_6 N_4 Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MPMOS_5 N_5 N_8 N_4 Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MPMOS_6 N_3 N_4 N_10 Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MPMOS_7 N_13 N_3 N_18 Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MPMOS_8 N_16 N_15 N_17 Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u
AD=2.25p PD=6.8u
MPMOS_9 N_16 N_6 N_12 Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p
PD=6.8u
MPMOS_10 N_13 N_8 N_12 Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u
AD=2.25p PD=6.8u
MPMOS_11 N_15 N_12 N_14 Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u
AD=2.25p PD=6.8u
VVoltageSource_1 N_2 Gnd DC 5
VVoltageSource_2 N_1 Gnd DC 5
VVoltageSource_3 N_11 Gnd DC 5
VVoltageSource_6 N_10 Gnd DC 5
VVoltageSource_7 N_17 Gnd DC 5
VVoltageSource_8 N_18 Gnd DC 5
VVoltageSource_10 N_14 Gnd DC 5
VVoltageSource_4 N_9 Gnd PULSE(0 5 0 1n 1n 145n 200n)
VVoltageSource_5 N_8 Gnd PULSE(0 5 360p 1n 1n 50n 100n)
.PRINT TRAN V(N_15)
.PRINT TRAN V(N_8)
.PRINT TRAN V(N_9)
********* Simulation Settings - Analysis section *********
.tran 1ns 250ns start=0ns
.option prtdel=1ns
********* Simulation Settings - Additional SPICE commands *********
.end
RESULTS OBTAINED:
FOR SETUPTIME = 0.35ns
FOR SETUPTIME = 0.36ns
CONCLUSION:
It can be noted from graph 1 that for ts=0.35ns the high transition in the input(D) is not
reflected at the output (Qout) and the output continues to stay at 0 for the entire high
period of the clock and becomes one in the negative clock transition. This is a faulty
result;
Now if ts=0.36 ns then as seen from graph 2 the out begins to respond to the change in
input as setup time has been overcame. The output also makes a high transition as soon as
the clock reaches after the specified delay time.
Lab 6
OBJECTIVE: Draw the layout of 6 Transistor SRAM cell. Extract the netlist and
simulate for read and write operations.
LAYOUT:
READ:
WRITE:
SPICE NETLIST:
READ:
CIRCUIT example.MSK
* IC Technology: CMOS 0.25μm - 6 Metal
*
VDD 1 0 DC 2.50
V2_vddHV 2 0 DC 1.80V
V4_vddHV 4 0 DC 1.80V
V~bl 6 0 PULSE(0.00 2.50 0.22N 0.00N 0.00N 0.22N 0.43N)
Vbl 8 0 PULSE(2.50 0.00 0.21N 0.01N 0.00N 0.22N 0.44N)
Vclock17 9 0 PULSE(0.00 2.50 0.91N 0.00N 0.00N 0.91N 1.82N)
*
* List of nodes
* "N3" corresponds to n°3
* "out" corresponds to n°5
* "~bl" corresponds to n°6
* "bl" corresponds to n°8
* "clock17" corresponds to n°9
*
* MOS devices
MN1 0 5 3 0 N1 W= 0.50U L= 0.75U
MN2 3 9 6 0 N1 W= 0.50U L= 0.25U
MN3 5 3 0 0 N1 W= 0.50U L= 0.75U
MN4 8 9 5 0 N1 W= 0.50U L= 0.25U
MP1 4 5 3 2 P1 W= 1.63U L= 0.75U
MP2 5 3 4 2 P1 W= 1.63U L= 0.75U
*
C2 2 0 4.688fF
C3 3 0 2.516fF
C4 4 0 0.913fF
C5 5 0 2.589fF
C6 6 0 0.384fF
C8 8 0 0.495fF
C9 9 0 0.165fF
**
* n-MOS BSIM4 :
* Standard
.MODEL N1 NMOS LEVEL=14 VTO=0.45 U0=0.062 TOX= 5.0E-9 LINT=-0.010U
+K1 =0.170 K2=0.100 DVT0=2.300
+DVT1=0.540 LPE0=23.000e-9 ETA0=0.080
+NFACTOR= 3.0 U0=0.062 UA=7.000e-15
+WINT=0.020U LPE0=23.000e-9
+KT1=-0.060 UTE=-1.800 VOFF=0.050
+XJ=0.150U NDEP=170.000e15 PCLM=0.290
+CGSO=100.0p CGDO=100.0p
+CGBO= 60.0p CJSW=240.0p
*
* p-MOS BSIM4:
* Standard
.MODEL P1 PMOS LEVEL=14 VTO=-0.45 U0=0.010 TOX= 5.0E-9 LINT=-0.040U
+K1 =0.290 K2=0.100 DVT0=2.300
+DVT1=0.540 LPE0=23.000e-9 ETA0=0.080
+NFACTOR= 2.2 U0=0.010 UA=1.000e-15
+WINT=0.020U LPE0=23.000e-9
+KT1=-0.060 UTE=-1.800 VOFF=0.050
+XJ=0.150U NDEP=170.000e15 PCLM=0.300
+CGSO=100.0p CGDO=100.0p
+CGBO= 60.0p CJSW=240.0p
*
* Transient analysis
*
.TEMP 27.0
.TRAN 0.80PS 2.00N
.PROBE
.print v(5)
.print v(8)
.print v(6)
.print v(9)
.END
WRITE:
CIRCUIT D:\MANISHA_PRAC\CMOS\sram_read\layout_read.MSK
*
* IC Technology: CMOS 0.25μm - 6 Metal
*
VDD 1 0 DC 2.50
V2_vddHV 2 0 DC 1.80V
V4_vddHV 4 0 DC 1.80V
VINTPUT_BITT 5 0 PULSE(0.00 2.50 0.48N 0.00N 0.00N 0.48N 0.95N)
VWL 9 0 PULSE(0.00 2.50 0.95N 0.05N 0.05N 3.80N)
*
* List of nodes
* "N3" corresponds to n°3
* "INTPUT_BITT" corresponds to n°5
* "~BIT_BAR" corresponds to n°6
* "BIT." corresponds to n°8
* "WL" corresponds to n°9
*
* MOS devices
MN1 0 5 3 0 N1 W= 0.50U L= 0.75U
MN2 3 9 6 0 N1 W= 0.50U L= 0.25U
MN3 5 3 0 0 N1 W= 0.50U L= 0.75U
MN4 8 9 5 0 N1 W= 0.50U L= 0.25U
MP1 4 5 3 2 P1 W= 1.63U L= 0.75U
MP2 5 3 4 2 P1 W= 1.63U L= 0.75U
*
C2 2 0 4.688fF
C3 3 0 2.516fF
C4 4 0 0.913fF
C5 5 0 2.589fF
C6 6 0 0.384fF
C8 8 0 0.495fF
C9 9 0 0.165fF
**
* n-MOS BSIM4 :
* Standard
.MODEL N1 NMOS LEVEL=14 VTO=0.45 U0=0.062 TOX= 5.0E-9 LINT=-0.010U
+K1 =0.170 K2=0.100 DVT0=2.300
+DVT1=0.540 LPE0=23.000e-9 ETA0=0.080
+NFACTOR= 3.0 U0=0.062 UA=7.000e-15
+WINT=0.020U LPE0=23.000e-9
+KT1=-0.060 UTE=-1.800 VOFF=0.050
+XJ=0.150U NDEP=170.000e15 PCLM=0.290
+CGSO=100.0p CGDO=100.0p
+CGBO= 60.0p CJSW=240.0p
*
* p-MOS BSIM4:
* Standard
.MODEL P1 PMOS LEVEL=14 VTO=-0.45 U0=0.010 TOX= 5.0E-9 LINT=-0.040U
+K1 =0.290 K2=0.100 DVT0=2.300
+DVT1=0.540 LPE0=23.000e-9 ETA0=0.080
+NFACTOR= 2.2 U0=0.010 UA=1.000e-15
+WINT=0.020U LPE0=23.000e-9
+KT1=-0.060 UTE=-1.800 VOFF=0.050
+XJ=0.150U NDEP=170.000e15 PCLM=0.300
+CGSO=100.0p CGDO=100.0p
+CGBO= 60.0p CJSW=240.0p
*
* Transient analysis
*
.TEMP 27.0
.TRAN 0.80PS 10.00N
.PROBE
.PRINT V(6)
.PRINT V(8)
.PRINT V(5)
.PRINT V(9)
.END
RESULTS OBTAINED:
READ:
WRITE:
CONCLUSION:
The layout of 6 Transistor SRAM cell was drawn. Advanced BSIM net list was extracted
and was simulated for both read and write operations.
