RTD2010
REALTEK
FLAT PANEL DISPLAY CONTROLLER
RTD2010
Product Brief
This document contains introductory information pertaining to the Realtek RTD2010 Flat Panel Display Controller. Because
proprietary and confidential information is contained in the complete specifications, this brief is offered to those interested in the
chip. For a more detailed description of the device, please contact your Realtek sales representative.
1. Features.................................................................................................................................................................................... 2
2. General Description ................................................................................................................................................................ 3
3. Block Diagram......................................................................................................................................................................... 4
4. Pin Assignments....................................................................................................................................................................... 5
5. Pin Descriptions....................................................................................................................................................................... 6
5.1 ADC ................................................................................................................................................................................... 6
5.2 PLL..................................................................................................................................................................................... 6
5.3 Control Interface ................................................................................................................................................................ 7
5.4 Digital Input ....................................................................................................................................................................... 8
5.5 Display Port........................................................................................................................................................................ 8
5.6 Miscellaneous Interface...................................................................................................................................................... 9
5.7 DDC Channel ..................................................................................................................................................................... 9
5.8 Power & Ground ................................................................................................................................................................ 9
5.9 MCU Interface.................................................................................................................................................................. 10
2002/11/12 1 Rev1.20
RTD2010
1. Features
General Color Processor
! Integrated Spread-Spectrum DCLK PLL ! Digital brightness and contrast adjustments
! Integrated 8-bit triple-channel 110MHz ADC/PLL ! Gamma correction
! Integrated programmable timing controller ! Dithering logic for 18-bit panel color depth
! Integrated microcontroller compatible with the enhancement
standard 8032
! 24 General-purpose input/outputs (GPIOs) Output Interface
! Embedded fully functional multi-language OSD ! Fully programmable, built-in display timing
support generator
! Embedded DDC supports DDC1, DDC2B, and ! 1 and 2-pixel/clock panel support, up to 110MHz
DDC/CI ! Pin swap, odd/even swap and red/blue group swap
! Supports ISP functionality on DDC channel ! Programmable TCON function support
! 3 Embedded programmable PWM ! Reduced EMI and Power saving features
! Zoom scaling up and down
! Embedded Pattern Generator Host Interface
! No external memory required ! Supports 3/4 pins MCU serial bus interface
! Requires only one crystal to generate all timing ! Support parallel bus interface while using internal
MCU
Analog RGB Input Interface
! Supports up to 110MHz (XGA @ 75Hz) Embedded OSD
! Supports Sync On Green (SOG) and de-composite ! 12*18 dot font per character
sync modes ! Embedded 256 characters and symbols including
! On-chip high-performance PLLs 16 multi-color symbols
! User font RAM, which allows programming of 128
Digital Input Interface special symbols
! Supports 24-bit pixel digital input up to 160MHz ! 7 background colors and 8 character colors
! Supports 12-bit DVO input ! Programmable width and height control
! Supports 16/24-bit YUV422/444 video format ! 4 background windows
input ! Selectable shadow color for windows and
! Supports 8-bit video format input characters
! Built-in YUV to RGB color space converter & ! Intensity, blinking effects
de-interlace ! Fade-in/out effect
! Capture window auto position & auto phase ! Frame shadowing and independent row shadowing
tracking capability ! Frame bordering and independent row bordering
! 4 channel 8-bits PWM output, and selectable PWM
Auto Detection /Auto Calibration clock frequency
! Input format detection ! Row-to-Row spacing to maintain constant display
! Compatibility with standard VESA mode and height
support for user-defined mode ! Window alpha-blending effect
! Smart engine for Phase and Image position
calibration Power & Technology
! 2.5V/3.3V power supply
Scaling ! 0.25µm CMOS process; 208-pin PQFP package
! Fully programmable zoom ratios
! Independent horizontal/vertical scaling
! Advanced zoom algorithm provides high image
quality
! Sharpness/Smooth filter enhancement
2002/11/12 2 Rev1.20
RTD2010
2. General Description
The Realtek RTD2010 is a highly-integrated single chip IC controller solution for producing real time, top quality digital video
and computer graphic images on LCD monitor/flat panel displays, such as XGA LCD monitors. LCD monitors and flat panel
displays provide a sharp, flicker free display while saving space and energy for desktop PC applications. The RTD2010 provides
an ideal interface between industry standard digital graphics controllers and a wide variety of LCD panel devices. Flat panel
devices using the RTD2010 can support all incoming VESA modes and interface to any TFT LCD device, up to XGA (1024x768)
resolution.
For increased flexibility, the RTD2010 supports both analog and digital interface inputs. The embedded 8-bit triple-channel
110MHz high-quality Analog to Digital Converter (ADC) and PLL support up to a 1024x768 75Hz RGB analog input signal. The
digital interface can support Transmission Minimized Differential Signaling (TMDS) receiver or Video-Decoder or DVO digital
output signals up to 160MHz.
The RTD2010 features an embedded On-Screen Display (OSD) engine. This OSD enables either character based or bit map based
menu display. Through this menu, display parameters, such as brightness and contrast, can be controlled, and information on
resolution and frequency, can be displayed. The embedded display pattern generator is a function for panel testing.
Processing 24-bit RGB or 16-bit YUV input data streams, and conversion of input VGA signals to high resolution output, the RTD2010
implements a sophisticated scaling algorithm. This feature allows the RTD2010 to perform horizontal and vertical interpolation or
replication and up & down image scaling, based on programmable parameters, to create images of the highest quality.
The built-in advanced filtering engine enables independent vertical and horizontal zoom/shrink, and, through enhancement of
individual pixels, enhances image sharpness, and provides superb visual quality. This allows appropriate sized display of crisp,
sharp text and smooth, clear graphics, taking full advantage of LCD flat panel technology.
Also featured are enhanced color processing functions, including gamma correction and dithering logic. Brightness, contrast and
gamma correction can be programmed through the internal gamma correction lookup tables. Full control of output panel data is
obtained by color mapping input RGB data. The 8-bit/color pixel path offers up to 16.7 million color support for 24-bit TFT LCD
panels. 18-bit LCD panels are also supported through spatial and temporal dither algorithms.
Increased integration in the RTD2010 includes components such as an 8032 compatible micro controller, and DDC RAM to
provide monitor information the PC through the DDC1/DDC2B protocol. Internal System Programming (ISP) is accomplished
through the DDC serial bus, supporting enhanced DDC-communication from PC to monitor, such as DDC/CI is also supported.
Finally, the Timing-Controller (TCON) generates the control signals for LCD-panel rather than LCD-monitor, and the embedded
spread-spectrum technology reduces EMI effects.
All these features make the RTD2010 is the optimum solution for superior-quality image display.
2002/11/12 3 Rev1.20
RTD2010
3. Block Diagram
Program ROM
(64KB~128KB)
Addr
Data
Ctrl
VS
HS
TCON LCD Panel
R/G/B
5C Row/Column
RTD2010 48D Driver
5C Flat Panel Display
NTSC Video 16D
PAL Decoder 8D
5C TTL Signal
48D LCD Panel
IIC
Rx0~2
RxC 48D TMDS/LVDS
TMDS IIC 5C
5C LCD Panel
Receiver IIC EEPROM 24.576MHz
Key-In
Application System Block Diagram
Analog
RGB Panel
Triple-ADC
Digital Color Timing Driver
FIFO
RGB/YUV Conversion Control
HS & VS Sync Control Built-In
Build-In
Scaling Up OSD
Processor Register
Onchip Color OSD Panel
PLL
MCU Processing MUX
24.576MHz
Flat Panel Display -- RTD2010
Chip Functional Block Diagram
2002/11/12 4 Rev1.20
RTD2010
4. Pin Assignments
P2.4/TCON15
P2.3/TCON14
P2.2/TCON13
P2.1/TCON12
P2.0/TCON11
P1.7/TCON10
P1.6/TCON9
P1.5/TCON8
P1.4/TCON7
P2.7/PWM2
P2.6/PWM1
INT0#/P3.2
DDCSDA
DDCSCL
BGRN0
BGRN1
BGRN2
BGRN3
BGRN4
BGRN5
BGRN6
BGRN7
BRED0
BRED1
BRED2
BRED3
BRED4
BRED5
BRED6
BRED7
GNDIK
BBLU0
BBLU1
BBLU2
BBLU3
BBLU4
BBLU5
BBLU6
BBLU7
GNDIK
PWM0
GNDO
VODD
VCCK
VCCK
BCLK
BEN
BHS
P3.3
AHS
BVS
AVS
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
P2.5/TCON16 1 156 VCC3IO
DBBLU0 2 155 EXT#
DBBLU1 3 154 ADC_VDD
VCC3IO 4 153 ADC_VDD
DBBLU2 5 152 R
GNDO 6 151 ADC_GND
DBBLU3 7 150 ADC_GND
DBBLU4 8 149 G
DBBLU5 9 148 ADC_VDD
DBBLU6 10 147 ADC_VDD
DBBLU7 11 146 B
GNDIK 12 145 ADC_GND
DBGRN0 13 144 ADC_GND
DBGRN1 14 143 ADC_TEST
DBGRN2 15 142 ADC_VDD
VCCK 16 141 ADC_VDD
DBGRN3 17 140 ADC_REFIO
VCC3IO 18 139 ADC_GND
DBGRN4 19 138 ADC_GND
GNDO 20 137 WE#/P0.4
DBGRN5 21 136 ROM_ADDR_BANK
DBGRN6 22 135 GNDIK
DBGRN7 23 134 ROM_ADDR15
DBRED0 24 133 VCCK
DBRED1 25 132 ROM_ADDR14
DBRED2 26 131 ROM_ADDR13
GNDIK 27 130 ROM_ADDR12
DBRED3 28 129 GNDIK
VCCK 29 128 ROM_ADDR11
DBRED4 30 127 VCCK
DBRED5
VCC3IO
DBRED6
GNDO
31
32
33
34
Realtek 126
125
124
123
ROM_ADDR10
GNDO
ROM_ADDR9
ROM_ADDR8
DBRED7 35 122 VCC3IO
REFCLK/OCLK
DABLU0
DABLU1
DABLU2
36
37
38
39
RTD2020
RTD2010 121
120
119
118
ROM_ADDR7
ROM_ADDR6
ROM_ADDR5
ROM_ADDR4
DABLU3 40 117 ROM_ADDR3
VCCK 41 116 ROM_ADDR2
DABLU4 42 115 ROM_ADDR1
DABLU5 43 114 ROM_ADDR0
GNDIK 44 113 ROM_DATA0
DABLU6 45 112 ROM_DATA1
VCC3IO 46 111 ROM_DATA2
DABLU7 47 110 ROM_DATA3
GNDO 48 109 GNDO
DAGRN0 49 108 ROM_DATA4
DAGRN1 50 107 ROM_DATA5
DAGRN2 51 106 VCC3IO
DAGRN3 52 105 ROM_DATA6
100
101
102
103
104
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
INT1#/P3.1/IRQ#
DEN/TCON4
DHS/TCON6
GNDIK
GNDIK
PLL_TEST1
PLL_TEST2
VCC3IO
DVS/TCON5
VCC3IO
P1.0/TCON0
P1.1/TCON1
P1.2/TCON2
P1.3/TCON3
GNDO
GNDO
ROM_DATA7
XI
RESET#
DAGRN4
DAGRN5
DAGRN6
DAGRN7
XO
P3.6/SDI
PLL_GND
PLL_GND
PLL_GND
PLL_GND
PLL_GND
PLL_GND
T1#/P3.5/SCLK
P3.7/SDO
VCCK
VCCK
T0#/P3.4/SCSB
DARED0
DARED1
DARED2
DARED3
DARED4
DARED5
DARED6
DARED7
PLL_VDD
PLL_VDD
PLL_VDD
PLL_VDD
PLL_VDD
PSEN#
DCLK/ECLK
P3.0/PWDN#
RTD2010 Pin-Out Diagram
2002/11/12 5 Rev1.20
RTD2010
5. Pin Descriptions
In order to reduce pin count, and therefore size and cost, some pins have multiple functions. In those cases, the functions are
separated with a “/” symbol. Refer to the Pin Assignment diagram for a graphical representation.
A = Analog P = Power
I = Input G = Ground
O = Output
5.1 ADC
Name Type Pin No Description
ADC_REFIO AI 140 ADC Reference Pad
ADC_TEST AIO 143 ADC Test Pin / SOG input
B AI 146 Analog Input from BLUE Channel
G AI 149 Analog Input from GREEN Channel
R AI 152 Analog Input from RED Channel
ADC_VDD AP 141,142 ADC Analog Power
147,148
153,154
ADC_GND AG 138,139 ADC Analog Ground
144,145
150,151
Total: 17 Pins
5.2 PLL
Name Type Pin No Description
XI AI 92 Reference Clock Input
XO AO 93 Reference Clock Output
PLL_TEST1 AIO 96 Test Pin 1
PLL_TEST2 AIO 97 Test Pin 2
PLL_VDD AP 88,94 PLL Analog Power
95,100
101
PLL_GND AG 89,90 PLL Analog Ground
91,98
99,102
Total: 15 Pins
2002/11/12 6 Rev1.20
RTD2010
5.3 Control Interface
Name Type Pin No Description
(EXT# =0): I 81 Serial Control I/F Chip Select
SCSB I/O GPIO_P3.4 / T0#
(EXT# =1):
GPIO_P3.4
(EXT# =0): I 82 Serial Control I/F Clock
SCLK I/O GPIO_P3.5 / T1#
(EXT# =1):
GPIO_P3.5
(EXT# =0): SDI I 83 Serial Control I/F Data in
(EXT# =1): I/O GPIO_P3.6
GPIO_P3.6
(EXT# =0): SDO O 84 Serial Control I/F Data out
(EXT# =1): I/O GPIO_P3.7
GPIO_P3.7
(EXT# =0): O 85 Controller’s IRQ# Output;
IRQ# I/O GPIO_P3.1 / INT#1
(EXT# =1):
GPIO_P3.1
(EXT# =0): I 86 PowerDown# for Controller
PWDN# I/O GPIO_P3.0
(EXT# =1):
GPIO_P3.0
RESET# I 87 (EXT#=0): RESET# for Controller;
(EXT#=1): RESET# for MCU
Total: 7 Pins
2002/11/12 7 Rev1.20
RTD2010
5.4 Digital Input
Name Type Pin No Description
AHS I 158 VGA-port Horizontal Sync
AVS I 160 VGA-port Vertical Sync
VODD I 167 Video ODD Signal
BHS I 168 VGB-port Horizontal Sync
BVS I 169 VGB-port Vertical Sync
BENA I 170 VGB-port Input Data Enable
BCLK I 171 VGB-port Input Clock
BRED/YIN [7:0] / I 172,173 VGB-port Input Data (Red/Y)
DVODATA 174,175
[11:4] / 176,177
VIDEO8 178,179
BGRN [7:0] / I 181,182 VGB-port Input Data (Green)
DVODATA [3:0] 184,185
186,187
188,189
BBLU/UVIN I 190,191 VGB-port Input Data (Blue/UV)
[7:0] 192,193
194,195
196,197
Total: 31 Pins
5.5 Display Port
Name Type Pin No Description
DCLK O 73 Display clock; / TCON_ECLK
DHS O 71 Display Horizontal Sync; / TCON_6
DVS O 70 Display Vertical Sync; / TCON_5
DEN O 69 Display Data Enable; / TCON_4
DARED [7:0] O 68, 67, 66 Display A-port RED Data
65, 63, 61
59, 58
DAGRN [7:0] O 57, 55, 54 Display A-port GREEN Data
53, 52, 51
50, 49
DABLU [7:0] O 47, 45, 43 Display A-port BLUE Data
42, 40, 39
38, 37
DBRED [7:0] O 35, 33, 31 Display B-port RED Data
30, 28, 26
25, 24
DBGRN [7:0] O 23, 22, 21 Display B-port GREEN Data
19, 17, 15
14, 13
DBBLU [7:0] O 11, 10, 9, 8 Display B-port BLUE Data
7, 5, 3, 2
Total: 52 Pins
2002/11/12 8 Rev1.20
RTD2010
5.6 Miscellaneous Interface
Name Type Pin No Description
REFCLK IO 36 In/out Test Pin for DCLK; / TCON_OCLK
PWM_0 O 166 PWM_0 Output
Total: 2 Pins
5.7 DDC Channel
Name Type Pin No Description
DDCSDA I 156 DDC Serial Control I/F Data Input
O DDC Serial Control I/F Data Output
DDCSCL I 161 DDC Serial Control I/F Clock
Total: 2 Pins
5.8 Power & Ground
Name Type Pin No Description
3.3V Power P 4, 18 VCC3IO: 9
32, 46
60, 72
106,122
157
3.3V Ground G 6, 20 GNDO: 9
34, 48
56, 74
109,125
159
2.5V Power P 16, 29 VCCK: 9
41, 64
78,127
133,180
198
2.5V Ground G 12, 27 GNDIK: 9
44, 62
80,129
135,183
201
Total: 36 Pins
2002/11/12 9 Rev1.20
RTD2010
5.9 MCU Interface
Name I/O Pin No Description
PSEN# O 103 Program Load Enable
ROM_DATA IO 104,105,107 ROM Data Input
[7:0] 108,110,111
112,113
ROM_ADDR O 134,132,131 ROM Address Output
[15:9] I 130,128,126 DDC_CA latch
124
ROM_ADDR O 123,121,120 ROM Address Output
[8:0] 119,118,117
116,115,114
ROM_ADDR_BA O 136 XDATA/PROG# Bank Select
NK
GPIO_P0.4 I/O 137 GPIO_P0.4 / WR#
EXT# I 155 External MCU, Internal MCU Disable
GPIO_P1.0 I/O 75 GPIO_P1.0 / TCON_0
GPIO_P1.1 I/O 76 GPIO_P1.1 / TCON_1
GPIO_P1.2 I/O 77 GPIO_P1.3 / TCON_2
GPIO_P1.3 I/O 79 GPIO_P1.3 / TCON_3
GPIO_P1.4 I/O 199 GPIO_P1.4 / TCON_7
GPIO_P1.5 I/O 200 GPIO_P1.5 / TCON_8
GPIO_P1.6 I/O 202 GPIO_P1.6 / TCON_9
GPIO_P1.7 I/O 203 GPIO_P1.7 / TCON_10
GPIO_P2.0 I/O 204 GPIO_P2.0 / TCON_11
GPIO_P2.1 I/O 205 GPIO_P2.1 / TCON_12
GPIO_P2.2 I/O 206 GPIO_P2.2 / TCON_13
GPIO_P2.3 I/O 207 GPIO_P2.3 / TCON_14
GPIO_P2.4 I/O 208 GPIO_P2.4 / TCON_15
GPIO_P2.5 I/O 1 GPIO_P2.5 / TCON_16
GPIO_P2.6 I/O 164 GPIO_P2.6 / PWM1
GPIO_P2.7 I/O 165 GPIO_P2.7 / PWM2
(EXT# =0): I Share PowerDown# for Controller
PWDN# I/O GPIO_P3.0
(EXT# =1):
GPIO_P3.0
(EXT# =0): IRQ# O Share Controller’s IRQ# output;
(EXT# =1): I/O GPIO_P3.1 / INT1#
GPIO_P3.1
GPIO_P3.2 I/O 162 GPIO_P3.2 / INT0#
GPIO_P3.3 I/O 163 GPIO_P3.3
(EXT# =0): SCSB I Share Serial control I/F chip select
(EXT# =1): I/O GPIO_P3.4 / T0#
GPIO_P3.4
(EXT# =0): SCLK I Share Serial control I/F clock
(EXT# =1): I/O GPIO_P3.5 / T1#
GPIO_P3.5
(EXT# =0): SDI I Share Serial control I/F data in
(EXT# =1): I/O GPIO_P3.6
GPIO_P3.6
(EXT# =0): SDO O Share Serial control I/F data out
(EXT# =1): I/O GPIO_P3.7
GPIO_P3.7
Total: 46 pins (6 share)
2002/11/12 10 Rev1.20
RTD2010
Realtek Semiconductor Corp.
Headquarters
1F, No. 2, Industry East Road IX, Science-based
Industrial Park, Hsinchu, 300, Taiwan, R.O.C.
Tel : 886-3-5780211 Fax : 886-3-5776047
WWW: www.realtek.com.tw
2002/11/12 11 Rev1.20
This datasheet has been downloaded from:
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