Lead-

Free
Package ®

Options ispLSI 2032/A

Available! In-System Programmable High Density PLD

Features Functional Block Diagram

• ENHANCEMENTS
— ispLSI 2032A is Fully Form and Function Compatible
to the ispLSI 2032, with Identical Timing
Specifcations and Packaging

S
— ispLSI 2032A is Built on an Advanced 0.35 Micron

See Ordering Information section for product status.

E2CMOS® Technology

N
• HIGH DENSITY PROGRAMMABLE LOGIC Global Routing Pool

IG
A0 A7
(GRP)

Output Routing Pool (ORP)

Output Routing Pool (ORP)

— 1000 PLD Gates
— 32 I/O Pins, Two Dedicated Inputs

ES

Select devices have been discontinued.

A1 A6
— 32 Registers D Q

Input Bus

Input Bus
— High Speed Global Interconnect Logic
D Q

— Wide Input Gating for Fast Counters, State A2 GLB Array D Q A5

D
Machines, Address Decoders, etc. D Q

— Small Logic Block Size for Random Logic

A3 A4

EW
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— fmax = 180 MHz Maximum Operating Frequency
— tpd = 5.0 ns Propagation Delay
— TTL Compatible Inputs and Outputs
—
—
Electrically Erasable and Reprogrammable
Non-Volatile
N 0139Bisp/2000
R
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
FO

Description
• IN-SYSTEM PROGRAMMABLE
— In-System Programmable (ISP™) 5V Only The ispLSI 2032 and 2032A are High Density Program-
— Increased Manufacturing Yields, Reduced Time-to- mable Logic Devices. The devices contain 32 Registers,
2E

Market and Improved Product Quality 32 Universal I/O pins, two Dedicated Input Pins, three
— Reprogram Soldered Devices for Faster Prototyping Dedicated Clock Input Pins, one dedicated Global OE
input pin and a Global Routing Pool (GRP). The GRP
03

• OFFERS THE EASE OF USE AND FAST SYSTEM

SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY provides complete interconnectivity between all of these
OF FIELD PROGRAMMABLE GATE ARRAYS elements. The ispLSI 2032 and 2032A feature 5V in-
I2

— Complete Programmable Device Can Combine Glue system programmability and in-system diagnostic
Logic and Structured Designs capabilities. The ispLSI 2032 and 2032A offer non-
LS

— Enhanced Pin Locking Capability volatile reprogrammability of the logic, as well as the
— Three Dedicated Clock Input Pins interconnect to provide truly reconfigurable systems.
— Synchronous and Asynchronous Clocks
The basic unit of logic on these devices is the Generic
p

— Programmable Output Slew Rate Control to

Minimize Switching Noise Logic Block (GLB). The GLBs are labeled A0, A1 .. A7
is

— Flexible Pin Placement (Figure 1). There are a total of eight GLBs in the ispLSI
— Optimized Global Routing Pool Provides Global 2032 and 2032A devices. Each GLB is made up of four
SE

Interconnectivity macrocells. Each GLB has 18 inputs, a programmable

— Lead-Free Package Options AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
U

Inputs to the GLB come from the GRP and dedicated

inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.

Copyright © 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. August 2006
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; [Link]

2032_11 1
 Specifications ispLSI 2032/A

Functional Block Diagram

Figure 1. ispLSI 2032/A Functional Block Diagram

GOE 0

S
N
See Ordering Information section for product status.
IG
ES
I/O 0 I/O 31

Select devices have been discontinued.

I/O 1 A0 A7 I/O 30
I/O 2 I/O 29
I/O 28
Output Routing Pool (ORP)

Output Routing Pool (ORP)

I/O 3

D
I/O 4 I/O 27
I/O 5 I/O 26
I/O 6 A1 Global Routing Pool A6 I/O 25
Input Bus

Input Bus
(GRP)

EW
I/O 7 I/O 24
I/O 8 I/O 23
I/O 9 I/O 22
I/O 10 A2 A5 I/O 21
I/O 11 I/O 20

I/O 12
I/O 13
N I/O 19
I/O 18
R
I/O 14 I/O 17
A3 A4
I/O 15 I/O 16
FO

SDI/IN 0
SDO/IN 1

CLK 0
CLK 1
CLK 2
MODE
2E

ispEN

Y0
03

Notes: Y1*/RESET
*Y1 and RESET are multiplexed on the same pin SCLK/Y2
0139B(1)isp/2000
I2

The devices also have 32 I/O cells, each of which is All of these signals are made available to the inputs of the
S

directly connected to an I/O pin. Each I/O cell can be GLBs. Delays through the GRP have been equalized to
pL

individually programmed to be a combinatorial input, minimize timing skew.

output or bi-directional I/O pin with 3-state control. The
signal levels are TTL compatible voltages and the output Clocks in the ispLSI 2032 and 2032A devices are se-
is

drivers can source 4 mA or sink 8 mA. Each output can lected using the dedicated clock pins. Three dedicated
be programmed independently for fast or slow output clock pins (Y0, Y1, Y2) or an asynchronous clock can be
SE

slew rate to minimize overall output switching noise. selected on a GLB basis. The asynchronous or Product
Term clock can be generated in any GLB for its own clock.
Eight GLBs, 32 I/O cells, two dedicated inputs and two
U

ORPs are connected together to make a Megablock

(Figure 1). The outputs of the eight GLBs are connected
to a set of 32 universal I/O cells by the ORP. Each ispLSI
2032 and 2032A device contains one Megablock.

The GRP has as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.

2
 Specifications ispLSI 2032/A

Absolute Maximum Ratings 1

Supply Voltage Vcc ...................................-0.5 to +7.0V

Input Voltage Applied ........................ -2.5 to VCC +1.0V

Off-State Output Voltage Applied ..... -2.5 to VCC +1.0V

Storage Temperature ................................ -65 to 150°C

S
Case Temp. with Power Applied .............. -55 to 125°C

N
See Ordering Information section for product status.
IG
Max. Junction Temp. (TJ) with Power Applied ... 150°C

1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional

ES
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification

Select devices have been discontinued.

is not implied (while programming, follow the programming specifications).

D
DC Recommended Operating Condition

EW
SYMBOL PARAMETER MIN. MAX. UNITS
Commercial TA = 0°C to + 70°C 4.75 5.25 V
VCC Supply Voltage
Industrial
N
TA = -40°C to + 85°C 4.5 5.5 V
R
VIL Input Low Voltage 0 0.8 V
VIH Input High Voltage 2.0 Vcc+1 V
FO

Table 2 - 0005/2032
2E

Capacitance (TA=25°C, f=1.0 MHz)

03

SYMBOL PARAMETER TYPICAL UNITS TEST CONDITIONS

C1 Dedicated Input Capacitance 6 pf VCC = 5.0V, VIN = 2.0V
I2

C2 I/O Capacitance 7 pf VCC = 5.0V, VI/O = 2.0V

C3 Clock Capacitance 10 pf VCC = 5.0V, VY = 2.0V
S

Table 2-0006/2032
pL

Data Retention Specifications

is

PARAMETER MINIMUM MAXIMUM UNITS

SE

Data Retention 20 – Years

Erase/Reprogram Cycles 10000 – Cycles
U

Table 2-0008A-isp

3
 Specifications ispLSI 2032/A

Switching Test Conditions

Input Pulse Levels GND to 3.0V Figure 2. Test Load
Input Rise and Fall Time -135, -150, -180 ≤ 1.5 ns + 5V
10% to 90% -80, -110 ≤ 3 ns
R1
Input Timing Reference Levels 1.5V
Output Timing Reference Levels 1.5V Device Test
Output Point

S
Output Load See Figure 2
Table 2-0003/2032 CL*

N
3-state levels are measured 0.5V from R2

See Ordering Information section for product status.

steady-state active level.

IG
Output Load Conditions (see Figure 2)
*CL includes Test Fixture and Probe Capacitance.

ES

Select devices have been discontinued.

TEST CONDITION R1 R2 CL 0213A

A 470Ω 390Ω 35pF

D
Active High ∞ 390Ω 35pF
B
Active Low 470Ω 390Ω 35pF

EW
Active High to Z ∞ 390Ω 5pF
at VOH -0.5V
C
Active Low to Z
470Ω 390Ω 5pF

N
at VOL +0.5V
Table 2 - 0004A
R
FO

DC Electrical Characteristics
Over Recommended Operating Conditions
3
SYMBOL PARAMETER CONDITION MIN. TYP. MAX. UNITS
2E

VOL Output Low Voltage IOL= 8 mA – – 0.4 V

VOH Output High Voltage IOH = -4 mA 2.4 – – V
03

IIL Input or I/O Low Leakage Current 0V ≤ VIN ≤ VIL (Max.) – – -10 μA
IIH
I2

Input or I/O High Leakage Current 3.5V ≤ VIN ≤ VCC – – 10 μA

IIL-isp ispEN Input Low Leakage Current 0V ≤ VIN ≤ VIL – – -150 μA
S

IIL-PU I/O Active Pull-Up Current 0V ≤ VIN ≤ VIL – – -150 μA

IOS1 Output Short Circuit Current VCC = 5V, VOUT = 0.5V – – -200 mA
pL

-180, -150 – 60 – mA
ICC2, 4 Operating Power Supply Current VIL = 0.0V, VIH = 3.0V Comm.
Others – 40 – mA
is

fTOGGLE = 1 MHz
Industrial – 40 – mA
Table 2-0007/2032
SE

1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test problems
by tester ground degradation. Characterized but not 100% tested.
2. Measured using two 16-bit counters.
U

3. Typical values are at VCC = 5V and TA= 25°C.

4. Maximum I CC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption
section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to
estimate maximum I CC .

4
 Specifications ispLSI 2032/A

External Timing Parameters

Over Recommended Operating Conditions
4 -180 -150 -135
TEST 2 1
PARAMETER # DESCRIPTION UNITS
COND. MIN. MAX. MIN. MAX. MIN. MAX.
tpd1 A 1 Data Prop. Delay, 4PT Bypass, ORP Bypass – 5.0 – 5.5 – 7.5 ns
tpd2 A 2 Data Prop. Delay – 7.5 – 8.0 – 10.0 ns

S
fmax A 3 Clk Frequency with Internal Feedback 3 180 – 154 – 137 – MHz

N
fmax (Ext.) – 4 Clk Frequency with Ext. Feedback ( tsu21+ tco1) 125 – 111 – 100 – MHz

See Ordering Information section for product status.

fmax (Tog.)

IG
– 5 Clk Frequency, Max. Toggle 200 – 167 – 167 – MHz
tsu1 – 6 GLB Reg Setup Time before Clk, 4 PT Bypass 3.0 – 3.0 – 4.0 – ns

ES
tco1 A 7 GLB Reg. Clk to Output Delay, ORP Bypass – 4.0 – 4.5 – 4.5 ns

Select devices have been discontinued.

th1 – 8 GLB Reg. Hold Time after Clk, 4 PT Bypass 0.0 – 0.0 – 0.0 – ns
tsu2 – 9 GLB Reg. Setup Time before Clk 4.0 – 4.5 – 5.5 – ns

D
tco2 – 10 GLB Reg. Clk to Output Delay – 4.5 – 5.0 – 5.5 ns

EW
th2 – 11 GLB Reg. Hold Time after Clk 0.0 – 0.0 – 0.0 – ns
tr1 A 12 Ext. Reset Pin to Output Delay – 7.0 – 8.0 – 10.0 ns
trw1 – 13 Ext. Reset Pulse Duration 4.0 – 4.5 – 5.0 – ns
tptoeen
tptoedis
B
C
14 Input to Output Enable
15 Input to Output Disable N –
–
10.0
10.0
–
–
11.0
11.0
–
–
12.0
12.0
ns
ns
R
tgoeen B 16 Global OE Output Enable – 5.0 – 5.0 – 6.0 ns
FO

tgoedis C 17 Global OE Output Disable – 5.0 – 5.0 – 6.0 ns

twh – 18 Ext. Synchronous Clk Pulse Duration, High 2.5 – 3.0 – 3.0 – ns
twl – 19 Ext. Synchronous Clk Pulse Duration, Low 2.5 – 3.0 – 3.0 – ns
2E

Table 2-0030B-180/2032
1. Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
03

3. Standard 16-bit counter using GRP feedback.

4. Reference Switching Test Conditions section.
S I2
pL
is
SE
U

5
 Specifications ispLSI 2032/A

External Timing Parameters

Over Recommended Operating Conditions
4 -110 -80
TEST 2 1
PARAMETER # DESCRIPTION UNITS
COND. MIN. MAX. MIN. MAX.
tpd1 A 1 Data Propagation Delay, 4PT Bypass, ORP Bypass – 10.0 – 15.0 ns
tpd2 A 2 Data Propagation Delay – 13.0 – 18.5 ns

S
fmax A 3 Clock Frequency with Internal Feedback 3 111 – 84.0 – MHz
1
Clock Frequency with External Feedback ( )

N
fmax (Ext.) – 4 77.0 – 57.0 – MHz

See Ordering Information section for product status.

tsu2 + tco1

fmax (Tog.) – 5 Clock Frequency, Max. Toggle 125 – 83.0 – MHz

IG
tsu1 – 6 GLB Reg. Setup Time before Clock, 4 PT Bypass 5.5 – 7.5 – ns

ES
tco1 A 7 GLB Reg. Clock to Output Delay, ORP Bypass – 5.5 – 8.0 ns

Select devices have been discontinued.

th1 – 8 GLB Reg. Hold Time after Clock, 4 PT Bypass 0.0 – 0.0 – ns
tsu2 – 9 GLB Reg. Setup Time before Clock 7.5 – 9.5 – ns

D
tco2 – 10 GLB Reg. Clock to Output Delay – 6.5 – 9.5 ns

EW
th2 – 11 GLB Reg. Hold Time after Clock 0.0 – 0.0 – ns
tr1 A 12 Ext. Reset Pin to Output Delay – 13.5 – 19.5 ns
trw1 – 13 Ext. Reset Pulse Duration 6.5 – 10.0 – ns
tptoeen
tptoedis
B
C
14 Input to Output Enable
15 Input to Output Disable N –
–
14.5
14.5
–
–
24.0
24.0
ns
ns
R
tgoeen B 16 Global OE Output Enable – 7.0 – 12.0 ns
FO

tgoedis C 17 Global OE Output Disable – 7.0 – 12.0 ns

twh – 18 External Synchronous Clock Pulse Duration, High 4.0 – 6.0 – ns
twl – 19 External Synchronous Clock Pulse Duration, Low 4.0 – 6.0 – ns
2E

Table 2-0030B-110/2032
1. Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
03

3. Standard 16-bit counter using GRP feedback.

4. Reference Switching Test Conditions section.
S I2
pL
is
SE
U

6
 Specifications ispLSI 2032/A

Internal Timing Parameters1

Over Recommended Operating Conditions

2
-180 -150 -135
PARAMETER # DESCRIPTION UNITS
MIN. MAX. MIN. MAX. MIN. MAX.
Inputs
tio 20 Input Buffer Delay – 0.6 – 0.6 – 1.1 ns

S
tdin 21 Dedicated Input Delay – 1.1 – 1.3 – 2.4 ns

N
GRP

See Ordering Information section for product status.

tgrp 22 GRP Delay – 0.7 – 0.7 – 1.3 ns

IG
GLB

ES
t4ptbpc 23 4 Product Term Bypass Path Delay (Combinatorial) – 2.3 – 2.6 – 3.6 ns

Select devices have been discontinued.

t4ptbpr 24 4 Product Term Bypass Path Delay (Registered) – 3.1 – 3.1 – 3.6 ns
t1ptxor 25 1 Product Term/XOR Path Delay – 3.6 – 4.3 – 5.0 ns

D
t20ptxor 26 20 Product Term/XOR Path Delay – 4.1 – 4.6 – 5.1 ns

EW
txoradj 27 XOR Adjacent Path Delay 3
– 4.8 – 5.0 – 5.6 ns
tgbp 28 GLB Register Bypass Delay – 0.2 – 0.0 – 0.0 ns
tgsu 29 GLB Register Setup Time before Clock 0.5 – 0.7 – 0.3 – ns
tgh
tgco
30 GLB Register Hold Time after Clock
31 GLB Register Clock to Output Delay N 1.8
– 0.7
– 1.8
– 0.8
– 3.0
–
–
0.7
ns
ns
R
tgro 32 GLB Register Reset to Output Delay – 1.0 – 1.2 – 1.1 ns
FO

tptre 33 GLB Product Term Reset to Register Delay – 2.8 – 2.9 – 4.4 ns
tptoe 34 GLB Product Term Output Enable to I/O Cell Delay – 5.9 – 6.9 – 6.4 ns
tptck 35 GLB Product Term Clock Delay 2.5 3.8 2.5 4.1 2.9 5.2 ns
2E

ORP
torp 36 ORP Delay – 0.7 – 0.8 – 1.3 ns
03

torpbp 37 ORP Bypass Delay – 0.2 – 0.3 – 0.3 ns

Outputs
I2

tob 38 Output Buffer Delay – 1.2 – 1.3 – 1.2 ns

tsl 39 Output Slew Limited Delay Adder – 10.0 – 10.0 – 10.0 ns
S

toen 40 I/O Cell OE to Output Enabled – 2.8 – 2.8 – 3.2 ns

pL

todis 41 I/O Cell OE to Output Disabled – 2.8 – 2.8 – 3.2 ns

tgoe 42 Global Output Enable – 2.2 – 2.2 – 2.8 ns
is

Clocks
tgy0 43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) 1.9 1.9 2.1 2.1 2.3 2.3 ns
SE

tgy1/2 44 Clock Delay, Y1 or Y2 to Global GLB Clock Line 1.9 1.9 2.1 2.1 2.3 2.3 ns
Global Reset
U

tgr 45 Global Reset to GLB – 4.1 – 4.7 – 6.4 ns

Table 2-0036C-180/2032
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.

7
 Specifications ispLSI 2032/A

Internal Timing Parameters1

Over Recommended Operating Conditions

2
-110 -80
PARAMETER # DESCRIPTION UNITS
MIN. MAX. MIN. MAX.
Inputs
tio 20 Input Buffer Delay – 1.7 – 2.2 ns

S
tdin 21 Dedicated Input Delay – 3.4 – 4.8 ns

N
See Ordering Information section for product status.
GRP
tgrp

IG
22 GRP Delay – 1.7 – 2.6 ns
GLB

ES
t4ptbpc 23 4 Product Term Bypass Path Delay (Combinatorial) – 4.9 – 7.2 ns

Select devices have been discontinued.

t4ptbpr 24 4 Product Term Bypass Path Delay (Registered) – 4.8 – 7.2 ns
t1ptxor

D
25 1 Product Term/XOR Path Delay – 6.2 – 8.8 ns
t20ptxor 26 20 Product Term/XOR Path Delay – 6.8 – 9.2 ns

EW
txoradj 27 XOR Adjacent Path Delay 3
– 7.5 – 10.2 ns
tgbp 28 GLB Register Bypass Delay – 0.1 – 0.0 ns
tgsu 29 GLB Register Setup Time befor Clock 0.5 – 0.1 – ns
tgh
tgco
30 GLB Register Hold Time after Clock
31 GLB Register Clock to Output Delay N 4.0
– 0.6
– 6.0
–
–
0.4
ns
ns
R
tgro 32 GLB Register Reset to Output Delay – 1.8 – 2.2 ns
FO

tptre 33 GLB Product Term Reset to Register Delay – 5.9 – 8.8 ns

tptoe 34 GLB Product Term Output Enable to I/O Cell Delay – 7.1 – 12.8 ns
tptck 35 GLB Product Term Clock Delay 4.0 7.0 5.5 9.5 ns
2E

ORP
torp 36 ORP Delay – 1.5 – 2.1 ns
03

torpbp 37 ORP Bypass Delay – 0.5 – 0.6 ns

Outputs
I2

tob 38 Output Buffer Delay – 1.2 – 2.4 ns

tsl 39 Output Slew Limited Delay Adder – – 10.0 ns
S

10.0
toen 40 I/O Cell OE to Output Enabled – 4.0 – 6.4 ns
pL

todis 41 I/O Cell OE to Output Disabled – 4.0 – 6.4 ns

tgoe 42 Global Output Enable – 3.0 – 5.6 ns
is

Clocks
tgy0 43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) 3.2 3.2 4.6 4.6 ns
SE

tgy1/2 44 Clock Delay, Y1 or Y2 to Global GLB Clock Line 3.2 3.2 4.6 4.6 ns
Global Reset
U

tgr 45 Global Reset to GLB – 9.0 – 12.8 ns

Table 2-0036C-110/2032
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.

8
 Specifications ispLSI 2032/A

ispLSI 2032/A Timing Model

I/O Cell GRP GLB ORP I/O Cell

Feedback

Ded. In Comb 4 PT Bypass #23

#21

S
I/O Delay GRP Reg 4 PT Bypass GLB Reg Bypass ORP Bypass #38,
I/O Pin 39 I/O Pin
#20 #22 #24 #28 #37

N
(Input) (Output)

See Ordering Information section for product status.

20 PT GLB Reg ORP
XOR Delays Delay Delay

IG
D Q
#25, 26, 27 #36
RST

ES
#45 #29, 30,

Select devices have been discontinued.

Reset 31, 32

D
Control RE
PTs OE

EW
#33, 34, CK
35 #40, 41

#43, 44
Y0,1,2
#42

N
GOE 0
0491/2000
R
Derivations of tsu, th and tco from the Product Term Clock 1
FO

tsu = Logic + Reg su - Clock (min)

= (tio + tgrp + t20ptxor) + (tgsu) - (tio + tgrp + tptck(min))
= (#20+ #22+ #26) + (#29) - (#20+ #22+ #35)
2E

2.1 ns = (0.6 + 0.7 + 4.1) + (0.5) - (0.6 + 0.7 + 2.5)

th = Clock (max) + Reg h - Logic
03

= (tio + tgrp + tptck(max)) + (tgh) - (tio + tgrp + t20ptxor)

= (#20+ #22+ #35) + (#30) - (#20+ #22+ #26)
I2

1.5 ns = (0.6 + 0.7 + 3.8) + (1.8) - (0.6 + 0.7 + 4.1)

tco = Clock (max) + Reg co + Output
S

= (tio + tgrp + tptck(max)) + (tgco) + (torp + tob)

= (#20+ #22+ #35) + (#31) + (#36 + #38)
pL

7.7 ns = (0.6 + 0.7 + 3.8) + (0.7) + (0.7 + 1.2)

is

Note: Calculations are based upon timing specifications for the ispLSI 2032/A-180L
Table 2- 0042-16/2032
SE
U

9
 Specifications ispLSI 2032/A

Power Consumption
Power consumption in the ispLSI 2032 and 2032A de- used. Figure 4 shows the relationship between power
vices depends on two primary factors: the speed at which and operating speed.
the device is operating and the number of Product Terms

Figure 4. Typical Device Power Consumption vs fmax

S
N
See Ordering Information section for product status.
IG
120

ES
110

Select devices have been discontinued.

ispLSI 2032/A (-150, -180)
100

D
ICC (mA)

90

EW
80

70
ispLSI 2032/A (-80, -110, -135)

N
60

50
R
40
FO

1 20 40 60 80 100 120 140 160 180

fmax (MHz)
2E

Notes: Configuration of Two 16-bit Counters

Typical Current at 5V, 25° C
03

ICC can be estimated for the ispLSI 2032/A using the following equation:
I2

For 2032/A -150, -180: ICC(mA) = 30 + (# of PTs * 0.46) + (# of nets * Max freq * 0.012)
For 2032/A -135, -110, -80: ICC(mA) = 21 + (# of PTs * 0.30) + (# of nets * Max freq * 0.012)
S
pL

Where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
is

Max freq = Highest Clock Frequency to the device (in MHz)

SE

The ICC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of two GLB loads
on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions
and the program in the device, the actual ICC should be verified.
U

0127A/2032A

10
 Specifications ispLSI 2032/A

Pin Description

44-PIN PLCC 44-PIN TQFP 48-PIN TQFP

NAME PIN NUMBERS PIN NUMBERS PIN NUMBERS DESCRIPTION
I/O 0 - I/O 3 15, 16, 17, 18, 9, 10, 11, 12, 9, 10, 11, 13, Input/Output Pins — These are the general purpose
I/O 4 - I/O 7 19, 20, 21, 22, 13, 14, 15, 16, 14, 15, 16, 17, I/O pins used by the logic array.
I/O 8 - I/O 11 25, 26, 27, 28, 19, 20, 21, 22, 20, 21, 22, 23,
I/O 12 - I/O 15 29, 30, 31, 32, 23, 24, 25, 26, 25, 26, 27, 28,
I/O 16 - I/O 19 38, 39, 40, 33, 34, 33, 34, 35, 37,

S
37, 31 32,
I/O 20 - I/O 23 41, 42, 43, 44, 35, 36, 37, 38, 38, 39, 40, 41,
I/O 24 - I/O 27 5, 6, 44, 44, 45, 46, 47,

N
3, 4, 41, 42, 43,

See Ordering Information section for product status.

I/O 28 - I/O 31 7, 8, 9, 10 1, 2, 3, 4 1, 2, 3, 4

IG
GOE 0 2 40 43 Global Output Enable input pin.

Y0 11 5 5 Dedicated Clock input. This clock input is connected to

ES
one of the clock inputs of all the GLBs on the device.

Select devices have been discontinued.

RESET/Y1 35 29 31 This pin performs two functions:
- Dedicated clock input. This clock input is brought

D
into the Clock Distribution Network, and can optionally
be routed to any GLB and/or I/O cell on the device.
- Active Low (0) Reset pin which resets all of the GLB

EW
and I/O registers in the device.
ispEN 13 7 7 Input — Dedicated in-system programming enable
input pin. This pin is brought low to enable the
programming mode. The MODE, SDI, SDO and SCLK

N
controls become active.
SDI/IN 02 14 8 8 Input — This pin performs two functions. When ispEN
R
is logic low, it functions as an input pin to load
programming data into the device. SDI/IN0 also is used
as one of the two control pins for the isp state machine.
FO

When ispEN is high, it functions as a dedicated input

pin.
MODE 36 30 32 Input — When in ISP Mode, controls operation of ISP
state machine.
2E

SDO/IN 12 24 18 19 Output/Input — This pin performs two functions. When

ispEN is logic low, it functions as an output pin to read
serial shift register data. When ispEN is high, it
03

functions as a dedicated input pin.

SCLK/Y22 33 27 29 Input — This pin performs two functions. When
I2

ispEN is logic low, it functions as a clock pin for the

Serial Shift Register. When ispEN is high, it
functions as a dedicated clock input. This clock input
S

is brought into the Clock Distribution Network and

can be routed to any GLB and/or I/O cell on the
pL

device.
GND 1, 23 17, 39 18, 42 Ground (GND)
VCC 12, 34 6, 28 6, 30 VCC
is

NC1 12, 24, 36, 48 No Connect.

Table 2-0002A-08isp/2032
SE

1. NC pins are not to be connected to any active signals, VCC or GND.

2. Pins have dual function capability.
U

11
 Specifications ispLSI 2032/A

Pin Configuration
ispLSI 2032/A 44-Pin PLCC Pinout Diagram

GOE 0
I/O 27
I/O 26
I/O 25
I/O 24

I/O 23
I/O 22
I/O 21
I/O 20
I/O 19
GND
6 5 4 3 2 1 44 43 42 41 40

S
N
I/O 28 7 39 I/O 18

See Ordering Information section for product status.

I/O 29 8 38 I/O 17

IG
I/O 30 9 37 I/O 16
I/O 31 10 36 MODE

ES
Y0 11 35 RESET/Y1

Select devices have been discontinued.

VCC 12 ispLSI 2032/A 34 VCC
ispEN 13 33 SCLK/Y21
Top View

D
1SDI/IN 0 14 32 I/O 15
I/O 0 15 31 I/O 14

EW
I/O 1 16 30 I/O 13
I/O 2 17 29 I/O 12

18 19 20 21 22 23 24 25 26 27 28

N
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
GND
1
I/O 8
I/O 9
I/O 10
I/O 11
1SDO/IN

R
0123B/2032/A
FO

1. Pins have dual function capability.

2E

ispLSI 2032/A 44-Pin TQFP Pinout Diagram

03
GOE 0
I/O 27
I/O 26
I/O 25
I/O 24

I/O 23
I/O 22
I/O 21
I/O 20
I/O 19
GND
I2

44 43 42 41 40 39 38 37 36 35 34

I/O 28 1 33 I/O 18
S

I/O 29 2 32 I/O 17
pL

I/O 30 3 31 I/O 16
I/O 31 4 30 MODE
Y0 5 29 RESET/Y1
ispLSI 2032/A
is

VCC 6 28 VCC
ispEN 7 Top View 27 SCLK/Y21
SE

1SDI/IN 0 8 26 I/O 15
I/O 0 9 25 I/O 14
I/O 1 10 24 I/O 13
U

I/O 2 11 23 I/O 12

12 13 14 15 16 17 18 19 20 21 22
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
GND
1
I/O 8
I/O 9
I/O 10
I/O 11
1SDO/IN

0851/2032/A

1. Pins have dual function capability.

12
 Specifications ispLSI 2032/A

Pin Configuration
ispLSI 2032/A 48-Pin TQFP Pinout Diagram

GOE 0
I/O 27
I/O 26
I/O 25
I/O 24

I/O 23
I/O 22
I/O 21
I/O 20
I/O 19
GND
NC1
48 47 46 45 44 43 42 41 40 39 38 37

S
I/O 28 1 36 NC1
I/O 29 2 35 I/O 18

N
See Ordering Information section for product status.
I/O 30 3 34 I/O 17

IG
I/O 31 4 33 I/O 16
Y0 5 32 MODE
ispLSI 2032/A RESET/Y12

ES
VCC 6 31

Select devices have been discontinued.

ispEN 7 30 VCC
Top View
2SDI/IN 0 8 29 SCLK/Y22

D
I/O 0 9 28 I/O 15
I/O 1 10 27 I/O 14
I/O 2 11 26 I/O 13

EW
1NC 12 25 I/O 12
13 14 15 16 17 18 19 20 21 22 23 24

1NC
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
GND
2SDO/IN 1

I/O 8
I/O 9
I/O 10
I/O 11
N
R
48-Pin TQFP-2032/A
FO

1. NC pins are not to be connected to any active signal, Vcc or GND.

2. Pins have dual function capability.
2E
03
S I2
pL
is
SE
U

13
 Specifications ispLSI 2032/A

Part Number Description

ispLSI XXXX – XXX X XXX X
Device Family Grade
Blank = Commercial
Device Number I = Industrial
20321 Package

S
2032A J = PLCC

N
See Ordering Information section for product status.
T44 = TQFP
Speed
T48 = TQFP

IG
180 = 180 MHz fmax
JN = Lead-Free PLCC
150 = 154 MHz fmax
TN48 = Lead-Free TQFP

ES
135 = 137 MHz fmax

Select devices have been discontinued.

TN48 = Lead-Free TQFP
110 = 111 MHz fmax
80 = 84 MHz fmax Power

D
L = Low
1. Discontinued per PCN #02-06. Contact Rochester Electronics for available inventory.

EW
ispLSI 2032/A Ordering Information
Conventional Packaging
N
R
COMMERCIAL
FO

FAMILY fmax (MHz) tpd (ns) ORDERING NUMBER PACKAGE

180 5.0 ispLSI 2032A-180LJ44 44-Pin PLCC
180 5.0 ispLSI 2032A-180LT44 44-Pin TQFP
2E

180 5.0 ispLSI 2032A-180LT48 48-Pin TQFP

154 5.5 ispLSI 2032A-150LJ44 44-Pin PLCC
03

154 5.5 ispLSI 2032A-150LT44 44-Pin TQFP

154 5.5 ispLSI 2032A-150LT48 48-Pin TQFP
137 7.5 ispLSI 2032A-135LJ44 44-Pin PLCC
I2

ispLSI 137 7.5 ispLSI 2032A-135LT44 44-Pin TQFP

137 7.5 ispLSI 2032A-135LT48 48-Pin TQFP
S

111 10 ispLSI 2032A-110LJ44 44-Pin PLCC

pL

111 10 ispLSI 2032A-110LT44 44-Pin TQFP

111 10 ispLSI 2032A-110LT48 48-Pin TQFP
84 15 44-Pin PLCC
is

ispLSI 2032A-80LJ44
84 15 ispLSI 2032A-80LT44 44-Pin TQFP
84 15 ispLSI 2032A-80LT48 48-Pin TQFP
SE

Table 2-0041A/2032A

INDUSTRIAL
U

FAMILY fmax (MHz) tpd (ns) ORDERING NUMBER PACKAGE

84 15 ispLSI 2032A-80LJ44I 44-Pin PLCC
ispLSI 84 15 ispLSI 2032A-80LT44I 44-Pin TQFP
84 15 ispLSI 2032A-80LT48I 48-Pin TQFP
Table 2-0041B/2032A

14
 Specifications ispLSI 2032/A

ispLSI 2032/A Ordering Information (Cont.)

Conventional Packaging
COMMERCIAL
FAMILY fmax (MHz) tpd (ns) ORDERING NUMBER PACKAGE
180 5.0 ispLSI 2032A-180LJ441 44-Pin PLCC
180 5.0 ispLSI 2032A-180LT441 44-Pin TQFP

S
180 5.0 ispLSI 2032A-180LT481 48-Pin TQFP
154 5.5 ispLSI 2032A-150LJ441 44-Pin PLCC

N
See Ordering Information section for product status.
154 5.5 ispLSI 2032A-150LT441 44-Pin TQFP

IG
154 5.5 ispLSI 2032A-150LT481 48-Pin TQFP
137 7.5 ispLSI 2032A-135LJ441 44-Pin PLCC

ES
ispLSI 137 7.5 ispLSI 2032A-135LT441 44-Pin TQFP

Select devices have been discontinued.

137 7.5 ispLSI 2032A-135LT481 48-Pin TQFP
111 10 ispLSI 2032A-110LJ441 44-Pin PLCC

D
111 10 ispLSI 2032A-110LT441 44-Pin TQFP
111 10 ispLSI 2032A-110LT481 48-Pin TQFP

EW
84 15 ispLSI 2032A-80LJ441 44-Pin PLCC
84 15 ispLSI 2032A-80LT441 44-Pin TQFP
84 15 ispLSI 2032A-80LT481 48-Pin TQFP

N
1. Discontinued per PCN #02-06. Contact Rochester Electronics for available inventory.
R
INDUSTRIAL
FO

FAMILY fmax (MHz) tpd (ns) ORDERING NUMBER PACKAGE

84 15 ispLSI 2032-80LJI1 44-Pin PLCC
ispLSI 84 15 ispLSI 2032-80LT44I1 44-Pin TQFP
2E

84 15 ispLSI 2032-80LT48I1 48-Pin TQFP

1. Discontinued per PCN #02-06. Contact Rochester Electronics for available inventory.
03

Lead-Free Packaging
I2

COMMERCIAL
S

FAMILY fmax (MHz) tpd (ns) ORDERING NUMBER PACKAGE

180 5.0 ispLSI 2032A-180LJN44 Lead-Free 44-Pin PLCC
pL

180 5.0 ispLSI 2032A-180LTN44 Lead-Free 44-Pin TQFP

180 5.0 ispLSI 2032A-180LTN48 Lead-Free 48-Pin TQFP
is

154 5.5 ispLSI 2032A-150LJN44 Lead-Free 44-Pin PLCC

154 5.5 ispLSI 2032A-150LTN44 Lead-Free 44-Pin TQFP
SE

154 5.5 ispLSI 2032A-150LTN48 Lead-Free 48-Pin TQFP

137 7.5 ispLSI 2032A-135LJN44 Lead-Free 44-Pin PLCC
ispLSI 137 7.5 ispLSI 2032A-135LTN44 Lead-Free 44-Pin TQFP
U

137 7.5 ispLSI 2032A-135LTN48 Lead-Free 48-Pin TQFP

111 10 ispLSI 2032A-110LJN44 Lead-Free 44-Pin PLCC
111 10 ispLSI 2032A-110LTN44 Lead-Free 44-Pin TQFP
111 10 ispLSI 2032A-110LTN48 Lead-Free 48-Pin TQFP
84 15 ispLSI 2032A-80LJN44 Lead-Free 44-Pin PLCC
84 15 ispLSI 2032A-80LTN44 Lead-Free 44-Pin TQFP
84 15 ispLSI 2032A-80LTN48 Lead-Free 48-Pin TQFP

15
 Specifications ispLSI 2032/A

ispLSI 2032/A Ordering Information (Cont.)

Lead-Free Packaging
INDUSTRIAL
FAMILY fmax (MHz) tpd (ns) ORDERING NUMBER PACKAGE
84 15 ispLSI 2032A-80LJN44I Lead-Free 44-Pin PLCC
ispLSI 84 15 ispLSI 2032A-80LTN44I Lead-Free 44-Pin TQFP

S
84 15 ispLSI 2032A-80LTN48I Lead-Free 48-Pin TQFP

N
See Ordering Information section for product status.
IG
Revision History

ES
Date Version Change Summary

Select devices have been discontinued.

— 10 Previous Lattice release.

D
August 2006 11 Updated for lead-free package options.

EW
N
R
FO
2E
03
S I2
pL
is
SE
U

16