HALF ADDER
HALF SUBTRACTOR
TRUTH TABLE
2 to 4 DECODER
TRUTH TABLE
AND GATE
OR Gate & Truth Table
NOT Gate & Truth Table
Assignment No.4
Aim :Write the VHDL code for 8:1 Multiplexer using components and draw a
suitable diagram with truth table.
Software Used: Xilinx Tools.
CODING:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity mux8to1 is
Port ( s0 : in std_logic;
s1 : in std_logic;
s2 : in std_logic;
s3 : in std_logic;
s4 : in std_logic;
s5 : in std_logic;
s6 : in std_logic;
s7 : in std_logic;
a : in std_logic;
b : in std_logic;
c : in std_logic;
o : out std_logic);
end mux8to1;
architecture structural of mux8to1 is
component mux4to1 is
port(s0,s1,s2,s3,a,b : in std_logic;
o1 : out std_logic);
end component;
component mux2to1 is
port(s0,s1,a: in std_logic;o:out std_logic) ;
end component;
signal o1,o2 :std_logic;
begin
x1 : mux4to1 port map(s0,s1,s2,s3,a,b,o1);
x2 : mux4to1 port map(s4,s5,s6,s7,a,b,o2);
x3 : mux2to1 port map(o1,o2,c,o);
end structural;
4.1 : COMPONENT MUX 2:1 :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity mux8to1 is
Port ( s0 : in std_logic;
s1 : in std_logic;
s2 : in std_logic;
s3 : in std_logic;
s4 : in std_logic;
s5 : in std_logic;
s6 : in std_logic;
s7 : in std_logic;
a : in std_logic;
b : in std_logic;
c : in std_logic;
o : out std_logic);
end mux8to1;
architecture structural of mux8to1 is
component mux4to1 is
port(s0,s1,s2,s3,a,b : in std_logic;
o1 : out std_logic);
end component;
component mux2to1 is
port(s0,s1,a: in std_logic;o:out std_logic) ;
end component;
signal o1,o2 :std_logic;
begin
x1 : mux4to1 port map(s0,s1,s2,s3,a,b,o1);
x2 : mux4to1 port map(s4,s5,s6,s7,a,b,o2);
x3 : mux2to1 port map(o1,o2,c,o);
end structural;
4.2 : COMPONENT MUX 4:1 :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity mux4to1 is
Port ( s0 : in std_logic;
s1 : in std_logic;
s2 : in std_logic;
s3 : in std_logic;
a,b: in std_logic;
o1 : out std_logic);
end mux4to1;
architecture Behavioral of mux4to1 is
component or2 is
port(p,q,r,t:in std_logic ;s:out std_logic);
end component ;
component and2 is
port(p,q,r:in std_logic ;s:out std_logic);
end component ;
component not1 is
port(p:in std_logic ;s:out std_logic);
end component ;
signal d0,d1,d2,d3,ad,bd:std_logic;
begin
x1: not1 port map (a,ad);
x2: not1 port map (b,bd);
x3: and2 port map (ad,bd,s0,d0);
x4: and2 port map (ad,b,s1,d1);
x5: and2 port map (a,bd,s2,d2);
x6: and2 port map (a,b,s3,d3);
x7: or2 port map (d0,d1,d2,d3,o1);
end Behavioral;
