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Four-Resistor Bias Network Design

This document describes the design objectives for a four-resistor bias network. It provides equations to calculate the bias current IE based on the equivalent resistance REQ, bias voltage VEQ, and transistor base-emitter voltage VBE. It states that REQ is designed such that its voltage drop is negligible. The document then calculates IE as 206μA for a given circuit. It also discusses constraints such as choosing the current I2 to be less than one-fifth the collector current IC and ensuring I2 is much greater than the bias current IB.

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Enock Kachokola
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142 views4 pages

Four-Resistor Bias Network Design

This document describes the design objectives for a four-resistor bias network. It provides equations to calculate the bias current IE based on the equivalent resistance REQ, bias voltage VEQ, and transistor base-emitter voltage VBE. It states that REQ is designed such that its voltage drop is negligible. The document then calculates IE as 206μA for a given circuit. It also discusses constraints such as choosing the current I2 to be less than one-fifth the collector current IC and ensuring I2 is much greater than the bias current IB.

Uploaded by

Enock Kachokola
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

Design Objectives for Four-Resistor Bias Network

V EQ = R EQ I B + V BE + R E I E
VCC = 12V
V EQ – V BE – R EQ I B
I E = ---------------------------------------------------- or R1 22 kΩ RC
RE 36 kΩ
V EQ – V BE I1
I E ≈ ---------------------------- for R EQ I B « V EQ – V BE
RE IB
I2
R EQ is designed so that its voltage drop is R2
16 kΩ RE
negligible. 18 kΩ

In this case, I E is determined by V EQ , V BE


V EQ – V BE 4 – 0.7
and R E . I E ≈ ---------------------------- = ---------------- = 206µA .
RE 16k

Another constraint is power dissipation. Choose I 2 ≤ I C ⁄ 5 . Now, power dissi-


pated in R 1 and R 2 is less than 17% of total quiescent power. Also, I 2 » I B for
β F ≥ 50 .

Lecture 28 28 - 1
Basic Current Mirror
For VBE = 0.7V, βF = 100, VA = 0V and IS =
VB, 12V VCC, 12V
1.4x10-16A (redundant). Find IREF and IC2.
Assume that both transistors are matched. R
IREF 56 kΩ IC2
Both transistors operate in forward-active
IC1
region.
V B – V C1 IB1 + I
12 – 0.7 B2
I REF = ----------------------- = ------------------- = 202µA VBE
R 56k
-
I C1
I REF = I C1 + I B1 + I B2 but -------- = I B1 = I B2
βF

∴I REF = I B2 ( β F + 2 ) ⇒ I B2 = 1.98µA

Therefore, I C2 = β F I B2 = 198µA ≈ I REF

IC 198µA – 16
I S = ---------------------- = ---------------------- = 1.37 ×10 A
V ⁄V e 0.7 / 0.025
e BE T

Lecture 28 28 - 2
Two-Resistor Bias Circuit
Find the Q-point for the circuit shown if βF = 75 and VBE = 10V
0.7V. 1.2 kΩ
10 = 1.2k ( I C + I B ) + 5kI B + V BE 5 kΩ
Assume transistor operates in forward-active region, IC
I C = β F I B and 10 = 1.2k ( β F I B + I B ) + 5kI B + V BE . IB
10 – V BE
IB = --------------------------------------------
-
1.2k ( β F + 1 ) + 5k

10 – V BE 10 – 0.7
I C = β F I B = β F --------------------------------------------- = 75 -------------------------------------------- = 7.25mA
1.2k ( β F + 1 ) + 5k 1.2k ( 75 + 1 ) + 5k

 IC 
V CE = 10 – 1.2k ( I C + I B ) = 10 – 1.2k  I C + ------ = 1.18V
 β F

Since V CE > V BE > 0 , our assumption is correct.

Lecture 28 28 - 3
A PNP Transistor Example
Find the Q-point of the shown circuit
since the emitter is connected to a higher potential than the
10V
base we have V
EB = 0.7V 2 kΩ

The emitter current is found through the loop IE


β = 100

10 = 0.7 + 2I E to get I E = 4.65mA


IB

Assuming forward active region we have I C = αI E = 4.6mA 1 kΩ

-10V
Checking the region of operation by calculating V CB we get
V CB = – 10 + I C × 1K = – 5.4V

it follows that the Collector-base junction is reverse-biased and our assump-


tion of forward active region is correct

Lecture 28 28 - 4

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