EE244 – Digital Logic Design – Fall 2012 Semester Lecture Notes Set #10

Dr. Kam F. Yee Nov 28, 2012

Mealy and Moore Sequential Circuits

Differ in the way the outputs are generated.

Moore:
• All outputs are functions of only the present state (flip-flops).
• All outputs are synchronized with the clock. Outputs don’t typically
change in the middle of a clock cycle.

Mealy:
• Any one of the outputs is a function of both the present state (flip-flops)
and the external inputs.
• Outputs may change if the external inputs change during a clock cycle.

Timing Trace

Shows the sequential behavior or a sequential circuit for a given input

sequence.

Given a state diagram (or state table), and an input sequence, determine the
output sequence. (This is a circuit that outputs a 1 when three or more
consecutive 1’s are found the in the input sequence.)

State A
Input 0 0 1 1 1 0 1 1 1 1 0 1
Output

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EE244 – Digital Logic Design – Fall 2012 Semester Lecture Notes Set #10
Dr. Kam F. Yee Nov 28, 2012

5.7: State Reduction

Goal: Given a state table, reduce number of states if possible, while maintain-
ing same circuit behavior. (Similar to simplification of Boolean functions.)
Why? Fewer states → fewer FF’s → simpler comb. logic → smaller circuit

1) Use fewer flip-flops

Ex. 5 states → ____ FF’s. If reduced to 4 states → ____ FF’s

2) Add don’t cares because of unused states

Ex. 8 states → ____ FF’s. If reduced to 6 states → ____ FF’s
No change in number of FF’s. But there are ____ unused states,
which introduce don’t cares (which helps in simplification).

State Equivalency Rule. Two states are equivalent if and only if:
- Outputs are identical for each input combination, and
- Next-states are identical for each input combination.
Ex. States A and C have identical rows ⇒ A ≡ C (A and C are equivalent)
Present Next State Output Present Next State Output
State x = 0 x = 1 x = 0 x = 1 State x = 0 x = 1 x = 0 x = 1
A A B 0 1 A A B 0 1
B C D 0 0 B A D 0 0
C A B 0 1 D D A 1 0
D D C 1 0 Reduced State Table (3 states)

Ex. States B and D have same outputs. Identical Next State under x=1.
Cross-reference each other under x=0 ⇒ B ≡ D (B and D are equivalent)
Present Next State Output Present Next State Output
State x = 0 x = 1 x = 0 x = 1 State x = 0 x = 1 x = 0 x = 1
A B C 0 1 A B C 0 1
B D A 0 0 B B A 0 0
C C A 0 1 C C A 0 1
D B A 0 0 Reduced State Table (3 states)

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EE244 – Digital Logic Design – Fall 2012 Semester Lecture Notes Set #10
Dr. Kam F. Yee Nov 28, 2012

Ex. The following state tables cannot be reduced any further.

Present Next State Output Present Next State Output
State x = 0 x = 1 x = 0 x = 1 State x = 0 x = 1 x = 0 x = 1
A A B 0 1 S0 S0 S1 0 1
B C D 0 0 S1 S2 S3 0 0
C A B 0 0 S2 S1 S0 0 1
D D C 1 0 S3 S3 S2 1 0
A,C have different outputs S0, S2 have different Next States

Ex. Reduce the following state table. Hint: 3 states.

Present Next State Output
State xy = 00 xy = 01 xy = 10 xy = 11
A A B C D 1
No identical rows.
B D C B B 1
C C B C C 0 No “obvious” reduction.
D D B C A 1
E E B C A 1
By considering Output column only:
- C cannot be reduced (its output is unique)
- A, B, D, E can potentially be equivalent (same output)
By considering Next State columns:
- A ≡ D (same Next State under xy=01, xy=10, and cross-reference each
other under xy=00, xy=11)
Present Next State Output
State xy = 00 xy = 01 xy = 10 xy = 11
A A B C A 1
B A C B B 1
C C B C C 0
E E B C A 1
A ≡ E (cross-reference each other)
Present Next State Output
State xy = 00 xy = 01 xy = 10 xy = 11
A A B C A 1 Reduced to 3 states
B A C B B 1
C C B C C 0
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EE244 – Digital Logic Design – Fall 2012 Semester Lecture Notes Set #10
Dr. Kam F. Yee Nov 28, 2012

5.7: State Assignment

Goal: Assign unique binary-coded values to the states of a sequential circuit.
A circuit with m states requires at least n bits, where m ≤ 2n [or, n ≥ log2(m)].

A sequential circuit has m = 5 states. At least n = _____ bits are needed.

Many possible state assignments. Three possibilities are shown:

Straightforward Gray Code One-Hot

State Binary Assignment Encoding
Assignment Assignment
A 000 000 00001
B 001 001 00010
C 010 011 00100
D 011 010 01000
E 100 110 10000
“Normal” binary Gray code Only one bit = 1,
counting order counting order the rest are zeros
(n = 3 flip-flops) (n = 3 flip-flops) (n = 5 flip-flops)

Other possibilities are:

State
A 111 000
B 110 111
C 101 100
D 100 011
E 011 010

Different assignments produce different circuits (some simpler than others).

Regardless of the state assignment, behavior of the circuits are the same.

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EE244 – Digital Logic Design – Fall 2012 Semester Lecture Notes Set #10
Dr. Kam F. Yee Nov 28, 2012

Ex. Given the following state table, assign states using Gray Code Assignment.
State Table Binary State Table
Present Next State Output Present Next State Output
State x=0 x=1 Y State x=0 x=1
q1 q2 q3 q1* q2* q3* q1* q2* q3* Y
A A B 0
B C D 0
C A D 1
D E D 0
E A D 1
n = 3 flip-flops ⇒ 8 combinations total
⇒ 3 unused combinations

5.8: Design of Sequential Circuits

Goal: Given a set of specifications of a circuit’s behavior, obtain the
required Boolean functions and a logic circuit diagram.
(Reverse process of Analysis of Sequential Circuits).
Procedure: (slightly different from textbook, but same ultimate goal)
Given word description of circuit behavior:
1) Derive a state diagram and state table
2) Reduce number of states [if required]
3) Perform state assignment ← Assign binary codes to the states
4) Derive binary-coded state table
5) Choose flip-flop excitation table (depends on type of F/F used)
6) Derive transition table and excitation table (2 tables, combined in 1)
7) Derive simplified equations of F/F inputs and circuit’s outputs
8) Draw logic circuit diagram

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EE244 – Digital Logic Design – Fall 2012 Semester Lecture Notes Set #10
Dr. Kam F. Yee Nov 28, 2012

Function Tables – Given F/F input and Pres. State → determines Next State
Input Next State Inputs Next State Input Next State
D Q* J K Q* T Q*
0 0 0 0 No change 0 No change
1 1 0 1 0 1 Complement
1 0 1
1 1 Complement
Q* = D Q* = J Q’ + K’Q Q* = T ⊕ Q

Excitation Tables – Given P.S. and N.S. → determines required F/F input value
PS NS FF input PS NS FF inputs PS NS FF input
Q Q* D Q Q* J K Q Q* T
0 0 0 0 0 0 x 0 0 0
0 1 1 0 1 1 x 0 1 1
1 0 0 1 0 x 1 1 0 1
1 1 1 1 1 x 0 1 1 0
D = NS If PS=0 ⇒ J=NS, K=x If PS=NS ⇒ T=0
If PS=1 ⇒ J=x, K=NS’ If PS=NS ⇒ T=1

Design Ex. 1 (p.328). Design a sequential circuit, using D flip-flops, that

implements the functionality given in the following state table:

x y
Your circuit
Clock

1) State Diagram and State Table

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EE244 – Digital Logic Design – Fall 2012 Semester Lecture Notes Set #10
Dr. Kam F. Yee Nov 28, 2012

2) State Reduction

3) State Assignment 4) Binary State Table

5) Choose Flip-Flop Excitation Table

6) Derive Transition Table and Excitation Table (2 tables, but combined in 1)

Present Input Next Output FF
State State Inputs
qA qB x qA* qB* y DA DB Transition Table: Given
Present State and Input,
shows Next State transition.

Excitation Table: Shows

required F/F input value to
produce the transition.

Transition Excitation
Table Table
DA (qA, qB, x) = Σ( [Optional minterm lists]
DB (qA, qB, x) = Σ(
z (qA, qB, x) = Σ(
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EE244 – Digital Logic Design – Fall 2012 Semester Lecture Notes Set #10
Dr. Kam F. Yee Nov 28, 2012

7) Derive simplified equations of F/F inputs and circuit’s outputs

00 01 11 10 00 01 11 10

0 0

1 1

00 01 11 10

8) Draw Logic Circuit Diagram

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EE244 – Digital Logic Design – Fall 2012 Semester Lecture Notes Set #10
Dr. Kam F. Yee Nov 28, 2012

Ex 2. Repeat same problem, but use JK flip-flops instead.

Steps (1)→(4): No change. Exactly the same!

5) Choose Flip-Flop Excitation Table

6) Derive Transition Table and Excitation Table (2 tables, but combined in 1)

Present Input Next Output FF Inputs
State State
qA qB x qA* qB* z J A KA J B KB

7) Derive simplified equations of F/F inputs and circuit’s outputs

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EE244 – Digital Logic Design – Fall 2012 Semester Lecture Notes Set #10
Dr. Kam F. Yee Nov 28, 2012

JA (qA, qB, x) =

KA (qA, qB, x) =

JB (qA, qB, x) =

KB (qA, qB, x) =

z (qA, qB, x) =

8) Draw Logic Circuit Diagram

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EE244 – Digital Logic Design – Fall 2012 Semester Lecture Notes Set #10
Dr. Kam F. Yee Nov 28, 2012

Ex 3. Repeat same problem, but use T flip-flops instead.

Steps (1)→(4): No change. Exactly the same!

5) Choose Flip-Flop Excitation Table

6) Derive Transition Table and Excitation Table (2 tables, but combined in 1)

Present Input Next Output FF Inputs
State State
qA qB x qA* qB* z TA TB

7) Derive simplified equations of F/F inputs and circuit’s outputs

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EE244 – Digital Logic Design – Fall 2012 Semester Lecture Notes Set #10
Dr. Kam F. Yee Nov 28, 2012

TA (qA, qB, x) =

TB (qA, qB, x) =

z (qA, qB, x) =

8) Draw Logic Circuit Diagram

Points to Remember:
• A sequential circuit may be Mealy or Moore type
• A sequential circuit can be designed using D, JK, T, or a mixture of F/F’s
• Number of flip-flops in circuit is independent of F/F type
• F/F input equations depends on type of F/F used
• Output equation is the same regardless of type of F/F used
• Complexity of logic equations depends on F/F type used. Usually, JK flip-
flop gives the least-complex circuit, but it is not always guaranteed.

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