[Link].

com UNIT-3
THYRISTORS
A thyristor is the most important type of power semiconductor devices. They are
extensively used in power electronic circuits. They are operated as bi-stable switches from
non-conducting to conducting state.
A thyristor is a four layer, semiconductor of p-n-p-n structure with three p-n junctions. It has
three terminals, the anode, cathode and the gate.
The word thyristor is coined from thyratron and transistor. It was invented in the year 1957 at
Bell Labs. The Different types of Thyristors are
• Silicon Controlled Rectifier (SCR).
• TRIAC
• DIAC
• Gate Turn Off Thyristor (GTO)

3.1 Silicon Controlled Rectifier (SCR)

The SCR is a four layer three terminal device with junctions J1 , J 2 , J 3 as shown. The
construction of SCR shows that the gate terminal is kept nearer the cathode. The approximate
thickness of each layer and doping densities are as indicated in the figure. In terms of their
lateral dimensions Thyristors are the largest semiconductor devices made. A complete silicon
wafer as large as ten centimeter in diameter may be used to make a single high power
thyristor.

Gate Cathode

n
+ 19
10 cm
-3
n
+ 19
10 cm
-3
} 10µm

}
J3 - 17 -3
p 10 cm 30-100µm

}
J2
–
n 10
13
-5 x 10
14
cm
-3 50-1000 µm

J1
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p
+
10 cm
17 -3
} 30-50µm
19 -3
p 10 cm

Anode
[Link]

Fig.3.1: Structure of a generic thyristor

Qualitative Analysis
When the anode is made positive with respect the cathode junctions J1 & J 3 are
forward biased and junction J 2 is reverse biased. With anode to cathode voltage VAK being
small, only leakage current flows through the device. The SCR is then said to be in the
forward blocking state. If VAK is further increased to a large value, the reverse biased junction
J 2 will breakdown due to avalanche effect resulting in a large current through the device.
The voltage at which this phenomenon occurs is called the forward breakdown voltage VBO .
Since the other junctions J1 & J 3 are already forward biased, there will be free movement of
carriers across all three junctions resulting in a large forward anode current. Once the SCR is
switched on, the voltage drop across it is very small, typically 1 to 1.5V. The anode current is
limited only by the external impedance present in the circuit.

Fig.3.2: Simplified model of a thyristor

Although an SCR can be turned on by increasing the forward voltage beyond VBO , in practice,
the forward voltage is maintained well below VBO and the SCR is turned on by applying a
positive voltage between gate and cathode. With the application of positive gate voltage, the
leakage current through the junction J 2 is increased. This is because the resulting gate
current consists mainly of electron flow from cathode to gate. Since the bottom end layer is
heavily doped as compared to the p-layer, due to the applied voltage, some of these electrons

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reach junction J 2 and add to the minority carrier concentration in the p-layer. This raises the
reverse leakage current and results in breakdown of junction J 2 even though the applied
forward voltage is less than the breakdown voltage VBO . With increase in gate current
breakdown occurs earlier.

V-I Characteristics

RL

VAA K
VGG

Fig.3.3 Circuit

Fig 3.4: V-I Characteristics

A typical V-I characteristics of a thyristor is shown above. In the reverse direction the
thyristor appears similar to a reverse biased diode which conducts very little current until
avalanche breakdown occurs. In the forward direction the thyristor has two stable states or
modes of operation that are connected together by an unstable mode that appears as a
negative resistance on the V-I characteristics. The low current high voltage region is the
forward blocking state or the off state and the low voltage high current mode is the on state.

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For the forward blocking state the quantity of interest is the forward blocking voltage VBO
which is defined for zero gate current. If a positive gate current is applied to a thyristor then
the transition or break over to the on state will occur at smaller values of anode to cathode
voltage as shown. Although not indicated the gate current does not have to be a dc current but
instead can be a pulse of current having some minimum time duration. This ability to switch
the thyristor by means of a current pulse is the reason for wide spread applications of the
device.
However once the thyristor is in the on state the gate cannot be used to turn the device off.
The only way to turn off the thyristor is for the external circuit to force the current through
the device to be less than the holding current for a minimum specified time period.

Fig.3.5: Effects on gate current on forward blocking voltage

Holding Current I H
After an SCR has been switched to the on state a certain minimum value of anode
current is required to maintain the thyristor in this low impedance state. If the anode current
is reduced below the critical µholding current value, the thyristor cannot maintain the current
through it and reverts to its off state usually I is associated with turn off the device.

Latching Current I L

After the SCR has switched on, there is a minimum current required to sustain conduction.
This current is called the latching current. I L associated with turn on and is usually greater
than holding current.

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3.2 Thyristor Gate Characteristics

Fig. 3.6 shows the gate trigger characteristics.

Fig 3.6 Gate Characteristics

The gate voltage is plotted with respect to gate current in the above characteristics. Ig(max)
is the maximum gate current that can flow through the thyristor without damaging it
Similarly Vg(max) is the maximum gate voltage to be applied. Similarly Vg (min) and Ig(min) are
minimum gate voltage and current, below which thyristor will not be turned-on. Hence to
turn-on the thyristor successfully the gate current and voltage should be
Ig(min) < Ig < Ig(max)
Vg (min) < Vg < Vg (max)

The characteristic of Fig. 3.6 also shows the curve for constant gate power (Pg). Thus for
reliable turn-on, the (Vg, Ig) point must lie in the shaded area in Fig. 3.6. It turns-on thyristor
successfully. Note that any spurious voltage/current spikes at the gate must be less than Vg
(min) and Ig(min) to avoid false triggering of the thyristor. The gate characteristics shown in Fig.
3.6 are for DC values of gate voltage and current.

3.2.1 Pulsed
Gate Drive
Instead of applying a continuous (DC) gate drive, the pulsed gate drive is used. The gate
voltage and current are applied in the form of high frequency pulses. The frequency of these

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pulses is upto l0 kHz. Hence the width of the pulse can be upto 100 micro seconds. The pulsed
gate drive is applied for following reasons (advantages):
i) The thyristor has small turn-on time i.e. upto 5 microseconds. Hence a pulse
of gate drive is sufficient to turn-on the thyristor.
ii) Once thyristor turns-on, there is no need of gate drive. Hence gate drive in
the form of pulses is suitable.
iii) The DC gate voltage and current increases losses in the thyristor. Pulsed gate
drive has reduced losses.
iv) The pulsed gate drive can be easily passed through isolation transformers to isolate
thyristor and trigger circuit.
3.2.2 Requirement of Gate Drive
The gate drive has to satisfy the following requirements:
i) The maximum gate power should not be exceeded by gate drive, otherwise
thyristor will be damaged.
ii) The gate voltage and current should be within the limits specified by gate
characteristics (Fig. 3.6) for successful turn-on.
iii) The gate drive should be preferably pulsed. In case of pulsed drive the following
relation must be satisfied: (Maximum gate power x pulse width) x (Pulse frequency) ≤
Allowable average gate power
iv) The width of the pulse should be sufficient to turn-on the thyristor successfully.
v) The gate drive should be isolated electrically from the thyristor. This avoids any
damage to the trigger circuit if in case thyristor is damaged.
vi) The gate drive should not exceed permissible negative gate to cathode voltage,
otherwise the thyristor is damaged.
vii) The gate drive circuit should not sink current out of the thyristor after turn-on.

3.3 Quantitative Analysis

Two Transistor Model

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The general transistor equations are,

I C = β I B + (1 + β ) I CBO
I C = α I E + I CBO
I E = IC + I B
I B = I E (1 − α ) − I CBO

The SCR can be considered to be made up of two transistors as shown in above figure.
Considering PNP transistor of the equivalent circuit,

I E 1 = I A , I C = I C1 , α = α1 , I CBO = I CBO1 , I B = I B1
∴ I B1 = I A (1 − α1 ) − I CBO1 − − − (1)

Considering NPN transistor of the equivalent circuit,

I C = I C2 , I B = I B2 , I E2 = I K = I A + I G
I C2 = α 2 I k + I CBO2
I C2 = α 2 ( I A + I G ) + I CBO2 − − − ( 2)

From the equivalent circuit, we see that

∴ I C2 = I B1
α 2 I g + ICBO1 + ICBO 2
⇒ IA =
1 − (α1 + α 2 )

Two transistors analog is valid only till SCR reaches ON state

Case 1: When I g = 0 ,

I CBO1 + I CBO2
IA =
1 − (α1 + α 2 )

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The gain α1 of transistor T1 varies with its emitter current I E = I A . Similarly varies with
I E = I A + I g = I K . In this case, with I g = 0 , α 2 varies only with I A . Initially when the applied
forward voltage is small, (α1 + α 2 ) < 1 .
If however the reverse leakage current is increased by increasing the applied forward voltage,
the gains of the transistor increase, resulting in (α1 + α 2 ) → 1 .

From the equation, it is seen that when (α1 + α 2 ) = 1 , the anode current I A tends towards ∞ .
This explains the increase in anode current for the break over voltage VB 0 .

Case 2: With gate current I g applied.

When sufficient gate drive is applied, we see that I B2 = I g is established. This in turn results in
a current through transistor T2 , these increases α 2 of T2 . But with the existence
ββ
of I C2 = I
2 β2 = I ,
2 g a current through T, is established. Therefore,
IC1 = I =
1 B1 1 I =
2 B2 1 I . This current in turn is connected to the base of T2 . Thus the
2 g

base drive of T2 is increased which in turn increases the base drive of T1 , therefore
regenerative feedback or positive feedback is established between the two transistors. This
causes (α1 + α 2 ) to tend to unity therefore the anode current begins to grow towards a large
value. This regeneration continues even if I g is removed this characteristic of SCR makes it
suitable for pulse triggering; SCR is also called a Lathing Device.

3.4 Switching Characteristics (Dynamic characteristics)

Thyristor Turn-ON Characteristics

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Fig.3.7: Turn-on characteristics

When the SCR is turned on with the application of the gate signal, the SCR does not conduct
fully at the instant of application of the gate trigger pulse. In the beginning, there is no
appreciable increase in the SCR anode current, which is because, only a small portion of the
silicon pellet in the immediate vicinity of the gate electrode starts conducting. The duration
between 90% of the peak gate trigger pulse and the instant the forward voltage has fallen to
90% of its initial value is called the gate controlled / trigger delay time t gd . It is also defined
as the duration between 90% of the gate trigger pulse and the instant at which the anode
current rises to 10% of its peak value. t gd is usually in the range of 1µsec.

Once t gd has lapsed, the current starts rising towards the peak value. The period during which
the anode current rises from 10% to 90% of its peak value is called the rise time. It is also
defined as the time for which the anode voltage falls from 90% to 10% of its peak value. The
summation of t gd and tr gives the turn on time ton of the thyristor.

Thyristor Turn OFF Characteristics

VAK
tC
tq

IA
di
Commutation
Anode current dt
begins to
decrease Recovery Recombination

t1 t2 t3 t4 t5

tq=device off time

trr t gr
tc=circuit off time
t q

tc

When an SCR is turned on by the gate signal, the gate loses control over the device and the
device can be brought back to the blocking state only by reducing the forward current to a
level below that of the holding current. In AC circuits, however, the current goes through a

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natural zero value and the device will automatically switch off. But in DC circuits, where no
neutral zero value of current exists, the forward current is reduced by applying a reverse
voltage across anode and cathode and thus forcing the current through the SCR to zero.
As in the case of diodes, the SCR has a reverse recovery time trr which is due to charge
storage in the junctions of the SCR. These excess carriers take some time for recombination
resulting in the gate recovery time or reverse recombination time t gr . Thus, the turn-off time
tq is the sum of the durations for which reverse recovery current flows after the application of
reverse voltage and the time required for the recombination of all excess carriers present. At
the end of the turn off time, a depletion layer develops across J 2 and the junction can now
withstand the forward voltage. The turn off time is dependent on the anode current, the
magnitude of reverse Vg applied ad the magnitude and rate of application of the forward
voltage. The turn off time for converte grade SCR’s is 50 to 100µsec and that for inverter
grade SCR’s is 10 to 20µsec.
To ensure that SCR has successfully turned off , it is required that the circuit off time tc be
greater than SCR turn off time tq .

Thyristor Turn ON
• Thermal Turn on: If the temperature of the thyristor is high, there will be an increase
in charge carriers which would increase the leakage current. This would cause an
increase in α1 & α 2 and the thyristor may turn on. This type of turn on many cause
thermal run away and is usually avoided.
• Light: If light be allowed to fall on the junctions of a thyristor, charge carrier
concentration would increase which may turn on the SCR.
• LASCR: Light activated SCRs are turned on by allowing light to strike the silicon
wafer.
• High Voltage Triggering: This is triggering without application of gate voltage with
only application of a large voltage across the anode-cathode such that it is greater than
the forward breakdown voltage VBO . This type of turn on is destructive and should be
avoided.
• Gate Triggering: Gate triggering is the method practically employed to turn-on the
thyristor. Gate triggering will be discussed in detail later.
dv
• Triggering: Under transient conditions, the capacitances of the p-n junction will
dt
influence the characteristics of a thyristor. If the thyristor is in the blocking state, a
rapidly rising voltage applied across the device would cause a high current to flow
through the device resulting in turn-on. If i j2 is the current throught the junction j2 and
C j2 is the junction capacitance and V j2 is the voltage across j2 , then

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( )
dq2 d C j dVJ 2 dC j2
ij 2 = = C j Vj = 2 + V j2
dt dt 2 2
dt dt

dv
From the above equation, we see that if is large, 1 j2 will be large. A high value of
dt
dv
charging current may damage the thyristor and the device must be protected against high .
dt
dv
The manufacturers specify the allowable .
dt

Thyristor Ratings

First Subscript Second Subscript Third Subscript

D → off state W → working M → Peak Value
T → ON state R → Repetitive
F → Forward S →Surge or non-repetitive
R → Reverse

VOLTAGE RATINGS

VDWM : This specifies the peak off state working forward voltage of the device. This specifies
the maximum forward off state voltage which the thyristor can withstand during its working.

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VDRM : This is the peak repetitive off state forward voltage that the thyristor can block
repeatedly in the forward direction (transient).

VDSM : This is the peak off state surge / non-repetitive forward voltage that will occur across
the thyristor.

VRWM : This the peak reverse working voltage that the thyristor can withstand in the reverse
direction.

VRRM : It is the peak repetitive reverse voltage. It is defined as the maximum permissible
instantaneous value of repetitive applied reverse voltage that the thyristor can block in
reverse direction.

VRSM : Peak surge reverse voltage. This rating occurs for transient conditions for a specified
time duration.

VT : On state voltage drop and is dependent on junction temperature.

VTM : Peak on state voltage. This is specified for a particular anode current and junction
temperature.

dv
rating: This is the maximum rate of rise of anode voltage that the SCR has to withstand
dt
dv
and which will not trigger the device without gate signal (refer triggering).
dt

Current Rating

ITaverage : This is the on state average current which is specified at a particular temperature.

ITRMS : This is the on-state RMS current.

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Latching current, I L : After the SCR has switched on, there is a minimum current required to
sustain conduction. This current is called the latching current. I L associated with turn on and
is usually greater than holding current

Holding current, I H : After an SCR has been switched to the on state a certain minimum
value of anode current isµ required to maintain the thyristor in this low impedance state. If the
anode current is reduced below the critical holding current value, the thyristor cannot
maintain the current through it and reverts to its off state usually I is associated with turn off
the device.

di
rating: This is a non repetitive rate of rise of on-state current. This maximum value of rate
dt
of rise of current is which the thyristor can withstand without destruction. When thyristor is
switched on, conduction starts at a place near the gate. This small area of conduction spreads
di
rapidly and if rate of rise of anode current is large compared to the spreading velocity of
dt
carriers, local hotspots will be formed near the gate due to high current density. This causes
µ
the junction temperature to rise above the safe limit and the SCR may be damaged
di
permanently. The rating is specified in A sec .
dt

Gate Specifications

I GT : This is the required gate current to trigger the SCR. This is usually specified as a DC
value.

VGT : This is the specified value of gate voltage to turn on the SCR (dc value).

VGD : This is the value of gate voltage, to switch from off state to on state. A value below this
will keep the SCR in off state.

QRR : Amount of charge carriers which have to be recovered during the turn off process.

Rthjc : Thermal resistance between junction and outer case of the device.

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Gate Triggering Methods

Types
The different methods of gate triggering are the following
• R-triggering.
• RC triggering.
• UJT triggering.
3.5 Resistance Triggering
A simple resistance triggering circuit is as shown. The resistor R1 limits the current through
the gate of the SCR. R2 is the variable resistance added to the circuit to achieve control over
the triggering angle of SCR. Resistor ‘R’ is a stabilizing resistor. The diode D is required to
ensure that no negative voltage reaches the gate of the SCR.

vO
a b
LOAD

i R1

R2
vS=Vmsinωt
D VT

R Vg

Fig.3.4: Resistance firing circuit

VS VS VS
Vmsinωt

3π 4π 3π 4π 3π 4π
π 2π ωt π 2π ωt π 2π ωt

Vg Vgt Vg Vg
Vgp=Vgt gpV gt
>V

Vgp Vgp Vgt ωt ωt ωt

Vo Vo Vo
α
ωt ωt ωt
io io io

ωt 270
0 ωt ωt
VT VT VT

3π 4π
ωt π 2π ωt ωt
α 0 0
90
0 α=90 α<90
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(a) (b) (c)
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Fig.3.8: Resistance firing of an SCR in half wave circuit with dc load

(a) No triggering of SCR (b) α = 900 (c) α < 900

Design
Vm
With R2 = 0 , we need to ensure that < I gm , where I gm is the maximum or peak gate
R1
Vm
current of the SCR. Therefore R1 ≥ .
I gm

Also with R2 = 0 , we need to ensure that the voltage drop across resistor ‘R’ does not exceed
Vgm , the maximum gate voltage

Vm R
Vgm ≥
R1 + R
∴ Vgm R1 + Vgm R ≥ Vm R
∴ Vgm R1 ≥ R (Vm − Vgm )
Vgm R1
R≤
Vm − Vgm

Operation
Case 1: Vgp < Vgt

Vgp , the peak gate voltage is less then Vgt since R2 is very large. Therefore, current ‘I’ flowing
through the gate is very small. SCR will not turn on and therefore the load voltage is zero and
vscr is equal to Vs . This is because we are using only a resistive network. Therefore, output
will be in phase with input.
Case 2: Vgp = Vgt , R2 → optimum value.

When R2 is set to an optimum value such that Vgp = Vgt , we see that the SCR is triggered at
90 0 (since Vgp reaches its peak at 90 0 only). The waveforms shows that the load voltage is
zero till 90 0 and the voltage across the SCR is the same as input voltage till it is triggered at
90 0 .
Case 3: Vgp > Vgt , R2 → small value.

The triggering value Vgt is reached much earlier than 90 0 . Hence the SCR turns on earlier
than VS reaches its peak value. The waveforms as shown with respect to Vs = Vm sin ω t .

At ω t = α , VS = Vgt , Vm = Vgp (QVgt = Vgp sin α )

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 Vgt 
α = sin −1 
 V 
Therefore
 gp 
Vm R
But Vgp =
R1 + R2 + R

Vgt ( R1 + R2 + R ) 
Therefore α = sin −1  
 Vm R 

Since Vgt , R1 , R are constants

3.6 Resistance Capacitance Triggering

A. RC Half Wave
Capacitor ‘C’ in the circuit is connected to shift the phase of the gate voltage. D1 is used to
prevent negative voltage from reaching the gate cathode of SCR.
In the negative half cycle, the capacitor charges to the peak negative voltage of the supply
( −Vm ) through the diode D2 . The capacitor maintains this voltage across it, till the supply
voltage crosses zero. As the supply becomes positive, the capacitor charges through resistor
‘R’ from initial voltage of −Vm , to a positive value.

When the capacitor voltage is equal to the gate trigger voltage of the SCR, the SCR is fired
and the capacitor voltage is clamped to a small positive value.
v
O

LOAD
+
R
D2 VT

-
vS=Vmsinωt
D1
VC C

Fig.: RC half-wave trigger circuit

Vmsinωt Vmsinωt
vs vs
Vgt Vgt

-π/2 0 -π/2 0
0 ωt 0 ωt
vc vc
vc vc
a a a a
vo α α vo
Vm Vm
0
π 2π 3π ωt α ωt
vT vT

Vm
α α 0 3π ωt
-Vm ωt π 2π
α -Vm
(2π+α)

(a) (b)
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Fig.3.9: Waveforms for RC half-wave trigger circuit

(a) High value of R (b) Low value of R
Case 1: R → Large.
When the resistor ‘R’ is large, the time taken for the capacitance to charge from −Vm to Vgt is
large, resulting in larger firing angle and lower load voltage.
Case 2: R → Small
When ‘R’ is set to a smaller value, the capacitor charges at a faster rate towards Vgt resulting
in early triggering of SCR and hence VL is more. When the SCR triggers, the voltage drop
across it falls to 1 – 1.5V. This in turn lowers, the voltage across R & C. Low voltage across
the SCR during conduction period keeps the capacitor discharge during the positive half
cycle.

Design Equation
From the circuit VC = Vgt + Vd1 . Considering the source voltage and the gate circuit, we can
write vs = I gt R + VC . SCR fires when vs ≥ I gt R + VC that is vS ≥ I g R + Vgt + Vd 1 . Therefore
vs − Vgt − Vd 1
R≤ . The RC time constant for zero output voltage that is maximum firing angle
I gt
T 
for power frequencies is empirically gives as RC ≥ 1.3   .
2
B. RC Full Wave
A simple circuit giving full wave output is shown in figure below. In this circuit the
initial voltage from which the capacitor ‘C’ charges is essentially zero. The capacitor ‘C’ is
reset to this voltage by the clamping action of the thyristor gate. For this reason the charging
time constant RC must be chosen longer than for half wave RC circuit in order to delay the
50T v − Vgt
triggering. The RC value is empirically chosen as RC ≥ . Also R ≤ s .
2 I gt
vO

LOAD
+
+
D1 D3 R
VT

vd -

C
vS=Vmsinωt
D4 D2
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vs Vmsinωt vs Vmsinωt

ωt ωt

vd
vd vd

vc vc vgt vc ωt vgt ωt
vo vo
α α α
α
ωt ωt
vT vT

ωt
(a) (b)

Fig 3.10: RC full-wave trigger circuit Fig: Wave-forms for RC full-wave trigger circuit
(a) High value of R (b) Low value of R

PROBLEM
1. Design a suitable RC triggering circuit for a thyristorised network operation on a
220V, 50Hz supply. The specifications of SCR are Vgt min = 5V , I gt max = 30mA .

vs − Vgt − VD
R= = 7143.3Ω
Ig

Therefore RC ≥ 0.013

µ R ≤ 7.143k Ω
C ≥ 1.8199 F
3.7 UNI-JUNCTION TRANSISTOR (UJT)
B2 B2

Eta-point +
B2
RB2
Eta-point
RB2
p-type
E
E A A VBB
E +
RB1
n-type RB1
Ve Ie V η BB

- -
B1 B1 B1
(a) (b) (c)
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Fig.3.11: (a) Basic structure of UJT (b) Symbolic representation

(c) Equivalent circuit
UJT is an n-type silicon bar in which p-type emitter is embedded. It has three terminals
base1, base2 and emitter ‘E’. Between B1 and B2 UJT behaves like ordinary resistor and the
internal resistances are given as RB1 and RB 2 with emitter open RB B = RB1 + RB 2 . Usually the
p-region is heavily doped and n-region is lightly doped. The equivalent circuit of UJT is as
shown. When VBB is applied across B1 and B2 , we find that potential at A is

VBB RB1  RB1 

VAB1 = = ηVBB η = 
RB1 + RB 2  RB1 + RB 2 

is intrinsic stand off ratio of UJT and ranges between 0.51 and 0.82. Resistor RB 2 is
between 5 to 10KΩ.
Operation
When voltage VBB is applied between emitter ‘E’ with base 1 B1 as reference and the emitter
voltage VE is less than (VD + ηVBE ) the UJT does not conduct. (VD + ηVBB ) is designated as
VP which is the value of voltage required to turn on the UJT. Once VE is equal to
VP ≡ ηVBE + VD , then UJT is forward biased and it conducts.

The peak point is the point at which peak current I P flows and the peak voltage VP is across
the UJT. After peak point the current increases but voltage across device drops, this is due to
the fact that emitter starts to inject holes into the lower doped n-region. Since p-region is
heavily doped compared to n-region. Also holes have a longer life time, therefore number of
carriers in the base region increases rapidly. Thus potential at ‘A’ falls but current I E
increases rapidly. RB1 acts as a decreasing resistance.

The negative resistance region of UJT is between peak point and valley point. After valley
point, the device acts as a normal diode since the base region is saturated and RB1 does not
decrease again.

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Negative Resistance
Region
V
Cutoff e Saturation
region region
VBB
R load line
Vp
Peak Point

Valley Point

Vv

0 Ip Iv Ie

Fig.3.12: V-I Characteristics of UJT

3.8 UJT RELAXATION OSCILLATOR

UJT is highly efficient switch. The switching times is in the range of nanoseconds. Since UJT
exhibits negative resistance characteristics it can be used as relaxation oscillator. The circuit
diagram is as shown with R1 and R2 being small compared to RB1 and RB 2 of UJT.

Ve Capacitor Capacitor
ηVBB+V discharging
charging
VBB T2=R1C
Vp
R R2
B2 VP
E T1=RC Vv
VV

T t
C B1
Ve R1 v
o Vo
α1
ω

t
(a) (b)

Fig.3.13: UJT oscillator (a) Connection diagram and (b) Voltage waveforms
Operation
When VBB is applied, capacitor ‘C’ begins to charge through resistor ‘R’ exponentially
towards VBB . During this charging emitter circuit of UJT is an open circuit. The rate of
chargingτ is 1 = RC . When this capacitor voltage which is nothing but emitter voltage VE

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reaches the peak point VP = ηVBB + VD , the emitter base junction is forward biased and UJT
turns on. Capacitor ‘C’ rapidly discharges through load resistance R1 with time
constant τ 2 = R1C (τ 2 τ 1 ) . When emitter voltage decreases to valley point Vv , UJT turns off.
Once again the capacitor will charge towards VBB and the cycle continues. The rate of
charging of the capacitor will be determined by the resistor R in the circuit. If R is small the
capacitor charges faster towards VBB and thus reaches VP faster and the SCR is triggered at a
smaller firing angle. If R is large the capacitor takes a longer time to charge towards VP the
firing angle is delayed. The waveform for both cases is as shown below.
(i) Expression for period of oscillation‘t’
The period of oscillation of the UJT can be derived based on the voltage across the capacitor.
Here we assume that the period of charging of the capacitor is lot larger than than the
discharging time.
Using initial and final value theorem for voltage across a capacitor, we get

VC = V final + (Vinitial − V final ) e

−t
RC

t = T ,VC = VP ,Vinitial = VV ,V final = VBB

Therefore VP = VBB + (VV − VBB ) e−T / RC

 V −V 
⇒ T = RC log e  BB V 
 VBB − VP 
If
VV < VBB ,
 VBB 
T = RC ln  
 VBB − VP 
 
 1 
= RC ln  
1 − VP 
 VBB 

But VP = ηVBB + VD

If VD VBB VP = ηVBB

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 1 
Therefore T = RC ln  
1 − 
Design of UJT Oscillator
Resistor ‘R’ is limited to a value between 3 kilo ohms and 3 mega ohms. The upper limit on
‘R’ is set by the requirement that the load line formed by ‘R’ and VBB intersects the device
characteristics to the right of the peak point but to the left of valley point. If the load line fails
to pass to the right of the peak point the UJT will not turn on, this condition will be satisfied
V − VP
if VBB − I P R > VP , therefore R < BB .
IP

At the valley point I E = IV and VE = VV , so the condition for the lower limit on ‘R’ to ensure
VBB − VV
turn-off is VBB − IV R < VV , therefore R > .
IV

The recommended range of supply voltage is from 10 to 35V. the width of the triggering
pulse t g = RB1C .

In general RB1 is limited to a value of 100 ohm and RB 2 has a value of 100 ohm or greater
104
and can be approximately determined as RB 2 = .
ηVBB
PROBLEM
1. ηA UJT is used to trigger the thyristor whose minimum gate triggering voltage is 6.2V,
The UJT ratings are: = 0.66 , I p = 0.5mA , I v = 3mA , RB1 + RB 2 = 5k Ω , leakage
current = 3.2mA, Vp = 14v and Vv = 1V . Oscillator frequency is 2kHz and capacitor C
= 0.04µF. Design the complete circuit.
Solution

η T = R C ln  1 
C 1 − 
 
Here,
1 1
T= = , since f = 2kHz and putting other values,
f 2 × 103

1  1 
= RC × 0.04 ×10−6 ln   = 11.6 kΩ
2 ×103
 1 − 0.66 
η
The peak voltage is given as, Vp = VBB + VD

Let VD = 0.8 , then putting other values,

14 = 0.66VBB + 0.8

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VBB = 20V

The value of R2 is given by

0.7 ( RB 2 + RB1 )
R2 =
ηVBB

0.7 ( 5 ×103 )
R2 =
0.66 × 20
∴ R2 = 265Ω

Value of R1 can be calculated by the equation

VBB = I leakage ( R1 + R2 + RB1 + RB 2 )

20 = 3.2 ×10−3 ( R1 + 265 + 5000 )

R1 = 985Ω

The value of Rc( max ) is given by equation

VBB − V p
Rc( max ) =
Ip

20 − 14
Rc( max ) =
0.5 ×10−3
Rc( max ) = 12k Ω

Similarly the value of Rc( min ) is given by equation

VBB − Vv
Rc( min ) =
Iv

20 − 1
Rc( min ) =
3 ×10−3
Rc( min ) = 6.33k Ω

η µ
2. Design the UJT triggering circuit for SCR. Given −VBB = 20V , = 0.6 , I p = 10 A ,
Vv = 2V , I v = 10mA . The frequency of oscillation is 100Hz. The triggering pulse
µ
width should be 50 s .

Solution

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1 1
The frequency f = 100Hz, Therefore T = =
η f 100

 1 
From equation T = RcC ln  
 1− 
Putting values in above equation,

1  1 
= RcC ln  
100  1 − 0.6 
µ ∴ Rc C = 0.0109135

Let us select C = 1 F . Then Rc will be,

0.0109135
Rc( min ) =
1×10−6

Rc( min ) = 10.91k Ω .

η The peak voltage is given as,

Vp = VBB + VD

Let VD = 0.8 and putting other values,

Vp = 0.6 × 20 + 0.8 = 12.8V

The minimum value of Rc can be calculated from

VBB − Vv
Rc( min ) =
Iv

20 − 2
Rc( min ) = = 1.8k Ω
10 ×10−3
Value of R2 can be calculated from

104
R2 =
ηVBB

104
R2 = = 833.33Ω
0.6 × 20
Here the pulse width is give, that is 50µs.
Hence, value of R1 will be,

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µ
2 = R1C

The width τ 2 = 50 µ sec and C = 1 F , hence above equation becomes,

50 ×10−6 = R1 ×1×10−6

∴ R1 = 50Ω
µ
Thus we obtained the values of components in UJT triggering circuit as,
R1 = 50Ω , R2 = 833.33Ω , Rc = 10.91k Ω , C = 1 F .

3.9 Synchronized UJT Oscillator

A synchronized UJT triggering circuit is as shown in figure below. The diodes rectify
the input ac to dc, resistor Rd lowers Vdc to a suitable value for the zener diode and UJT. The
zener diode ‘Z’ functions to clip the rectified voltage to a standard level VZ which remains
constant except near Vdc = 0 . This voltage VZ is applied to the charging RC circuit. The
capacitor ‘C’ charges at a rate determined by the RC time constant. When the capacitor
reaches the peak point VP the UJT starts conducting and capacitor discharges through the
primary of the pulse transformer. As the current through the primary is in the form of a pulse
the secondary windings have pulse voltages at the output. The pulses at the two secondaries
feed SCRs in phase. As the zener voltage VZ goes to zero at the end of each half cycle the
synchronization of the trigger circuit with the supply voltage across the SCRs is archived,
small variations in supply voltage and frequency are not going to effect the circuit operation.
In case the resistor ‘R’ is reduced so that the capacitor voltage reaches UJT threshold voltage
twice in each half cycle there will be two pulses in each half cycle with one pulse becoming
redundant.
R1
+ +

i1 R R2
D1 D3
B2
Pulse Transf
+ E
Vdc Z VZ
B1 G1
C1 To SCR
vc C Gates
G2
D4 D2
C2
- - -

Fig.3.14: Synchronized UJT trigger circuit

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Digital Firing Circuit

Fig.3.15: Block diagram of digital firing circuit
A A
Preset
(’N’ no. of counting bits)
Logic circuit
Clk B +
Fixed frequency max G1
n-bit Flip - Flop Modulator
Oscillator
Counter min S (F / F) B +
(ff) G2
Driver stage
En R
Reset Reset
Load

fC y(’1’ or ‘0’)
Sync Carrier
Signal (~6V) Frequency
ZCD Oscillator
C ( ∼ 10KHz)
D.C. 5V
supply

A A

vc,
vdc VZ Vdc

ηVZ

vc vc vc ωt
Pulse
Voltage
1 2 1 2 1 2

α α ωt
ω ω

Fig.3.16: Generation of output pulses for the synchronized UJT trigger circuit

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fc
A I To
G1 Driver
B J Circuit
G1=[Link]
A 0.1µF
B
H
y
Logic Circuit Modulator
fc
To
A G2 Driver
B K Circuit
G2=[Link]
A 0.1µF
B
y
Fig.3.17: Logic circuit, Carrier Modulator

The digital firing scheme is as shown in the above figure. It constitutes a pre-settable
counter, oscillator, zero crossing detection, flip-flop and a logic control unit with NAND and
AND function.
Oscillator: The oscillator generates the clock required for the counter. The frequency of the
clock is say f C . In order to cover the entire range of firing angle that is from 00 to 1800, a n-
bit counter is required for obtaining 2n rectangular pulses in a half cycle of ac source.
Therefore 4-bit counter is used, we obtain sixteen pulses in a half cycle of ac source.
Zero Crossing Detector: The zero crossing detector gives a short pulse whenever the input ac
signal goes through zeroes. The ZCD output is used to reset the counter, oscillator and flip-
flops for getting correct pulses at zero crossing point in each half cycle, a low voltage
synchronized signal is used.
Counter: The counter is a pre-settable n-bit counter. It counts at the rate of f C pulses/second.
In order to cover the entire range of firing angle from 0 to 1800 , the n-bit counter is required
for obtaining 2n rectangular pulses in a half cycle.
Example: If 4-bit counter is used there will be sixteen pulses / half cycle duration. The
counter is used in the down counting mode. As soon as the synchronized signal crosses zero,
the load and enable become high and low respectively and the counter starts counting the
clock pulses in the down mode from the maximum value to the pre-set value ‘N’. ‘N’ is the
binary equivalent of the control signal. once the counter reaches the preset value ‘N’ counter
overflow signal goes high. The counter overflow signal is processed to trigger the Thyristors.
Thus by varying the preset input one can control the firing angle of Thyristors. The value of
firing angle (α ) can be calculated from the following equation

 2n − N   N
α =  180 =  1 − 180 ( for n = 4 )
0 0
n
 2   16 

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Modified R-S Flip-Flop: The reset input terminal of flip-flop is connected to the output of
ZCD and set is connected to output of counter. The pulse goes low at each zero crossing of
the ac signal. A low value of ZCD output resets the B-bar to 1 and B to 0.
A high output of the counter sets B-bar to 0 and B to 1. This state of the flip-flop is latched
till the next zero crossing of the synchronized signal. The output terminal B of flip-flop is
connected with enable pin of counter. A high at enable ‘EN’ of counter stops counting till the
next zero crossing.

Input Output Remarks

R S B B-bar
1 1 1 0
0 1 1 0 Set
0 0 0 1 Reset
1 0 0 1 Last Stage
1 1 1 0
Truth Table of Modified R-S Flip-Flop

Logic Circuit, Modulation and Driver Stage: The output of the flip-flop and pulses A and A-
bar of ZCD are applied to the logic circuit. The logic variable Y equal to zero or one enables
to select the firing pulse duration from α to π or α
Overall Operation
The input sinusoidal signal is used to derive signals A and A-bar with the help of ZCD. The
zero crossing detector along with a low voltage sync signal is used to generate pulses at the
instant the input goes through zeroes. The signal C and C-bar are as shown. The signal C-
bar is used to reset the fixed frequency oscillator, the flip flop and the n-bit counter. The
fixed frequency oscillator determines the rate at which the counter must count. The counter is
preset to a value N which is the decimal equivalent of the trigger angle. The counter starts to
down count as soon as the C-bar connected to load pin is zero. Once the down count N is
over the counter gives a overflow signal which is processed to be given to the Thyristors.
This overflow signal is given to the Set input S of the modified R-S flip flop. If S=1 B goes
high as given by the truth table and B –bar has to go low. B has been connected to the Enable
pin of counter. Once B goes low the counter stops counting till the next zero crossing. The
carrier oscillator generates pulses with a frequency of 10kHz for generating trigger pulses for
the Thyristors. Depending upon the values of A, A-bar, B, B-bar and Y the logic circuit will
generate triggering pulses for gate1 or gate 2 for Thyristors 1 and 2 respectively.

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dv
PROTECTION
3.10 dt
dv
The across the thyristor is limited by using snubber circuit as shown in figure (a) below.
dt
If switch S1 is closed at t = 0 , the rate of rise of voltage across the thyristor is limited by the
capacitor CS . When thyristor T1 is turned on, the discharge current of the capacitor is limited
by the resistor RS as shown in figure (b) below.

Fig.3.18 (a)

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Fig.3.18 (b)

Fig.3.18 (c)
The voltage across the thyristor will rise exponentially as shown by fig (c) above. From fig.
(b) above, circuit we have (for SCR off)
1
VS = i ( t ) RS + i ( t ) dt + Vc ( 0 )[ for t =0] .
C∫

τ −t
V
Therefore i ( t ) = S e τ s , where s = RS CS
RS

Also VT ( t ) = VS − i ( t ) RS

VS − t τ s
VT ( t ) = VS − e RS
RS
−t
 −t

Therefore VT ( t ) = VS − VS e τs
= VS 1 − e τ s 
 

At t = 0, VT ( 0 ) = 0

At t = τ s , VT (τ s ) = 0.632VS

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dv VT (τ s ) − VT ( 0 ) 0.632VS
Therefore = =
dt τs RS CS

VS
And RS = .
ITD

ITD is the discharge current of the capacitor.

dv
It is possible to use more than one resistor for and discharging as shown in the
dt
dv
figure (d) below. The is limited by R1 and CS . R1 + R2 limits the discharging current
dt
VS
such that ITD =
R1 + R2

Fig.3.18 (d)
The load can form a series circuit with the snubber network as shown in figure (e) below.
The damping ratio of this second order system consisting RLC network is given as,

α RS + R CS
δ= = , where LS stray inductance and L, R is is load inductance
ω0 2 LS + L
and resistance respectively.
To limit the peak overshoot applied across the thyristor, the damping ratio should be in the
range of 0.5 to 1. If the load inductance is high, RS can be high and CS can be small to retain
the desired value of damping ratio. A high value of RS will reduce discharge current and a

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low value of CS reduces snubber loss. The damping ratio is calculated for a particular circuit
RS and CS can be found.

Fig.3.18 (e)

di
PROTECTION
3.11 dt

di
Practical devices must be protected against high . As an example let us consider the
dt
circuit shown above, under steady state operation Dm conducts when thyristor T1 is off. If T1
di
is fired when Dm is still conducting can be very high and limited only by the stray
dt
di
inductance of the circuit. In practice the is limited by adding a series inductor LS as
dt
di V
shown in the circuit above. Then the forward = S .
dt LS

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Recommended questions:

1 Distinguish between latching current and holding current.

2. Converter grade and inverter grade thyristors
3. Thyristor turn off and circuit turn off time
4. Peak repetitive forward blocking voltage i2 t rating
5. Explain the turn on and turn of dynamic characteristics of thyristor
6. A string of series connected thyristors is to withstand a DC voltage of 12 KV. The
maximum leakage current and recovery charge differences of a thyristors are 12 mA and
120 µC respectively. A de-rating factor of 20% is applied for the steady state and
dynamic (transient) voltage sharing of the thyristors. If the maximum steady sate voltage
is 1000V, determine 1) the steady voltage sharing resistor R for each thyristor. 2) the
transient voltage capacitor C1 for each thryristor
7. A SCR is to operate in a circuit where the supply voltage is 200 VDC. The dv/dt should
be limited to 100 V/ µs. Series R and C are connected across the SCR for limiting dv/dt.
The maximum discharge current from C into the SCR, if and when it is turned ON is to
be limited to 100 A. Using an approximate expression, obtain the values of R and C.
8. With the circuit diagram and relevant waveforms, discuss the operation of synchronized
UJT firing circuit for a full wave SCR semi converter.
9. Explain gate to cathode equivalent circuit and draw the gate characteristics. Mark the
operating region.
10. Mention the different turn on methods employed for a SCR
11. A SCR is having a dv/dt rating of 200 V/µs and a di/dt rating of 100 A/µs. This SCR is
used in an inverter circuit operating at 400 VDC and has 1.5Ω source resistance. Find the
values of snubber circuit components.
12. Explain the following gate triggering circuits with the help of waveforms: 1) R –
triggering 2) RC – triggering.

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