NATIONAL UNIVERSITY OF HO CHI MINH CITY

UNIVERSITY OF INFORMATION TECHNOLOGY

FACULTY OF COMPUTER ENGINEERING

CHAPTER 8 FINITE STATE MACHINES

Lecturer: Ho Ngoc Diem

 Agenda
 Chapter 1: Introduction
 Chapter 2: Modules and hierarchical structure
 Chapter 3: Fundamental concepts
 Chapter 4: Structural modeling (Gate & switch-level modeling)
 Chapter 5: Dataflow modeling (Expression)
 Chapter 6: Behavioral modeling
 Chapter 7: Tasks and Functions
 Chapter 8: Finite state machines
 Chapter 9: Testbench and verification
 Chapter 10: VHDL introduction

UIT Circuit Design with HDL - Chapter 8 2

 Introduction
 Finite State Machines (FSMs): a useful abstraction for
digital logic circuits with centralized “states” of operation
 Three basic components:
- Combinational logic – next state
- Sequential logic – store state
- Output logic

UIT Circuit Design with HDL - Chapter 8 3

Finite state machine (FSM)
 At each clock edge, combinational logic computes
outputs and next state as a function of inputs and
present state

UIT Circuit Design with HDL - Chapter 8 4

FSM Approaches
 There are two styles of designing finite state machines
 Moore type:
The output is a function of only the current state
 Mealy type:
The output is a function of the current state and inputs

UIT Circuit Design with HDL - Chapter 8 5

Moore vs Mealy types

Next state = F (current state, inputs)

Outputs = G (current state)

Next state = F (current state, inputs)

Outputs = G (current state, inputs)

UIT Circuit Design with HDL - Chapter 8 6

Moore vs Mealy types
Moore type example

UIT Circuit Design with HDL - Chapter 8 7

Moore vs Mealy types
Mealy type example

UIT Circuit Design with HDL - Chapter 8 8

Constructing State Machines
 Current state
- Register to hold: always @(posedge clk) block
 Next state
- State by state case analysis: next state determined by
current state and given inputs
 Output function
State by state analysis:
- Moore: output determined by current state only
- Mealy: output determined by current state and inputs

UIT Circuit Design with HDL - Chapter 8 9

 Constructing State Machines (con’t)
 Model FSM:
 Decide how many states are needed, which transitions are
possible from one state to another
Using constants declaration like parameter or `define to
define name of states in FSM makes code more readable and easy
to manage.

 Reset state

 “always @ (posedge clock)” defines the state registers

 Combinational logic defines the next state and output logic

UIT Circuit Design with HDL - Chapter 8 10

 Constructing State Machines (con’t)
 Encoding state style:
- Binary (usually used)
- One hot (usually used)
- One cold
- Almost one hot
- Almost one cold
- Gray

UIT Circuit Design with HDL - Chapter 8 11

 Example: Moore 101 detector
 Moore 101 detector

1st approach
output z

Ref: Verilog Digital System Design – Zainalabedin Navabi

UIT Circuit Design with HDL - Chapter 8 12

 Example: Moore 101 detector
module moore_detector (input x, rst, clk, output z);
localparam [1:0] got10: begin
reset=0, got1=1, got10=2, got101=3; if ( x==1’b1 ) current <= got101;
reg [1:0] current; else current <= reset;
always @ (posedge clk ) begin end
if ( rst ) current <= reset; got101: begin
else case ( current ) if (x==1’b1 ) current <= got1;
reset: begin else current <= got10;
if( x==1’b1 ) current <= got1; end
else current <= reset; default:
end current <= reset;
got1: begin endcase
if( x==1’b0 ) current <= got10; end
else current <= got1; assign z = (current==got101) ? 1 : 0;
end endmodule

UIT Circuit Design with HDL - Chapter 8 13

 Example: Moore 101 detector
module moore_detector (input x, rst, clk, output z);
` define reset 2’b00 `got10: begin
` define got1 2’b01 If ( x==1’b1 ) current <= `got101;
` define got10 2’b10 else current <= `reset;
` define got101 2’b11 end
reg [1:0] current; `got101: begin
always @ (posedge clk ) begin If (x==1’b1 ) current <= `got1;
if ( rst ) current <= `reset; else current <= `got10;
else case ( current ) end
`reset: begin default:
if( x==1’b1 ) current <= `got1; current <= `reset;
else current <= `reset; endcase
end end
`got1: begin //--------- output ---------------
if( x==1’b0 ) current <= `got10; assign z = (current==`got101) ? 1 : 0;
else current <= `got1; endmodule
end

UIT Circuit Design with HDL - Chapter 8 14

Example: Moore 101 detector
2nd approach

UIT 15
 Example: Moore 101 detector
module moore_detector (input x, rst, clk, output z);
localparam [1:0] got101:
reset=0, got1=1, got10=2, got101=3; if (x) next_state = got1;
reg [1:0] state, next_state; else next_state = got10;
//Combinational Next State Logic default:
always @(state or x) next_state = reset;
case (state) endcase // case(state)
reset: //State FF Transition
if (x) next_state = got1; always @(posedge clk)
else next_state = reset; if (rst == 1)
got1: state <= reset;
if (x) next_state = got1; else
else next_state = got10; state <= next_state;
got10: //Combinational Output Logic
if (x) next_state = got101; assign found = (state == got101) ? 1: 0;
else next_state = reset; endmodule // Moore101 Detector
UIT Circuit Design with HDL - Chapter 8 16
Example: Moore 101 detector
3rd approach

UIT 17
 Example: Moore 101 detector
got10: begin
module moore_detector (input x, rst, clk, output reg z); if( x==1’b1 ) n_state = got101;
localparam [1:0] reset=0, got1=1, got10=2, got101=3; else n_state = reset;
reg [1:0] p_state, n_state; z = 1’b0;
end
always @ ( p_state or x ) begin: combinational got101: begin
n_state = reset; if( x==1’b1 ) n_state = got1;
z = 1’b0; else n_state = got10;
case ( p_state ) z = 1’b1;
reset: begin end
if( x==1’b1 ) n_state = got1; default: begin
else n_state = reset; n_state = reset;
z = 1’b0; z = 1’b0;
end end
got1: begin endcase
end
if( x==1’b0 ) n_state = got10;
always @ (posedge clk ) //sequential
else n_state = got1;
if( rst ) p_state <= reset;
z = 1’b0; else p_state <= n_state;
end endmodule

UIT Circuit Design with HDL - Chapter 8 18

Example: Mealy 101 detector
input x
output z

UIT Circuit Design with HDL - Chapter 8 19

Example: Mealy 101 detector
module mealy_detector (input x, rst, clk, output z);
localparam [1:0] reset = 0, got1 = 1, got10 = 2;
reg [1:0] current;
always @ (posedge clk ) begin
if (rst) current <= reset;
else case ( current )
reset:
if( x==1’b1 ) current <= got1; default:
else current <= reset; current <= reset;
got1: endcase
if( x==1’b0 ) current <= got10; end
else current <= got1; assign z = ( current==got10 && x==1’b1)?
got10: 1’b1 : 1’b0;
if( x==1’b1 ) current <= got1; endmodule
else current <= reset;

UIT Circuit Design with HDL - Chapter 8 20

 Example: Mealy 101 detector
 Another approach
module mealy_detector (input x, rst, clk, output z);
localparam [1:0] reset = 0, got1 = 1, got10 = 2; default:
reg [1:0] state, next_state; next_state = reset;
//Combinational Next State Logic endcase // case(state)
always @(state or x)
case (state) //State FF Transition
reset: always @(posedge clk)
if (x) next_state = got1; if (rst == 1)
else next_state = reset; state <= reset;
got1: else
if (x) next_state = got1; state <= next_state;
else next_state = got10;
got10: //Combinational Output Logic
if (x) next_state = got1; assign z = (state == got10 && x == 1) ?
else next_state = reset; 1: 0;
endmodule // Mealy101Detector
UIT Circuit Design with HDL - Chapter 8 21
Typical Example of FSM
 Objectives:
- Build an electronic combination lock with a reset
button, two number buttons – 0 and 1, and an
unlock output.
- The combination should be 01011
 Step:
1. Design lock FSM: block diagram, state transitions
2. Write verilog module(s) for FSM

UIT Circuit Design with HDL - Chapter 8 22

STEP 1A - Block Diagram

UIT Circuit Design with HDL - Chapter 8 23

STEP 1B – State Transition Diagram

UIT Circuit Design with HDL - Chapter 8 24

STEP 2 – Write Verilog

UIT Circuit Design with HDL - Chapter 8 25

STEP 2 – State Transition Diagram

UIT Circuit Design with HDL - Chapter 8 26

STEP 2 – Final Implementation Verilog

UIT Circuit Design with HDL - Chapter 8 27

 Tips on FSM
 Don’t forget to handle the “default” for case statement
 Use two different always blocks for next state and current state circuit
Can do it in one big block but not as clear
 Outputs can be a mix of combin. and seq.
Moore machine: Output only depends on current state
Mealy machine: Output only depends on current state and inputs

UIT Circuit Design with HDL - Chapter 8 28